S6BT112A02SSB1002 [CYPRESS]
Interface Circuit;
| 型号： | S6BT112A02SSB1002 |
| 厂家： | 
CYPRESS |
| 描述： | Interface Circuit 接口集成电路 |
| 文件： | 总40页 (文件大小：1252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
S6BT112A01/S6BT112A02
ASSP
CXPI Transceiver IC for Automotive Network
The S6BT112A01 and S66BT112A02 are integrated transceiver IC for Automotive communication network with Clock extension
Peripheral Interface (CXPI). It is flexible bit rate from 2.4 k bit per second to 20 k bit per second with JASO CXPI compliant. This
CXPI transceiver IC connect between CXPI data link controller and CXPI Bus line, and enables to connect to vehicle battery directly,
with high surge protection. Additionally products have optional function for Spread Spectrum Clock Generator (SSCG).
In the standby operation, S6BT112A01 and S6BT112A02 success ultra low power consumption as sleep mode. The Cypress CXPI
transceiver IC supports master node and slave node as selected SELMS pin.
Features
Compliant with the JASO CXPI (JASO D 015-3-15) standard
Compliant with the SAE CXPI ( J3076_201510) standard
Supported bitrate 2.4kbps to 20kbps
Easy selected master node or slave node.
Over temperature protection
Low voltage detection.
Waveshaping for low Electromagnetic Interference (EMI)
Operating Voltage Range 5.3V to 18V
Supported Sleep and Wakeup
Sleep mode current :6uA(Typical @Slave)
Halogen free package 8pin SOIC
ESD protection HBM (1.5kΩ 100pF) ±8kV (BUS pin, BAT pin)
Voltage tolerance ±40V (BUS pin)
Direct battery operation with protection against load dump,
jump start and transients
BUS short to VBAT over current protection.
Loss of ground protection. BUS pin leakage is lower than
±1mA.
S6BT112A01: With spread spectrum clock generator.
S6BT112A02: Without spread spectrum clock generator.
Block Diagram
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Document Number: 002-10203 Rev.*A
Revised April 6, 2016
PRELIMINARY
S6BT112A01/S6BT112A02
Table of Contents
Features
............................................................................................................................................................. 1
............................................................................................................................................................. 1
............................................................................................................................................................. 3
............................................................................................................................................................. 4
Block Diagram
1. Applications
2. Pin Assignment
3. Pin Descriptions ............................................................................................................................................................. 5
4. Block Diagram ............................................................................................................................................................. 6
5. Function Description.......................................................................................................................................................... 7
5.1
5.2
Operation Modes........................................................................................................................................................... 7
Master node .................................................................................................................................................................. 8
5.2.1 Normal mode.................................................................................................................................................................. 8
5.2.2 Sleep mode.................................................................................................................................................................... 9
5.2.3 Standby mode.............................................................................................................................................................. 10
5.2.4 Power-on Sequence..................................................................................................................................................... 10
5.3
Slave node .................................................................................................................................................................. 12
5.3.1 Normal mode................................................................................................................................................................ 12
5.3.2 Sleep mode.................................................................................................................................................................. 13
5.3.3 Standby........................................................................................................................................................................ 15
5.3.4 Power-on Sequence..................................................................................................................................................... 15
5.4
Common function ........................................................................................................................................................ 16
5.4.1 Over temperature protection ........................................................................................................................................ 16
5.4.2 Low voltage reset......................................................................................................................................................... 18
5.4.3 Over current protection ................................................................................................................................................ 19
5.4.4 Secondary Clock Master.............................................................................................................................................. 19
5.4.5 Arbitration..................................................................................................................................................................... 21
5.4.6 TXD Toggle.................................................................................................................................................................. 22
6. Absolute Maximum Ratings............................................................................................................................................. 24
7. Recommended Operating Conditions ............................................................................................................................ 25
8. Electrical Characteristics................................................................................................................................................. 26
9. Ordering Information........................................................................................................................................................ 37
10. Package Dimensions...................................................................................................................................................... 38
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PRELIMINARY
S6BT112A01/S6BT112A02
1. Applications
Typical applications of S6BT112A01 or S6BT112A02
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S6BT112A01/S6BT112A02
2. Pin Assignment
Figure 2-1 Pin Assignment
(TOP VIEW)
RXD
SELMS
1
2
3
4
8
7
6
5
BAT
BUS
GND
NSLP
CLK
TXD
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S6BT112A01/S6BT112A02
3. Pin Descriptions
Table 3-1 Pin Descriptions
Pin
Symbol
Number
Direction
Descriptions
Receive data output (open-drain).
1
RXD
Output
External pull-up resistor is required. (refer to Table 7-1 )
Sleep control input.
Low: Sleep mode or Standby mode
High: Normal mode.
2
NSLP
Input
Detail refer to section 5.2.2 or section 5.3.2
When the SELMS pin was Low, the CLK pin is Baud late clock input.
Input clock signal with baud rate frequency.
(When input clock frequency was 20kHz , bit rate is 20kbps)
When the SELMS pin was High, the CLK pin is Baud late clock output.
Outputs clock signal with baud rate frequency.
(When input clock frequency was 20kHz , bitrate is 20kbps)
Open drain output.
3
CLK
I/O
External pull-up resistor is required. (refer to Table 7-1)
4
5
6
7
TXD
GND
BUS
BAT
Input
Transmit data input
-
I/O
-
Ground
CXPI BUS line Input/Output
Battery (voltage source) supply.
Master / slave node select input.
Low : Master
8
SELMS
Input
High : Slave
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S6BT112A01/S6BT112A02
4. Block Diagram
Figure 4-1 Block Diagram
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PRELIMINARY
S6BT112A01/S6BT112A02
5. Function Description
5.1 Operation Modes
Figure 5-1 State Transition Diagram
Notes
[0] : “Hi-z” means High impedance.
[1] : Switching of the master / slave during operation is prohibited. Please refer to “5.4.4 Secondary Clock master”.
[2] : Don't power on with the Normal mode. Transceiver must power on with sleep mode
[3] : If TXD is Low when releasing Thermal shutdown, TXD have to toggle "High" before valid.
TXD is Low signal inputs. For detail, please refer to “5.4.6 TXD Toggle”
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S6BT112A01/S6BT112A02
5.2 Master node
Only one node in a system having function of schedule management and a primary clock master.
Transceiver works as Master mode when Low level is applied on SELMS.
Baud rate clock is applied on CLK pin in Master state.
Usually transceiver is used to the "Master" or "Slave". However, except for the “Secondary Clock master function”.
SELMS input should not be changed in normal mode.
SELMS input should not be changed during wakeup pulse transmission in sleep mode.
The CLK pin inputs for baud rate clock in Master state.
Table 5-1 SELMS Pin State for master
Pin
Input Signal
Master/Slave
SELMS
Low
Master
Figure 5-2 CLK Input -> BUS signal (Master)
5.2.1
Normal mode
The Normal mode denotes the state to which the communication is possible.
The master node transmits clock to CXPI BUS. It’s means the “clock master”.
During the Normal mode the transmitted signal is encoded and the received signal is decoded.
When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after converting the data to UART format by
1 byte.
The data is transmitted to the CXPI BUS as LSB first.
When the receiving node receive data from the CXPI BUS , it revise from the RXD pin as UART format by 1byte.
The UART format is refer to Table 5-2 UART Format
Refer to the JASO CXPI (JASO D 015-3:2015) standard details of the operation.
Table 5-2 UART Format
Start bit bit 0 (LSB) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7(MSB) Stop bit
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S6BT112A01/S6BT112A02
5.2.2
Sleep mode
The Sleep mode denotes the state of the power saving to which each node stopped transmitting and receiving of data. All nodes
transition to Sleep mode after power-on. Other than immediately after power-on, they also transition to Sleep mode after the Sleep
processing was executed from the Normal mode and transition from Standby mode or Normal mode due to the CXPI BUS error.
During the Sleep mode, when each node receives the Wakeup factor, it transitions to the Standby mode.
The Wakeup factor is described per the system and is composed of the internal factor (e.g. detecting that the ignition has been
turned on) and the external factor that receives the Wakeup pulse from the CXPI BUS.
During the Sleep mode, the reception signal is received without decoding. MCU can detect a wake-up pulse width monitor the RXD
signal.
The sleep mode is initiated by a falling edge on the NSLP pin while TXD is already set High. The CXPI BUS transmit path is
immediately disabled when the NSLP pin goes Low.
All wake-up events must be maintained for a specific period (TMODE_CHG, Table 8-7).
Table 5-3 Transition from Normal to Sleep mode
Pin
TXD
Pin State
High
Descriptions
No data transmitting
CLK
High
No clock receiving
NSLP
RXD
High to Low
High impedance
High impedance
Low
-
High level with external pullup resistor.
BUS
High level with external pullup resistor.
SELMS
-
Notes : The “Pin State” indicates before the falling edge in the NSLP pin
Table 5-4 Transition from Sleep to Normal mode
Pin
TXD
Pin State
High
Descriptions
No data transmitting
CLK
High
No clock receiving
NSLP
RXD
Low to High
High impedance
High impedance
Low
-
High level with external pullup resistor.
BUS
High level with external pullup resistor.
SELMS
-
Notes : Table 5-4The “Pin State” indicates before the rising edge in the NSLP pin
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Figure 5-3 Transition Sequence Between Sleep and Normal mode
Notes:
[0] “Hi-Z” means High impedance.
Table 5-5 Bitrate of 20Kbps (50us/Bit)
UART Receive Data Number of Bits of L Level Wakeup Pulse Width
FCH
F8H
F0H
E0H
C0H
80H
00H
3bit
4bit
5bit
6bit
7bit
8bit
9bit
150us
200us
250us
300us
350us
400us
450us
5.2.3
Standby mode
The Standby mode denotes prepared state to the Normal mode after releasing the Sleep mode. During the state CLK (in slave
node), the RXD pin and the BUS pin become High impedance state. After "TMODE_CHG," state is changed to the Normal mode.
5.2.4
Power-on Sequence
At power-up, setting up Sleep mode. When VBAT is above 5.3V, the NSLP pin should be High state.
After transition to the normal mode, To activate the BUS pin after the clock input of the 33 periods.
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S6BT112A01/S6BT112A02
Figure 5-4 Power-on Sequence of Master node
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5.3 Slave node
Each node other than master node connected with system
Transceiver works as Slave when High level is applied on SELMS.
The CLK pin outputs baud rate clock in Slave state.
Usually transceiver is used to the "Master" or "Slave". However, except for the “Secondary Clock master function”.
Table 5-6 SELMS Pin State for salve
Pin
Input Signal
Master/Slave
SELMS
High
Slave
SELMS input should not be changed in the Normal mode.
SELMS input should not be changed during wakeup pulse transmission in the Sleep mode.
The CLK pin outputs baud rate clock in Slave node.
Figure 5-5 CLK Pin Clock Output (Slave)
5.3.1
Normal mode
The Normal mode that can perform data transmitting and receiving.
During the Normal mode the signal that is transmitted is encoded and the signal that is received is decoded.
When the transmitting node transmits data to the CXPI BUS, it transmits to the TXD pin after converting the data to UART format by
1 byte.
The data is transmitted to the CXPI BUS by LSB first.
When the receiving node receive data from the CXPI BUS , it revise from the RXD pin as UART format by 1byte.
The UART format is shown in Table 5-7 UART Format
Refer to the JASO CXPI (JASO D 015-3:2015) standard details of the operation.
Table 5-7 UART Format
Start bit bit 0 (LSB) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7(MSB) Stop bit
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S6BT112A01/S6BT112A02
5.3.2
Sleep mode
The Sleep mode denotes the state of the power saving to which each node stopped transmitting and receiving of data. All nodes
transition to the Sleep mode after power-on. Other than immediately after power-on, they also transition to the Sleep mode after the
sleep processing was executed from the Normal mode and transition from the Standby mode or the Normal mode due to the CXPI
BUS error.
During the Sleep mode, when each node receives the Wakeup factor, it transitions to the Standby mode.
The Wakeup factor is described per the system and is composed of the internal factor (e.g. detecting that the ignition has been
turned on) and the external factor that receives the Wakeup pulse from the CXPI BUS.
During the Sleep mode, the reception signal is received without decoding.
The sleep mode is initiated by a falling edge on the NSLP pin while the TXD pin is already set High. The CXPI BUS transmit path is
immediately disabled when the NSLP pin goes Low.
All wake-up events must be maintained for a specific period (TMODE_CHG, Table 8-7).
Figure 5-6 Transition Sequence Between Sleep and Normal mode
Table 5-8 Transition from Normal to Sleep mode
Pin
TXD
Pin State
High
Descriptions
No data transmitting
CLK
High impedance
High to Low
High impedance
High impedance
High
High level with external pullup resistor.
NSLP
RXD
-
High level with external pullup resistor.
BUS
High level with external pullup resistor.
SELMS
-
Notes: The “Pin State” indicates before the falling edge in the NSLP pin.
Table 5-9 Transition from Sleep to Normal mode
Pin
TXD
Pin State
High
Descriptions
No data transmitting
CLK
High impedance
Low to High
High impedance
High impedance
High
High level with external pullup resistor.
NSLP
RXD
-
High level with external pullup resistor.
BUS
High level with external pullup resistor.
SELMS
-
Notes: The “Pin State” indicates before the rising edge in the NSLP pin.
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S6BT112A01/S6BT112A02
■Receiver function in Sleep mode
During the Sleep mode, it will be output from CLK pin without decoding a received signal. The RXD pin outputs High level.
When Master node transmits encoded PWM clock signal to CXPI BUS in wake-up sequence, Slave MCUs receive shorter Low level
width signal than UART communication period and possibly get errors. Because Slave-node received without decoding. To avoid
these errors, S6BT112A01 or S6BT112A02 CXPI transceiver IC outputs received signal on CLK pin in the Sleep mode.
MCU can detect a wake-up pulse width monitor the CLK signal. (Figure 5-7)
Figure 5-7 CLK Output of Receive Signal、RXD stays High (for Slave node)
■Wakeup function
The WakeupPulseOutput state that transmits out wakeup pulse in the Slave node.
The slave device returns from the Sleep mode must transmit a wake-up pulse.
At the NSLP pin is Low state, the TXD pin transmitted Low state. The TXD signal is transmitted to the BUS pin without encode.
The TXD pin outputs signal width which is a value obtained by subtracting the TTXD_BT
Figure 5-8 Wake-Up Pulse Transmission
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S6BT112A01/S6BT112A02
5.3.3
Standby mode
The standby state to the Normal mode after releasing the Sleep mode. During the state CLK (in slave node), the RXD pin and the
BUS pin become High impedance state. After "TMODE_CHG," state is changed to the Normal mode.
5.3.4
Power-on Sequence
At power-up, setting up the Sleep mode. When VBAT is above 5.3V, the NSLP pin should be High state.
Figure 5-9 Power-on Sequence of Slave node
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S6BT112A01/S6BT112A02
5.4 Common function
5.4.1 Over temperature protection
The over temperature protection monitors the die temperature. If the junction temperature exceeds the shutdown junction
temperature, TSD_H, the thermal protection circuit disables the output driver.
The driver is enabled again when the junction temperature falls below TSD_L and theTXD pin is toggled. (Table 5-10)
WP_ThermalShutdown
The WP_ThermalShutdown state that detecting "Shutdown temperature" in WakeupPulseOutput mode.
The over temperature protection is inactive in the Sleep mode.
Table 5-10 Input Signal Change after Recovery from thermal shutdown
Master/Slave
Pin
Toggle of Input Signal
Master
TXD
required
Slave
TXD
required
Table 5-11 State Under thermal shutdown
Master/Slave Pin
Descriptions
TXD
Normal function
NSLP
CLK(input)
RXD
High: Normal mode / Low: Sleep mode(Thermal protection inactive)
Master
Normal function
Normal function
BUS
High impedance
TXD
Normal function
NSLP
CLK
High: Normal mode / Low: Sleep mode (Thermal protection inactive)
Slave
Normal function
Normal function
High impedance
RXD
BUS
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PRELIMINARY
S6BT112A01/S6BT112A02
Figure 5-10 Sequence of thermal shutdown
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S6BT112A01/S6BT112A02
5.4.2
Low voltage reset
The LowVoltageReset state by detecting low voltage of the BAT pin.
This device has an integrated Power - On reset at the supply BAT and Low Voltage detection at the supply BAT.
In case the supply voltage VBAT is dropping below the Power-On reset level VBAT<VPOR_L,change the LowPowerReset mode.
In LowPowerReset mode the output stage is disabled and no communication to the CXPI BUS is possible.
If the power supply VBAT reaches a higher level as the Low Voltage reset level VBAT> VPOR_H, change the Standby-mode(the NSLP
pin is High) or Sleep-mode(the NSLP pin is Low).
After releasing LowPowerRest mode, do the Power-up sequence.
Table 5-12 Input Signal Change after Recovery from Low Voltage Reset
Master/Slave
Pin
Toggle of Input Signal
Master
TXD
required
Slave
TXD
required
Table 5-13 State Under Low voltage Reset
Master/Slave
Pin
Descriptions
SELMS
Reset
Reset
Reset
TXD
NSLP
CLK
Master
Reset(High impedance)
High impedance
High impedance
Reset
RXD
BUS
SELMS
TXD
Reset
Reset
NSLP
CLK
Slave
Reset(High impedance)
High impedance
High impedance
RXD
BUS
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Figure 5-11 Low Voltage Detection
After releasing Low voltage reset mode, logical value high is output to the BUS pin after the clock input of 33 periods.
TXD data is valid from falling edge on the TXD pin.
5.4.3
Over current protection
The current in the transmitter output stage is limited in order to protect the transmitter against short-circuit to BAT or GND pins.
Table 5-14 Over Current Protection
Master/Slave
Pin
TXD
Descriptions
Normal function
NSLP
CLK
Normal function
Master
Normal function
RXD
BUS
TXD
NSLP
CLK
Normal function
Output current limited by IBUS_LIM
Normal function
Normal function
Slave
Normal function
RXD
BUS
Normal function
Output current limited by IBUS_LIM
5.4.4
Secondary Clock Master
The node that detects the wakeup event transmits the wakeup pulse onto the CXPI BUS. If the primary clock master cannot transmit
the clock onto the CXPI BUS due to failure, the wakeup pulse is retransmitted. If the clock is not transmitted onto the CXPI BUS,
each node detects the CXPI BUS error.
The secondary clock master may transmit the clock onto the CXPI BUS instead of the primary clock master if it detects that the
clock does not exist and confirms that the clock does not exist on the CXPI BUS for the period during which it transitions from sleep
mode
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■Operation sequence from master to slave
The TXD input pin is set High and The CLK pin is High impedance. Set Low on the NSLP pin initiates a transition to Sleep mode.
After the RXD pin was confirmed to High, and the SELMS pin goes to High.
Table 5-15 shows the pin states just before the SELMS pin input signal change.
Table 5-15 Pin State Table (from Master to Slave)
Pin
TXD
Pin State
High
Descriptions
No data transmitting
CLK
High impedance
Low
High level with external pullup resistor.
NSLP
SELMS
RXD
Sleep mode
Low to High
High
-
No data receiving
BUS
High
No wakeup signal receiving preferred
Figure 5-12 Application example Secondary clock master
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Figure 5-13 Transition Sequence from Master to Slave
■Operation sequence from slave to master
The TXD pin was inputting high, and the slave node to transition sleep mode.
After the CLK pin was confirmed to High, and the SELMS pin goes to Low.
Table 5-16 Pin State Table (from Slave to Master)
Pin
TXD
Pin State
High
Descriptions
No data transmitting
CLK
High impedance
Low
No wakeup signal receiving
NSLP
SELMS
RXD
Sleep mode
High to Low
High
-
-
BUS
High
No wakeup signal receiving preferred
Notes: The pin states just before SELMS input signal change.
Figure 5-14 Transition Sequence from Slave to Master
5.4.5
Arbitration
Transceivers will arbitration a bit-by-bit. It does not arbitrate in bytes.
Arbitration in bytes is done in the MCU.
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In the state of the Normal mode state, each node always compares received bit from the CXPI BUS with transmitted bit to the CXPI
BUS. When the value of the bit is corresponding, the node may continuously transmit to the CXPI BUS. When the value of the bit
is not corresponding, the loss of the arbitration is detected, and the transmission of the bit after that shall discontinue. If the
transmitting node detects the losing of arbitration, it behaves as the receiving node. The data of each bit transmitted on the CXPI
BUS performs arbitration from the start by the bit. Moreover, arbitration is performed targeted at entire field of the frame. When two
or more nodes begin transmitting at the same time, by arbitration only the node that transmits the highest priority frame can
complete the transmission.
MCU to make compares between transmitted data (TXD) and received data (RXD). If the data difference is detected, MCU has to
stop data transmission until finding IFS.
5.4.6
TXD Toggle
If the TXD pin short to ground or open, the BUS pin output is not a logic value Low fixed. Therefore it does not interfere with
communication of the other device.
An initial TXD dominant check prevents the bus line being driven to a permanent dominant state (blocking all network
communications) if the TXD pin is forced permanently Low by a hardware and/or software application failure. The TXD input level is
checked after a transition to the Normal mode.
If the TXD pin is Low, the transmit path remains disabled and is only enabled when the TXD pin goes High.
TXD toggle required in the following cases.
Data transmission after recovery from low voltage reset.
Data transmission after recovery from thermal shutdown.
First TXD data transmission in the Normal mode.
First wake-up pulse transmission in sleep mode.
■Short-circuit from the TXD pin to ground.(failure detect)
In the event of a short-circuit to ground or an open-wire on the TXD pin, the BUS pin output remains High(logical value ‘1’) by this
toggle function. In this case, comparing sent data to the TXD pin and received data from the RXD pin of the transceiver IC, MCU
can detect the permanent Low on the TXD pin by the data difference.
Even in this case receiver is active.
Figure 5-15 Normal Transmission Sequence of Master
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Figure 5-16 TXD Toggle of Master after Transition to Normal mode
Figure 5-17 Slave TXD Toggle after Recovery from Low voltage State
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6. Absolute Maximum Ratings
Rating
Parameters
Symbol
VBAT
Conditions
Min
Unit
Max
Power supply voltage
BAT pin
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-40
40
V
V
V
V
V
V
V
V
VNSLP
VSELMS
VCLK
NSLP pin
SELMS pin
CLK pin
TXD pin
RXD pin
CLK pin
BUS pin
6.9
18
Input voltage
6.9
6.9
6.9
6.9
40
VTXD
VRXD
VCLK
Output voltage
BUS pin voltage
BUS pin ESD
(1.5kΩ, 100pF)
BAT pin ESD
VBUS
VESDBUS
BUS pin
BAT pin
-8
-8
8
8
kV
kV
VESDBAT
(1.5kΩ, 100pF)
NSLP pin
SELMS pin
CLK pin
TXD pin
RXD pin
-
ESD
VESD
-2
2
kV
(1.5kΩ, 100pF)
Storage temperature
Maximum
TSTG
-55
-40
150
150
°C
°C
TJMAX
-
junction temperature
WARNING:
1. Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
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7. Recommended Operating Conditions
Table 7-1 Recommended condition
Value
Unit
Parameters
Symbol
Conditions
Min
Typ
Max
Power supply voltage
Operating ambient temperature
BUS pin pull-up resistance
RXD pin pull-up resistance
CLK pin pull-up resistance
Notes
VBAT
Ta
BAT pin [1]
5.3
-
18
V
-
－40
+25
1000
10
+125
°C
Ω
RMASTER
RRXD
RCLK
BUS pin (Master node：SELMS=0V)
RXD pin
900
2.4
2.4
1100
-
-
kΩ
kΩ
CLK pin (SELMS=5V)
10
[1]: (18V < VBAT ≤ 27V) less than 2 minutes.
WARNING:
1. The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of
the device's electrical characteristics are warranted when the device is operated under these conditions.
2. Any use of semiconductor devices will be under their recommended operating condition.
3. Operation under any conditions other than these conditions may adversely affect reliability of device and could result in device
failure.
4. No warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. If you
are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
Document Number: 002-10203 Rev.*A
Page 25 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
8. Electrical Characteristics
Table 8-1 DC Characteristics
VBAT = 5.3V~27V[1], Ta = -40~125°C; All voltages are referenced to Pin 8 (GND); Positive currents Flow into the IC; unless
Otherwise Specified.
Pin
Name
Parameters
Symbol
Conditions
Normal mode
Min
Typ
Max
Unit
TXD=5V
-
1.4
2.9
mA
CLK=20kHz, Duty 50%
Normal mode
TXD=0V
-
-
2.0
4.0
mA
uA
CLK=20kHz, Duty 50%
Sleep mode
VBAT =12V
TXD=5V
6
-
SELMS=5V
BUS= VBAT
Ta=25°C
Sleep mode
V
BAT =12V
Power supply current
IBAT
BAT
TXD=5V
-
16
-
uA
SELMS=0V
BUS= VBAT
Ta=25°C
Sleep mode
VBAT =12V
TXD=5V
-
-
-
-
50
60
uA
uA
SELMS=5V
BUS= VBAT
Sleep mode
VBAT =12V
TXD=5V
SELMS=0V
BUS= VBAT
BUS pin pull-up
resistance
RBUSpu
BUS
BUS
-
20
40
30
47
kΩ
BUS short circuit
current
IBUS_LIM
VBUS=18V
-
200
mA
Document Number: 002-10203 Rev.*A
Page 26 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Pin
Parameters
Symbol
Conditions
BUS=18V
BAT =5.3V
Min
Typ
Max
Unit
Name
V
BUS input leak current
(HIGH)
IBUS_PAS_rec
BUS
-
-
20
uA
TXD=5V
Ta=25°C
BUS=0V
VBAT =12V
TXD=5V
BUS input leak current
(LOW)
IBUS_PAS_dom
BUS
-1
-
-
mA
loss of ground BUS
leak current
VBAT =GND=18V
BUS=0V
IBUS_NO_GND
IBUS_NO_BAT
VBUSDR
BUS
BUS
BUS
-1
-
-
-
-
1
mA
uA
V
VBAT =0V
BUS=18V
Ta=25°C
loss of battery BUS
leak current
30
5.7
VBAT =13.5V
BUS drop voltage
2.4
IBUSsource=-100uA
TXD=0V
VBAT =7V
BUS pull-up resistance=
500Ω
VO_dom
BUS
BUS
-
-
-
1.4
V
V
BUS low level output
voltage
TXD=0V
VBAT =18V
BUS pull-up resistance=
500Ω
VO_dom
-
-
2
Receiver low level
threshold voltage
0.423
VBAT
VBUSdom
VBUSrec
VBUS_CNT
VHYS
BUS
BUS
BUS
BUS
BAT
-
-
-
-
-
-
-
V
V
V
V
V
Receiver high level
threshold voltage
0.556
VBAT
-
Receiver center level
voltage
0.475
VBAT
0.5
VBAT
0.525
VBAT
Receiver hysteresis
voltage
0.133
VBAT
-
-
Low level power-on
reset threshold voltage
VPOR_L
3.1
3.8
4.7
High level power-on
reset threshold
voltage
VPOR_H
BAT
-
3.3
4.1
4.9
V
power-on reset
hysteresis voltage
VPOR_HYS
TSD_H
BAT
-
0.2
156
151
0.3
165
159
0.5
174
168
V
Temperature shutdown
threshold
-
-
[2]
[2]
°C
°C
Temperature shutdown
release threshold
TSD_L
Notes
[1]: (18V < VBAT ≤ 27V) less than 2 minutes.
[2]: Guaranteed by design
Document Number: 002-10203 Rev.*A
Page 27 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Table 8-2 DC Characteristics CLK Pin (In Case of SELMS=5V, This Pin operates as Open Drain Output Pin.
In Case of SELMS=0V, This Pin operates as Input Pin)
VBAT = 5.3V～27V[1], Ta = -40～125°C; All voltages are referenced to Pin 8 (GND); Positive current Flow into the IC; unless
Otherwise Specified.
Pin
Name
Parameters
Symbol
Conditions
Min
Typ Max
Unit
High level input voltage
VIH_CLK
CLK
SELMS=0V
2
-
-
-
6
V
Low level input voltage
VIL_CLK
CLK
CLK
SELMS=0V
SELMS=0V
ICLK=2.2mA
SELMS=5V
SELMS=5V
SELMS=5V
SELMS=5V
-0.3
0.8
0.5
V
V
Hysteresis range of input voltage
VHYS_CLK
0.03
Low level output voltage
VOL_CLK
CLK
-
-
0.6
V
Low level current
High level leak current
Low level leak current
Notes
IOL_CLK
IILH_CLK
IILL_CLK
CLK
CLK
CLK
1.3
-3
3
-
-
mA
uA
uA
3
3
-3
-
[1]: (18V < VBAT ≤ 27V) less than 2 minutes.
Table 8-3 DC Characteristics NSLP Pin
VBAT = 5.3V~27V[1], Ta = -40~125°C; All voltages are referenced to Pin 8 (GND); Positive current Flow into the IC; unless
Otherwise Specified.
Pin
Name
Parameters
Symbol
Conditions
Min
Typ Max
Unit
High level input voltage
-
-
-
VIH_NSLP
NSLP
2
-
6
V
NSLP
NSLP
NSLP
NSLP
Low level input voltage
Hysteresis range of input voltage
Internal pull-down resistance
Low level leak current
Notes
VIL_NSLP
VHYS_NSLP
RPD_NSLP
IILL_NSLP
-0.3
0.03
100
-3
-
0.8
0.5
650
3
V
V
-
250
-
NSLP=5V
NSLP=0V
kΩ
uA
[1]: (18V < VBAT ≤ 27V) less than 2 minutes
Document Number: 002-10203 Rev.*A
Page 28 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Table 8-4 TXD Pin
VBAT = 5.3V~27V[1], Ta = -40~125°C; All voltages are referenced to Pin 8 (GND); Positive current Flow into the IC; unless
Otherwise Specified.
Pin
Name
Parameters
Symbol
Conditions
Min
Typ
Max
Unit
High level input voltage
VIH_TXD
TXD
-
2
-
6
V
Low level input voltage
Hysteresis range of input voltage
Internal pull-up resistance
High level leak current
Notes
VIL_TXD
VHYS_TXD
RPU_TXD
IILH_TXD
TXD
TXD
TXD
TXD
-
-0.3
0.03
50
-
0.8
0.5
325
3
V
V
-
-
125
-
TXD=0V
TXD=5V
kΩ
uA
-3
[1]: (18V < VBAT ≤ 27V) less than 2 minutes
Table 8-5 SELMS Pin
VBAT = 5.3V~27V[1], Ta = -40~125°C; All voltages are referenced to Pin 8 (GND); Positive current Flow into the IC; unless
Otherwise Specified.
Pin
Name
Parameters
Symbol
Conditions
Min
Typ
Max
Unit
High level input voltage
VIH_SELMS
SELMS
-
2
-
6
V
SELMS
SELMS
SELMS
SELMS
Low level input voltage
Hysteresis range of input voltage
Internal pull-up resistance
High level leak current
Notes
VIL_SELMS
VHYS_SELMS
RPU_SELMS
IILH_SELMS
-
-0.3
0.03
200
-3
-
0.8
0.5
1300
3
V
V
-
-
500
-
SELMS=0V
SELMS=5V
kΩ
uA
[1]: (18V < VBAT ≤ 27V) less than 2 minutes
Table 8-6 RXD Pin (Open Drain Output)
VBAT = 5.3V~27V[1], Ta = -40~125°C; All voltages are referenced to Pin 8 (GND); Positive current Flow into the IC; unless
Otherwise Specified.
Parameters
Symbol
Pin Name
Conditions
Min
Typ
Max
Unit
RXD
Low level output voltage
VOL_RXD
IRXD=2.2mA
-
-
0.6
V
RXD
RXD
RXD
Low level current
High level leak current
Low level leak current
Notes
IOL_RXD
IOLH_RXD
IOLL_RXD
RXD=0.4V
RXD=5V
RXD=0V
1.3
-3
3
-
-
mA
uA
uA
3
3
-3
-
[1]: (18V < VBAT≦ 27V) less than 2 minutes
Document Number: 002-10203 Rev.*A
Page 29 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Table 8-7 AC Characteristics
VBAT = 5.3V~27V[1], Ta = -40~125°C BUS Load 1kΩ /1nF; unless Otherwise Specified.
Pin
Parameters
Bitrate
Symbol
Nam
e
Conditions
Min
Typ
Max
Unit
TBUAD
BUS
VTH(bus) [3]=0.5VBAT
2.4
-
20
kbps
Mode transition time
(Sleep to Normal or
Normal to Sleep.)
TMODE_CHG
NSLP VTH(5v)[4]=50%
-
-
1
ms
CLK
NSLP wait time
TSLP_WT
TSLP_MN
VTH(5v) [4]=50%
NSLP
100
1
-
-
-
-
us
Minimum sleep time
NSLP
-
ms
NLSP = 0V
SELMS = 5V
Driver boot time under
sleep mode. [2]
TTXD_BT
TXD
-
-
195
us
V
V
TH(5v)[4]=50%
TH(bus)[3]=0.3VBAT
NLSP = 5V
SELMS = 0V
CLK=input clock
TXD=5V
CLK transmission delay
time
TCLK_PD
CLK
-
-
0.9
Tbit[5]
V
V
TH(5v)[4]=50%
TH(bus)[3]=0.3VBAT
NLSP = 5V
SELMS = 0V
CLK=input clock
TXD=5V
Time of Low level of
logic value '1'
0.39Tbit
+6τ
Ttx_1_lo_rec
BUS
BUS
-
-
-
-
V
TH(bus)[3]=0.7VBAT
NLSP = 5V
SELMS = 0V
CLK=input clock
TXD=5V
Time of Low level of
logic value '1'
Ttx_1_lo_dom
0.11
-
Tbit
V
TH(bus)[3]=0.3 VBAT
NLSP = 5V
TXD=0V
Ttx_1_lo_rec
Time of Low level of
logic value '0'
Ttx_0_lo_rec
BUS
BUS
-
-
-
-
-
-
+0.06Tbit
V
TH(bus) [3]=0.7 VBAT
NLSP = 5V
TXD=0V
Ttx_1_lo_dom
Time of Low level of
logic value '0'
Ttx_0_lo_dom
+0.06Tbit
V
TH(bus) [3]=0.3 VBAT
Document Number: 002-10203 Rev.*A
Page 30 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Pin
Nam
e
Parameters
Symbol
Conditions
Min
Typ
Max
Unit
NLSP = 5V
TXD=0V
TH(bus) [3]=0.556 VBAT
High level time at
receiving node.
Ttx_0_hi
BUS
0.06
-
-
Tbit
V
NSLP=5V
VTH(bus) [3]=VBUSdom
Receiver delay time
TRXD_PD
TTXD_PD
TICLK_DY
TOCLK_DY
RXD
TXD
CLK
CLK
-
-
-
-
-
2.4
3.3
70
Tbit
Tbit
%
Delay time of
transmission if logic
value '0'.
NSLP=5V
VTH(bus) [3]=0.3 VBAT
-
SELMS=0V
Input clock duty
30
14
V
TH(5v)[4]=50%
SELMS=5V
VTH(5v)[4]=50%
Output clock duty[6]
50
%
NSLP=0V
Wakeup pulse filter
constant(Master)
SELMS=0V
Trx_wakeup_master
BUS
BUS
30
-
-
150
5
us
us
VTH(bus) [3]=42.3%
NSLP=0V
Wakeup pulse filter
constant(Slave)
Trx_wakeup_slave
SELMS=5V
0.5
V
TH(bus) [3]=42.3%
NSLP=5V
Time of bus slope from
minimum
Ttx_1_dom_m
BUS
BUS
SELMS=0V
-
-
-
0.16
Tbit
V
TH(bus) [3]=0.3 VBAT
Recessive level of
logical value ‘0’.
V_rec_0
NSLP=5V
0.93
-
V_rec_1
Notes
[1]: (18V < VBAT ≤ 27V) less than 2 minutes
RXD pin load: 20pF
[2]: CXPI BUS load (Figure 8-12) : 10nF/500Ω
[3]: VTH(bus)：threshold of BUS pin
[4]: VTH(5v) ：threshold of NSLP,CLK,TXD,SELMS,RXD pins.
[5]: Tbit stands for 1bit time.(Figure 8-1)
[6]: logic '0/1' threshold clock
Document Number: 002-10203 Rev.*A
Page 31 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Figure 8-1 Definition of Tbit
Figure 8-2 Mode Transition Time
Figure 8-3 NSLP Wait Time
Figure 8-4 Minimum Sleep Time
Document Number: 002-10203 Rev.*A
Page 32 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Figure 8-5 Driver boot Time Under Sleep Mode
Figure 8-6 CLK Transmission Delay Time
Document Number: 002-10203 Rev.*A
Page 33 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Figure 8-7 Logic low and high CXPI BUS Waveform
Figure 8-8 Receiver Delay Time
Document Number: 002-10203 Rev.*A
Page 34 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Figure 8-9 Logic low Transmission Delay Time
Figure 8-10 Wakeup pulse waveform
Document Number: 002-10203 Rev.*A
Page 35 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Figure 8-11 CXPI BUS Load Connection
Document Number: 002-10203 Rev.*A
Page 36 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
9. Ordering Information
Part Number
Package
S6BT112A01SSB1002
8Pin 150-mil SOIC
S6BT112A01SSBB002
S6BT112A02SSB1002
S6BT112A02SSBB002
8Pin 150-mil SOIC Tape and Real
8Pin 150-mil SOIC
8Pin 150-mil SOIC Tape and Real
Document Number: 002-10203 Rev.*A
Page 37 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
10.Package Dimensions
D
A
C
Document Number: 002-10203 Rev.*A
Page 38 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Document History
Document Title: S6BT112A01/S6BT112A02 ASSP CXPI Transceiver IC for Automotive Network
Document Number: 002-10203
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
Initial release
New Spec.
**
5046456
AKFU
12/11/2015
04/06/2016
Revised the sentence style of the cover page
Changed all section 5 for easy to understand.
Changed figure of application.
*A
5208207
AKFU
Changed Figure 4-1 and Figure 5-1.
Removed “Driver recovery time when over-temperature detection is released.”
Document Number: 002-10203 Rev.*A
Page 39 of 40
PRELIMINARY
S6BT112A01/S6BT112A02
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
Products
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© Cypress Semiconductor Corporation 2015-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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whole or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall
indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the
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Document Number: 002-10203 Rev.*A
April 6, 2016
Page 40 of 40
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