W216_技术文档

PRELIMINARY

W216

Spread Spectrum FTG for 440BX and VIA Apollo Pro-133

Features

Table 1. Mode Input Table

Mode

Pin 3

PCI_STOP#

REF0

• Maximized EMI Suppression using Cypress’s Spread

Spectrum Technology

• Single chip system FTG for Intel 440BX AGPset and

VIA Apollo Pro-133

0

1

®

Table 2. Pin Selectable Frequency

Input Address

• Three copies of CPU output

• Seven copies of PCI output

• One 48-MHz output for USB / One 24-MHz for SIO

• Two buffered reference outputs

• Two IOAPIC outputs

CPU_F, 1:2

PCI_F, 0:5

FS3 FS2 FS1 FS0

(MHz)

133.3

124

(MHz)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

33.3 (CPU/4)

31 (CPU/4)

37.5 (CPU/4)

35 (CPU/4)

35 (CPU/3)

36.7 (CPU/3)

38.3 (CPU/3)

40 (CPU/3)

33.3 (CPU/3)

• Seventeen SDRAM outputs provide support for 4

DIMMs

150

140

• Supports frequencies up to 150 MHz

105

2

• I C™ interface for programming

110

• Power management control inputs

115

Key Specifications

120

100

CPU Cycle-to-Cycle Jitter:.......................................... 250 ps

CPU to CPU Output Skew: ......................................... 175 ps

PCI to PCI Output Skew: ............................................ 500 ps

SDRAMIN to SDRAM0:15 Delay: ..........................3.7 ns typ.

Reserved

112

103

66.8

83.3

75

37.3 (CPU/3)

34.3 (CPU/3)

33.4 (CPU/2)

41.7 (CPU/2)

37.5 (CPU/2)

V

: .................................................................... 3.3V±5%

: .................................................................... 2.5V±5%

DDQ3

DDQ2

SDRAM0:15 (leads) to SDRAM_F Skew: ..............0.4 ns typ.

Reserved

Pin Configuration^[1]

Block Diagram

VDDQ3

REF0/(PCI_STOP#)

VDDQ3

REF1/FS2

REF0/(PCI_STOP#)

GND

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

VDDQ2

REF1/FS2

IOAPIC0

IOAPIC_F

GND

2

X1

X2

XTAL

OSC

3

4

PLL Ref Freq

X1

X2

5

CPU_F

CPU1

VDDQ2

CPU2

GND

VDDQ2

6

7

8

9

Stop

Clock

Control

IOAPIC_F

I/O Pin

Control

VDDQ3

PCI_F/MODE

PCI0/FS3

GND

IOAPIC0

CLK_STOP#

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

CLK_STOP#

SDRAM_F

VDDQ3

SDRAM0

SDRAM1

GND

SDRAM2

SDRAM3

SDRAM4

SDRAM5

VDDQ3

SDRAM6

SDRAM7

GND

VDDQ2

CPU_F

PCI1

PCI2

PCI3

PCI4

VDDQ3

PCI5

SDRAMIN

SDRAM11

SDRAM10

VDDQ3

SDRAM9

SDRAM8

GND

Stop

Clock

CPU1

CPU2

Control

PLL 1

÷2,3,4

VDDQ3

PCI_F/MODE

PCI0/FS3

PCI1

Stop

Clock

Control

PCI2

PCI3

SDRAM15

SDRAM14

GND

SDRAM12

SDRAM13

VDDQ3

24MHz/FS0

48MHz/FS1

25

26

27

28

2

SDATA

SCLK

I C

PCI4

SDATA

SCLK

Logic

PCI5

VDDQ3

Note:

48MHz/FS1

PLL2

1. Internal pull-up resistors should not be relied upon for setting I/O

pins HIGH. Pin function with parentheses determined by MODE pin

resistor strapping. Unlike other I/O pins, input FS3 has an internal

pull-down resistor.

24MHz/FS0

VDDQ3

SDRAM0:15

Stop

Clock

SDRAMIN

Control

16

SDRAM_F

Intel is a registered trademark of Intel Corporation. I²C is a trademark of Philips Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

October 27, 1999, rev. **

PRELIMINARY

W216

Pin Definitions

Type

Pin Name

Pin No.

Pin Description

CPU1:2

51, 49

O

CPU Outputs 1 and 2: Frequency is set by the FS0:3 inputs or through serial input

interface, see Tables 2 and 6. These outputs are affected by the CLK_STOP# input.

CPU_F

52

Free-Running CPU Output: Frequency is set by the FS0:3 inputs or through serial input

interface, see Tables 2 and 6. This output is not affected by the CLK_STOP# input.

PCI1:5

11,12, 13, 14,

16

PCI Outputs 1 through 5: Frequency is set by the FS0:3 inputs or through serial input

interface, see Tables 2 and 6. These outputs are affected by the PCI_STOP# input.

PCI0/FS3

9

I/O PCI Output/Frequency Select Input: As an output, frequency is set by the FS0:3 inputs

or through serial input interface, see Tables 2 and 6. This output is affected by the

PCI_STOP# input. When an input, latches data selecting the frequency of the CPU and

PCI outputs.

PCI_F/MODE

CLK_STOP#

IOAPIC_F

8

I/O Free Running PCI Output: Frequency is set by the FS0:3 inputs or through serial input

interface, see Tables 2 and 6. This output is not affected by the PCI_STOP# input. When

an input, selects function of pin 3 as described in Table 1.

47

54

I

CLK_STOP# Input: When brought LOW, affected outputs are stopped LOW after com-

pleting a full clock cycle (2–3 CPU clock latency). When brought HIGH, affected outputs

start beginning with a full clock cycle (2–3 CPU clock latency).

O

Free-running IOAPIC Output: This output is a buffered version of the reference input

which is not affected by the CPU_STOP# logic input. It’s swing is set by voltage applied

to VDDQ2.

IOAPIC0

55

29

I/O IOAPIC Output: Provides 14.318-MHz fixed frequency. The output voltage swing is set

by voltage applied to VDDQ2. This output is disabled when CLK_STOP# is set LOW.

48MHz/FS1

I/O 48-MHz Output: 48 MHz is provided in normal operation. In standard systems, this

output can be used as the reference for the Universal Serial Bus. Upon power up, FS1

input will be latched, setting output frequencies as described in Table 2.

24MHz/FS0

REF1/FS2

30

I/O 24-MHz Output: 24 MHz is provided in normal operation. In standard systems, this

output can be used as the clock input for a Super I/O chip. Upon power up, FS0 input

will be latched, setting output frequencies as described in Table 2.

2

3

I/O Reference Output: 14.318 MHz is provided in normal operation. Upon power-up, FS2

input will be latched, setting output frequencies as described in Table 2.

REF0

(PCI_STOP#)

I/O Fixed 14.318-MHz Output 0 or PCI_STOP# Pin: Function determined by MODE pin.

The PCI_STOP# input enables the PCI 0:5 outputs when HIGH and causes them to

remain at logic 0 when LOW. The PCI_STOP signal is latched on the rising edge of

PCI_F. Its effects take place on the next PCI_F clock cycle. As an output, this pin provides

a fixed clock signal equal in frequency to the reference signal provided at the X1/X2 pins

(14.318 MHz).

SDRAMIN

17

I

Buffered Input Pin: The signal provided to this input pin is buffered to 17 outputs

(SDRAM0:15, SDRAM_F).

SDRAM0:15

44,43, 41, 40,

39,38, 36, 35,

22,21, 19, 18,

33, 32, 25, 24

Buffered Outputs: These sixteen dedicated outputs provide copies of the signal pro-

vided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when

CLK_STOP# input is set LOW.

O

SDRAM_F

46

O

I

Free-Running Buffered Output: This output provides a single copy of the SDRAMIN

input. The swing is set by VDDQ3; this signal is unaffected by the CLK_STOP# input.

2

SCLK

SDATA

X1

28

27

5

Clock pin for I C circuitry.

2

I/O Data pin for I C circuitry.

I

Crystal Connection or External Reference Frequency Input: This pin has dual func-

tions. It can be used as an external 14.318-MHz crystal connection or as an external

reference frequency input.

X2

6

I

Crystal Connection: An input connection for an external 14.318-MHz crystal. If using

an external reference, this pin must be left unconnected.

VDDQ3

1, 7, 15, 20,

31, 37, 45

P

Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs buffers,

PCI output buffers, reference output buffers and 48-MHz/24-MHz output buffers. Con-

nect to 3.3V.

VDDQ2

50, 56

P

Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V

or 3.3V.

2

PRELIMINARY

W216

Pin Definitions (continued)

Pin Name

GND

Pin No.

Type

Pin Description

4, 10, 23, 26,

34, 42, 48, 53

G

Ground Connections: Connect all ground pins to the common system ground plane.

tor on the l/O pins to pull the pins and their associated capac-

itive clock load to either a logic HIGH or LOW state. At the end

of the 2-ms period, the established logic “0” or “1” condition of

the l/O pin is latched. Next the output buffer is enabled, con-

verting the l/O pins into operating clock outputs. The 2-ms tim-

Overview

The W216 was designed as a single-chip alternative to the

standard two-chip Intel 440BX AGPset clock solution. It pro-

vides sufficient outputs to support most single-processor, four

SDRAM DIMM designs.

er starts when V reaches 2.0V. The input bits can only be

DD

reset by turning V off and then back on again.

DD

Functional Description

It should be noted that the strapping resistors have no signifi-

cant effect on clock output signal integrity. The drive imped-

ance of clock output (<40Ω, nominal), which is minimally af-

I/O Pin Operation

Pins 2, 8, 9, 29, and 30 are dual-purpose l/O pins. Upon power-

up these pins act as logic inputs, allowing the determination of

assigned device functions. A short time after power-up, the

logic state of each pin is latched and the pins become clock

outputs. This feature reduces device pin count by combining

clock outputs with input select pins.

fected by the 10-kΩ strap to ground or V . As with the series

DD

termination resistor, the output strapping resistor should be

placed as close to the l/O pin as possible in order to keep the

interconnecting trace short. The trace from the resistor to

ground or V should be kept less than two inches in length

DD

to prevent system noise coupling during input logic sampling.

An external 10-kΩ “strapping” resistor is connected between

When the clock outputs are enabled following the 2-ms input

period, the specified output frequency is delivered on the pin,

assuming that V has stabilized. If V has not yet reached

the l/O pin and ground or V . Connection to ground sets a

DD

latch to “0,” connection to V sets a latch to “1.” Figure 1 and

DD

Figure 2 show two suggested methods for strapping resistor

connections.

full value, output frequency initially may be below target but will

increase to target once V voltage has stabilized. In either

DD

case, a short output clock cycle may be produced from the

CPU clock outputs when the outputs are enabled.

Upon W216 power-up, the first 2 ms of operation is used for

input logic selection. During this period, the five I/O pins (2, 8,

9, 29, 30) are three-stated, allowing the output strapping resis-

V_DD

Output Strapping Resistor

Series Termination Resistor

10 k

Ω

(Load Option 1)

Clock Load

W216

Output

Buffer

R

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

10 k

(Load Option 0)

Ω

Q

D

Data

Latch

Figure 1. Input Logic Selection Through Resistor Load Option

Jumper Options

Output Strapping Resistor

Series Termination Resistor

V_DD

10 k

Ω

Clock Load

W216

R

Output

Buffer

Resistor Value R

Power-on

Reset

Timer

Hold

Output

Low

Output Three-state

Q

D

Data

Latch

Figure 2. Input Logic Selection Through Jumper Option

3

PRELIMINARY

W216

Where P is the percentage of deviation and F is the frequency

in MHz where the reduction is measured.

Spread Spectrum Frequency Timing Generator

The device generates a clock that is frequency modulated in

order to increase the bandwidth that it occupies. By increasing

the bandwidth of the fundamental and its harmonics, the am-

plitudes of the radiated electromagnetic emissions are re-

duced. This effect is depicted in Figure 3.

The output clock is modulated with a waveform depicted in

Figure 4. This waveform, as discussed in “Spread Spectrum

Clock Generation for the Reduction of Radiated Emissions” by

Bush, Fessler, and Hardin produces the maximum reduction

in the amplitude of radiated electromagnetic emissions. The

deviation selected for this chip is specified in Table 6. Figure 4

details the Cypress spreading pattern. Cypress does offer op-

tions with more spread and greater EMI reduction. Contact

your local Sales representative for details on these devices.

As shown in Figure 3, a harmonic of a modulated clock has a

much lower amplitude than that of an unmodulated signal. The

reduction in amplitude is dependent on the harmonic number

and the frequency deviation or spread. The equation for the

reduction is

Spread Spectrum clocking is activated or deactivated by se-

dB = 6.5 + 9*log (P) + 9*log (F)

lecting the appropriate values for bits 1–0 in data byte 0 of the

I C data stream. Refer to Table 7 for more details.

10

2

EMI Reduction

Spread

Non-

Spread

Spectrum

Enabled

Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation

MAX

MIN

Figure 4. Typical Modulation Profile

4

PRELIMINARY

W216

chipset. Clock device register changes are normally made

upon system initialization, if any are required. The interface

can also be used during system operation for power manage-

ment functions. Table 3 summarizes the control functions of

the serial data interface.

Serial Data Interface

The W216 features a two-pin, serial data interface that can be

used to configure internal register settings that control partic-

ular device functions. Upon power-up, the W216 initializes with

default register settings, therefore the use of this serial data

interface is optional. The serial interface is write-only (to the

clock chip) and is the dedicated function of device pins SDATA

and SCLOCK. In motherboard applications, SDATA and

SCLOCK are typically driven by two logic outputs of the

Operation

Data is written to the W216 in eleven bytes of eight bits each.

Bytes are written in the order shown in Table 4.

Table 3. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Output Disable

Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI

abled outputs are actively held low.

and system power. Examples are clock out-

puts to unused PCI slots.

CPU Clock Frequency

Selection

Provides CPU/PCI frequency selections alternate For alternate microprocessors and power

to the selections that are provided by the FS0:3 management options. Smooth frequency tran-

pins. Frequency is changed in a smooth and con- sition allows CPU frequency change under

trolled fashion.

normal system operation.

Spread Spectrum

Enabling

Enables or disables spread spectrum clocking.

For EMI reduction.

Output Three-state

Test Mode

Puts all clock outputs into a high-impedance state. Production PCB testing.

All clock outputs toggle in relation to X1 input, inter- Production PCB testing.

nal PLL is bypassed. Refer to Table 5.

(Reserved)

Reserved function for future device revision or pro- No user application. Register bit must be writ-

duction device testing.

ten as 0.

Table 4. Byte Writing Sequence

Byte Sequence

Byte Name

Bit Sequence

Byte Description

1

Slave Address 11010010

Commands the W216 to accept the bits in Data Bytes 0–7 for internal

register configuration. Since other devices may exist on the same com-

mon serial data bus, it is necessary to have a specific slave address for

each potential receiver. The slave receiver address for the W216 is

11010010. Register setting will not be made if the Slave Address is not

correct (or is for an alternate slave receiver).

2

3

Command

Code

Don’t Care

Unused by the W216, therefore bit values are ignored (“don’t care”). This

byte must be included in the data write sequence to maintain proper byte

allocation. The Command Code Byte is part of the standard serial com-

munication protocol and may be used when writing to another ad-

dressed slave receiver on the serial data bus.

Byte Count

Unused by the W216, therefore bit values are ignored (“don’t care”). This

byte must be included in the data write sequence to maintain proper byte

allocation. The Byte Count Byte is part of the standard serial communi-

cation protocol and may be used when writing to another addressed

slave receiver on the serial data bus.

4

5

Data Byte 0

Data Byte 1

Data Byte 2

Data Byte 3

Data Byte 4

Data Byte 5

Data Byte 6

Data Byte 7

Refer to Table 5 The data bits in Data Bytes 0–7 set internal W216 registers that control

device operation. The data bits are only accepted when the Address

Byte bit sequence is 11010010, as noted above. For description of bit

control functions, refer to Table 5, Data Byte Serial Configuration Map.

6

7

8

9

10

11

Don’t Care

Unused by the W216, therefore bit values are ignored (“don’t care”).

5

PRELIMINARY

W216

Writing Data Bytes

Table 6 details additional frequency selections that are avail-

able through the serial data interface.

Each bit in Data Bytes 0–7 controls a particular device function

except for the “reserved” bits which must be written as a logic

0. Bits are written MSB (most significant bit) first, which is bit

7. Table 5 gives the bit formats for registers located in Data

Bytes 0–7.

Table 7 details the select functions for Byte 0, bits 1 and 0.

Table 5. Data Bytes 0–7 Serial Configuration Map

Affected Pin

Bit Control

Bit(s) Pin No.

Data Byte 0

Pin Name

Control Function

0

1

Default

7

6

5

4

3

--

(Reserved)

--

0

SEL2

Refer to Table 6

SEL1

SEL0

Frequency Table Selection

Frequency Con-

trolled by FS (3:0)

Table 2

Frequency Con-

trolled by SEL (3:0)

Table 6

2

--

SEL3

Refer to Table 6

0

1

Spread Spectrum --

OFF

ON

0

Test Mode

--

Normal

Three-stated

Data Byte 1

7

6

5

4

--

0

1

--

3

2

1

0

46

49

51

52

SDRAM_F

CPU2

CPU1

CPU_F

Clock Output Disable

Low

Active

Data Byte 2

7

6

--

8

--

(Reserved)

--

0

1

PCI_F

PCI5

PCI4

PCI3

PCI2

PCI1

PCI0

Clock Output Disable

Low

Active

5

4

3

2

1

0

16

14

13

12

11

9

Data Byte 3

7

6

--

(Reserved)

--

0

1

(Reserved)

--

5

4

3

29

30

48MHz

24MHz

SDRAM12:15

Clock Output Disable

Low

Active

33, 32,

25, 24

6

PRELIMINARY

W216

Table 5. Data Bytes 0–7 Serial Configuration Map (continued)

Affected Pin

Bit Control

Bit(s) Pin No.

Pin Name

Control Function

0

1

Default

2

1

0

22, 21,

19, 18

SDRAM8:11

Clock Output Disable

Low

Active

1

39, 38,

36, 35

SDRAM4:7

SDRAM0:3

Clock Output Disable

Low

Active

1

44, 43,

41, 40

Data Byte 4

7

--

(Reserved)

--

0

6

5

4

3

2

1

0

Data Byte 5

7

6

--

(Reserved)

--

0

1

0

1

(Reserved)

5

4

3

2

1

0

54

55

--

IOAPIC_F

IOAPICO

--

Disabled

Low

--

Active

--

Disabled

(Reserved)

--

(Reserved)

--

2

REF1

REF0

Clock Output Disable

Low

Active

3

7

PRELIMINARY

W216

Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes

Input Conditions

Output Frequency

Spread On

Data Byte 0, Bit 3 = 1

Bit 2

Bit 6

Bit 5

Bit 4

CPU, SDRAM

PCI Clocks

(MHz)

SEL_3

SEL_2

SEL_1

SEL_0

Clocks (MHz)

133.3

124

Spread Percentage

–0.5% Down

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

33.3 (CPU/4)

31 (CPU/4)

37.5 (CPU/4)

35 (CPU/4)

35 (CPU/3)

36.7 (CPU/3)

38.3 (CPU/3)

40 (CPU/3)

33.3 (CPU/3)

150

140

105

110

115

120

100

Reserved

112

103

66.8

83.3

75

37.3 (CPU/3)

34.3 (CPU/3)

33.4 (CPU/2)

41.7 (CPU/2)

37.5 (CPU/2)

Reserved

Table 7. Select Function for Data Byte 0, Bits 0:1

Input Conditions

Output Conditions

Data Byte 0

PCI_F,

PCI0:5

REF0:1,

Function

Normal Operation

Spread Spectrum

Bit 1

Bit 0

CPU_F, 1:2

Note 2

IOAPIC0,_F

48MHZ

24MHZ

24 MHz

Hi-Z

0

1

0

1

Note 2

Hi-Z

14.318 MHz

Hi-Z

48 MHz

Hi-Z

Note 2

Three-state

X

Hi-Z

Note:

2. CPU and PCI frequency selections are listed in Table 2 and Table 6.

8

PRELIMINARY

W216

Absolute Maximum Ratings

Stresses greater than those listed in this table may cause per-

manent damage to the device. These represent a stress rating

above those specified in the operating sections of this specifi-

cation is not implied. Maximum conditions for extended peri-

ods may affect reliability.

only. Operation of the device at these or any other conditions

.

Parameter

Description

Voltage on any pin with respect to GND

Storage Temperature

Rating

–0.5 to +7.0

–65 to +150

–55 to +125

0 to +70

Unit

V

, V

DD IN

T

°C

kV

STG

B

Ambient Temperature under Bias

Operating Temperature

T

A

ESD

Input ESD Protection

2 (min.)

PROT

DC Electrical Characteristics: T = 0°C to +70°C, V

= 3.3V±5%, V = 2.5V±5%

DDQ2

A

DDQ3

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Supply Current

I

3.3V Supply Current

CPU_F, 1:2 = 100 MHz

Outputs Loaded

320

40

mA

DD

[3]

I

2.5V Supply Current

CPU_F, 1:2 = 100 MHz

DD

[3]

Outputs Loaded

Logic Inputs

V

Input Low Voltage

Input High Voltage

GND – 0.3

0.8

V

IL

2.0

V

+ 0.3

DD

V

IH

[4]

I

Input Low Current

–25

10

µA

IL

[4]

Input High Current

IH

IL

Input Low Current (SEL100/66#)

Input High Current (SEL100/66#)

–5

+5

IH

Clock Outputs

V

Output Low Voltage

Output High Voltage

Output High Voltage CPU_F, 1:2 IOAPIC

Output Low Current CPU_F, 1:2

PCI_F, PCI0:5

I

= 1 mA

50

mV

V

OL

OH

V

= –1 mA

3.1

2.2

60

96

72

61

60

95

43

76

60

50

75

OH

V

OH

I

V

= 1.25V

= 1.5V

= 1.25V

= 1.5V

= 1.25V

= 1.5V

= 1.25V

= 1.5V

73

110

92

71

70

110

60

96

90

60

95

85

130

110

80

mA

OL

IOAPIC0, IOAPIC_F

REF0:1

48-MHz

80

24-MHz

80

SDRAM0:15,_F

130

80

I

Output High Current CPU_F, 1:2

PCI_F, PCI0:5

OH

120

130

72

IOAPIC0, IOAPIC_F

REF0:1

48-MHz

72

24-MHz

72

SDRAM0:15,_F

120

Notes:

3. All clock outputs loaded with 6" 60Ω transmission lines with 22-pF capacitors.

4. W216 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device.

9

PRELIMINARY

W216

DC Electrical Characteristics: T = 0°C to +70°C, V

= 3.3V±5%, V

= 2.5V±5% (continued)

DDQ2

A

DDQ3

Parameter

Description

Test Condition

Min.

Typ.

Max.

Unit

Crystal Oscillator

[5]

V

X1 Input Threshold Voltage

V

= 3.3V

DDQ3

1.65

14

V

TH

C

Load Capacitance, Imposed on

pF

LOAD

[6]

External Crystal

[7]

C

X1 Input Capacitance

Pin X2 unconnected

Except X1 and X2

28

pF

IN,X1

Pin Capacitance/Inductance

C

Input Pin Capacitance

Output Pin Capacitance

Input Pin Inductance

5

6

7

pF

nH

IN

OUT

IN

L

AC Electrical Characteristics

T = 0°C to +70°C, V

= 3.3V±5%,V

= 2.5V± 5% f = 14.31818 MHz

XTL

A

DDQ3

DDQ2

AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the

clock output; Spread Spectrum is disabled.

CPU Clock Outputs, CPU_F, 1:2 (Lump Capacitance Test Load = 20 pF)

CPU = 66.8 MHz

CPU = 100 MHz

CPU = 133 MHz

Test Condition/

Comments

Parameter

Description

Period

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

t

Measured on rising edge

at 1.25

15

5.2

5.0

1

15.5 10

3.0

10.5 7.5

1.87

8.0

ns

P

High Time

Low Time

Duration of clock cycle

above 2.0V

H

L

Duration of clock cycle

below 0.4V

2.8

1.67

ns

Output Rise

Edge Rate

Measured from 0.4V to

2.0V

4

1

4

1

4

V/ns

%

R

F

OutputFallEdge Measured from 2.0V to

Rate

1

0.4V

Duty Cycle

Measured on rising and

falling edge at 1.25V

45

55

250

45

55

250

45

55

250

D

JC

Jitter,

Cycle-to-Cycle

Measured on rising edge

at 1.25V. Maximum differ-

ence of cycle time be-

ps

tween two adjacent cycles.

t

f

Output Skew

Measured on rising edge

at 1.25V

175

3

175

3

175

3

ps

SK

Frequency

Assumes full supply volt-

age reached within 1 ms

from power-up. Short cy-

cles exist prior to frequen-

cy stabilization.

ms

ST

Stabilization

from Power-up

(cold start)

Z

AC Output

Impedance

Average value during

switching transition. Used

for determining series ter-

mination value.

20

Ω

o

Notes:

5. X1 input threshold voltage (typical) is V_DDQ3/2.

6. The W216 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;

this includes typical stray capacitance of short PCB traces to crystal.

7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).

10

PRELIMINARY

W216

PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF

Parameter

Description

Period

Test Condition/Comments

Measured on rising edge at 1.5V

Min.

30

12

1

Typ.

Max.

Unit

ns

t

P

High Time

Duration of clock cycle above 2.4V

Duration of clock cycle below 0.4V

Measured from 0.4V to 2.4V

ns

H

L

Low Time

ns

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

4

V/ns

%

R

F

Measured from 2.4V to 0.4V

1

Measured on rising and falling edge at 1.5V

45

55

250

D

JC

Jitter, Cycle-to-Cycle

Measured on rising edge at 1.5V. Maximum

ps

difference of cycle time between two adjacent cycles.

t

Output Skew

Measured on rising edge at 1.5V

500

4

ps

ns

SK

CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising

edge at 1.5V. CPU leads PCI output.

1.5

O

f

Frequency Stabilization

from Power-up (cold

start)

Assumes full supply voltage reached within 1 ms

from power-up. Short cycles exist prior to frequency

stabilization.

3

ms

ST

Z

AC Output Impedance

Average value during switching transition. Used for

determining series termination value.

15

Ω

o

IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Frequency generated by crystal oscillator

Measured from 0.4V to 2.0V

Min.

Typ.

Max. Unit

f

14.318

MHz

t

f

1

4

V/ns

%

R

Measured from 2.0V to 0.4V

F

Measured on rising and falling edge at 1.25V

45

55

1.5

D

FrequencyStabilizationfrom Assumes full supply voltage reached within

ms

ST

Power-up (cold start)

AC Output Impedance

1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Z

Average value during switching transition. Used

for determining series termination value.

15

Ω

o

REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Frequency, Actual

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

Test Condition/Comments

Frequency generated by crystal oscillator

Measured from 0.4V to 2.4V

Min.

Typ.

Max. Unit

f

14.318

MHz

t

f

0.5

45

2

V/ns

%

R

Measured from 2.4V to 0.4V

F

Measured on rising and falling edge at 1.5V

55

3

D

FrequencyStabilizationfrom Assumes full supply voltage reached within

ms

ST

Power-up (cold start)

1 ms from power-up. Short cycles exist prior to

frequency stabilization.

Z

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

25

Ω

o

11

PRELIMINARY

W216

SDRAM 0:15,_F Clock Outputs (Lump Capacitance Test Load = 22 pF)

SDRAMIN =

100 MHz

SDRAMIN =

133 MHz

66.8 MHz

Test Condition/

Parameter

Description

Period

Comments

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit

t

Measured on rising edge

at 1.5V

15

5.2

5.0

1

15.5 10

10.5 7.5

8.0

ns

P

High Time

Low Time

Duration of clock cycle

above 2.4V

3.0

1.87

ns

H

Duration of clock cycle

below 0.4V

2.0

1.67

ns

L

Output Rise

Edge Rate

Measured from 0.4V to

2.4V

4

1

4

1

4

V/ns

%

R

OutputFallEdge Measured from 2.4V to

1

F

Rate

0.4V

Duty Cycle

Measured on rising and

falling edge at 1.5V

45

55

250

45

55

250

45

55

250

D

Output Skew

Measured on rising and

falling edge at 1.5V

ps

SK

PD

ns

Propagation

Delay

Measured from SDRAMIN

3.7

15

3.7

15

3.7

15

Z

AC Output

Impedance

Average value during

switching transition. Used

for determining series ter-

mination value.

Ω

o

48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Frequency, Actual

Deviation from 48 MHz

PLL Ratio

Test Condition/Comments

Min.

Typ.

Max. Unit

MHz

f

Determined by PLL divider ratio (see m/n below)

(48.008 – 48)/48

48.008

+167

f

ppm

D

m/n

(14.31818 MHz x 57/17 = 48.008 MHz)

Measured from 0.4V to 2.4V

57/17

t

f

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

0.5

45

2

V/ns

%

R

Measured from 2.4V to 0.4V

F

Measured on rising and falling edge at 1.5V

55

3

D

Frequency Stabilization

Assumes full supply voltage reached within 1 ms

ms

ST

from Power-up (cold start) from power-up. Short cycles exist prior to fre-

quency stabilization.

Z

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

25

Ω

o

12

PRELIMINARY

W216

24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)

Parameter

Description

Frequency, Actual

Deviation from 24 MHz

PLL Ratio

Test Condition/Comments

Determined by PLL divider ratio (see m/n below)

(24.004 – 24)/24

Min.

Typ.

24.004

+167

Max. Unit

MHz

f

ppm

D

m/n

(14.31818 MHz x 57/34 = 24.004 MHz)

Measured from 0.4V to 2.4V

57/34

t

f

Output Rise Edge Rate

Output Fall Edge Rate

Duty Cycle

0.5

45

2

V/ns

%

R

Measured from 2.4V to 0.4V

F

Measured on rising and falling edge at 1.5V

Assumes full supply voltage reached within 1 ms

55

3

D

Frequency Stabilization

ms

ST

from Power-up (cold start) from power-up. Short cycles exist prior to fre-

quency stabilization.

Z

AC Output Impedance

Average value during switching transition. Used

for determining series termination value.

25

Ω

o

Ordering Information

Package

Name

Ordering Code

Package Type

W216

H

56-pin SSOP (300 mils)

Document #: 38-00850

13

PRELIMINARY

W216

Package Diagram

56-Pin Small Shrink Outline Package (SSOP, 300 mils)

Summary of nominal dimensions in inches:

Body Width: 0.296

Lead Pitch: 0.025

Body Length: 0.625

Body Height: 0.102

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	W216
厂家：	CYPRESS
描述：	Spread Spectrum FTG for 440BX and VIA Apollo Pro-133 扩频FTG的440BX和威盛Apollo Pro的-133
文件：	总14页 (文件大小：157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W216 [CYPRESS]

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