W42C31-06GT [CYPRESS]
Clock Generator, 60MHz, CMOS, PDSO8, 0.150 INCH, PLASTIC, SO-8;
| 型号： | W42C31-06GT |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator, 60MHz, CMOS, PDSO8, 0.150 INCH, PLASTIC, SO-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总6页 (文件大小：135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W42C31-06
Spread Spectrum Frequency Timing Generator
to pass increasingly difficult EMI testing without resorting to
costly shielding or redesign.
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Generates a spread spectrum 3X copy of the input
• Integrated loop filter components
• Operates with a 5V supply
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
• Low-power CMOS design
Table 1. Frequency Spread Selection
• Available in 8-pin SOIC (Small Outline Integrated
Circuit)
W42C31-06 Oscillator
Input
Frequency
(MHz)
XTAL Input
Frequency
(MHz)
Output
Frequency
(MHz)
Overview
FS0
0
The W42C31-06 incorporates the latest advances in PLL
spread spectrum frequency synthesizer techniques. By fre-
quency modulating the output with a low-frequency carrier,
EMI is greatly reduced. Use of this technology allows systems
14 to 20
14 to 20
14 to 20
14 to 20
3f ±0.75%
IN
1
3f ±1.25%
IN
Simplified Block Diagram
Pin Configuration
5.0V
SOIC
X1
X1
X2
SSON#
NC
1
2
3
4
8
7
6
5
XTAL
Input
X2
GND
FS0
VDD
Spread Spectrum
Output
W42C31-06
CLKOUT
(EMI suppressed)
5.0V
Oscillator or Reference
Input
Spread Spectrum
W42C31-06
Output
(EMI suppressed)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 29, 1999, rev. **
W42C31-06
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CLKOUT
5
O
I
Output Modulated Frequency: Frequency modulated copy of the unmodulated input
clock (multiplier of 3).
X1
1
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It may either be connected to an external crystal, or to an external reference
clock.
X2
2
8
I
I
Crystal Connection: If using an external reference, this pin must be left unconnected.
SSON#
Spread Spectrum (Active LOW): Pulling this input signal HIGH turns the internal
modulating waveform off. This pin has an internal pull-down resistor.
FS0
4
I
Frequency Selection Bit 0: This pin selects the frequency spreading
characteristics. Refer to Table 1. This pin has an internal pull-up resistor.
NC
7
6
3
NC
P
No Connect: This pin must be left unconnected.
VDD
GND
Power Connection: Connected to 5V power supply.
G
Ground Connection: This should be connected to the common ground plane.
Frequency Selection With SSFTG
Functional Description
In Spread Spectrum Frequency Timing Generation, EMI re-
The W42C31-06 uses a phase-locked loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. An
on-chip crystal driver causes the crystal to oscillate at its fun-
damental. The resulting reference signal is divided by Q and
fed to the phase detector. A signal from the VCO is divided by
P and fed back to the phase detector also. The PLL will force
the frequency of the VCO output signal to change until the
divided output signal and the divided reference signal match
at the phase detector input. The output frequency is then equal
to the ratio of P/Q times the reference frequency. The unique
feature of the Spread Spectrum Clock Generator is that a mod-
ulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a pre-
determined frequency band.
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed, the modula-
tion percentage may be varied.
Using the frequency select bit (FS0), the spreading percent-
age can be chosen (see Table 1).
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between ±0.5% and ±2.5% are most
common.
The W42C31 features the ability to select from various spread
spectrum characteristics. Selections specific to the
W42C31-06 are shown in Table 1. Other spreading character-
istics are available (see separate data sheets) or can be cre-
ated with a custom mask.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
VDD
X1
CLKOUT
Post
Dividers
XTAL
Freq.
Divider
Q
Phase
Detector
Charge
Pump
VCO
Σ
X2
Modulating
Waveform
Feedback
Divider
Crystal load
capacitors
as needed
P
PLL
GND
Figure 1. System Block Diagram
2
W42C31-06
Spread Spectrum Frequency Timing
Generation
5dB/div
The benefits of using Spread Spectrum Frequency Timing
Generation are depicted in Figure 2. An EMI emission profile
of a clock harmonic is shown.
SSFTG
Typical Clock
Contrast the typical clock EMI with the Cypress Spread Spec-
trum Frequency Timing Generation EMI. Notice the spike in
the typical clock. This spike can make systems fail quasi-peak
EMI testing. The FCC and other regulatory agencies test for
peak emissions. With spread spectrum enabled, the peak en-
ergy is much lower (at least 8 dB) because the energy is
spread out across a wider bandwidth.
Modulating Waveform
The shape of the modulating waveform is critical to EMI reduc-
tion. The modulation scheme used to accomplish the maxi-
mum reduction in EMI is shown in Figure 3. The period of the
modulation is shown as a percentage of the period length
along the X axis. The amount that the frequency is varied is
shown along the Y axis, also shown as a percentage of the
total frequency spread.
Cypress frequency selection tables express the modulation
percentage in two ways. The first method displays the spread-
ing frequency band as a percent of the programmed average
output frequency, symmetric about the programmed average
frequency. This method is always shown using the expression
Figure 2. Typical Clock and SSFTG Comparison
±
f
X
% in the frequency spread selection table.
Center
MOD
SSON# Pin
The second approach is to specify the maximum operating
frequency and the spreading band as a percentage of this fre-
quency. The output signal is swept from the lower edge of the
band to the maximum frequency. The expression for this ap-
An internal pull-down resistor defaults the chip into spread
spectrum mode. The SSON# pin enables the spreading fea-
ture when set LOW. When disabled (SSON# HIGH), the
W42C31-06 simply passes through the input clock. Upon go-
ing LOW, the device takes 2 ms to re-track the spreading algo-
rithm.
–
proach is f
X
%. Whenever this expression is used,
MAX
MOD
Cypress has taken care to ensure that f
will never be ex-
MAX
ceeded. This is important in applications where the clock
drives components with tight maximum clock speed specifica-
tions.
100%
80%
60%
40%
20%
0%
–20%
–40%
–60%
–80%
–100%
Time
Figure 3. Modulation Waveform Profile
3
W42C31-06
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
, V
DD IN
T
°C
°C
°C
W
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
Power Dissipation
–55 to +125
0.5
B
P
D
DC Electrical Characteristics: 0°C < T < 70°C, V = 5V ±10%
A
DD
Parameter
Description
Supply Current
Test Condition
Min
Typ
Max
Unit
mA
ms
I
t
20
40
5
DD
ON
Power Up Time
First locked clock cycle after
Power Good
V
V
V
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
Input High Current
Output Low Current
Output High Current
Input Capacitance
0.15V
0.4
V
V
IL
DD
0.7V
IH
DD
V
OL
OH
2.5
V
I
I
I
I
Note 1
Note 1
–100
µA
µA
mA
mA
pF
pF
IL
10
IH
@ 0.4V, V = 5V
24
24
OL
OH
DD
@ 2.4V, V = 5V
DD
C
C
All pins except X1, X2
7
I
[2]
Load Capacitance (as seen
by XTAL)
Pins X1, X2
17
L
R
Input Pull-Up Resistor
500
20
kΩ
P
Z
Clock Output Impedance
Ω
OUT
AC Electrical Characteristics: T = 0°C to +70°C, V = 5V±10%
A
DD
Parameter
Description
Input Frequency
Test Condition
Min
14
Typ
Max
Unit
f
f
t
t
t
t
t
Input Clock
Spread Off
20
60
5
MHz
MHz
ns
IN
Output Frequency
Output Rise Time
Output Fall Time
42
OUT
R
V
V
, 15-pF load 0.8–2.4
2
2
DD
, 15-pF load 2.4–0.8
DD
5
ns
F
Output Duty Cycle
Input Duty Cycle
15-pF load
45
40
55
60
300
%
OD
ID
%
Jitter, Cycle-to-Cycle
Harmonic Reduction
250
ps
JCYC
8
dB
Notes:
1. Input FS0 has a pull-up resistor; Input SSON# has a pull-down resistor.
2. Pins X1 and X2 each have a 34-pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 17 pF. If driving X1 with a
reference clock signal, the load capacitance will be 34 pF (typical).
4
W42C31-06
The 10-µF decoupling capacitor shown should be a tantalum
Application Information
type. For further EMI protection, the V
made via a ferrite bead, as shown.
connection can be
DD
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
The 6-pF XTAL load capacitors can be used to raise the inte-
grated 17-pF capacitance up to a total load of 20 pF on the
crystal.
V
decoupling is important to both reduce phase jitter and
DD
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
Recommended Board Layout
DD
Figure 5 shows a recommended 2-layer board layout.
1
8
7
6
5
C1
6 pF
2
3
4
XTAL1
GND
VDD
Output
R1
C2
6 pF
C3
µF
0.1
5V System Supply
FB
C4
10
µF Tantalum
Figure 4. Recommended Circuit Configuration
C1, C2 = XTAL load capacitors (optional; use
is not required for operation).
Typical value is 6 pF.
C3 = High frequency supply decoupling
Optional Guard Ring for
XTAL Oscillator Circuitry
µF recommended).
capacitor (0.1-
C4 = Common supply low frequency
µF tantalum
decoupling capacitor (10-
recommended).
R1 = Match value to line impedance
G
FB
G
=
Ferrite Bead
C1
Via To GND Plane
=
G
XTAL1
C3
C2
G
G
G
R1
Clock Output
C4
G
Power Supply Input
(5V)
FB
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Freq. Mask
Package
Name
Ordering Code
Code
Package Type
W42C31
06
G
8-pin Plastic SOIC (150-mil)
Document #: 38-00800
5
W42C31-06
Package Diagram
8-Pin Small Outline Integrated Circuit (SOIC, 150-mil)
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
©2020 ICPDF网 联系我们和版权申明