DA16200 [DIALOG]
Ultra Low Power Wi-Fi SoC;
| 型号： | DA16200 |
| 厂家： | 
Dialog Semiconductor |
| 描述： | Ultra Low Power Wi-Fi SoC |
| 文件： | 总94页 (文件大小：3130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DA16200
Ultra Low Power Wi-Fi SoC
General Description
The DA16200 is a highly integrated ultra-low power Wi-Fi system on a chip (SoC), which contains an
802.11b/g/n radio (PHY), a baseband processor, a media access controller (MAC), on-chip memory,
and a host networking application processor, all on a single silicon die.
The SoC enables full offload capabilities, running the entire networking stack on chip so that no
external network processor, CPU, or microcontroller is required, while many other SoCs optionally
use a microcontroller.
DA16200 is a synthesis of breakthrough ultra-low power technologies that enables extremely low
power operation in the SoC. DA16200 shuts down every micro element of the chip that is not in use,
which allows a near zero level of power consumption when not actively transmitting or receiving data.
Such low power operation can extend the battery life as long as a year or more depending on the
application. DA16200 also enables ultra-low power transmitting and receiving modes when the SoC
needs to be awake to exchange information with other devices. Advanced algorithms enable staying
asleep until the exact moment required to wake up to transmit or receive.
The SoC is built from the ground up for the Internet of Things (IoT) and is ideal for door locks,
thermostats, sensors, pet trackers, asset trackers, sprinkler systems, connected lighting, video
cameras, video doorbells, wearables, and other IoT devices.
Key Features
■
■
■
Highly integrated ultra-low power Wi-Fi®
system on chip
□
Provides dynamic auto switching function
■
Supports various interfaces
Full offload: SoC runs full networking OS and
TCP/IP stack
□
□
□
□
□
□
□
□
□
eMMC/SD expanded memory
SDIO Host/Slave function
QSPI for external flash control
Three UARTs
Wi-Fi processor
□
IEEE 802.11b/g/n, 1×1, 20 MHz channel
bandwidth, 2.4 GHz
SPI Master/Slave interface
I2C Master/Slave interface
I2S for digital audio streaming
4-channel PWM
□
□
□
IEEE 802.11s Wi-Fi mesh
On-chip PA, LNA, and RF switch
Wi-Fi security: WPA/WPA2-
Enterprise/Personal, WPA2 SI, WPA3
SAE, and OWE
Individually programmable, multiplexed
GPIO pins
□
Vendor EAP types: EAP-
TTLS/MSCHAPv2, PEAPv0/EAP-
MSCHAPv2, PEAPv1, EAP-FAST, and
EAP-TLS
□
JTAG and SWD
■
Wi-Fi Alliance certifications:
□
□
□
Wi-Fi CERTIFIED™ b, g, n
WPA™ - Enterprise, Personal
WPA2™ - Enterprise, Personal
WPA3™ - Enterprise, Personal
Wi-Fi Direct
□
Operating modes: Station, SoftAP, and
Wi-Fi Direct® Modes (GO, GC, GO fixed)
□
□
WPS-PIN/PBC for easy Wi-Fi provisioning
Connection manager for autonomous and
fast Wi-Fi connections
□
□
□
□
Bluetooth coexistence
□
Wi-Fi Enhanced Open™
WMM
Antenna switching diversity
□
□
□
■
■
Built-in 4-channel auxiliary ADC for sensor
interfaces
WMM - Power Save
Wi-Fi Protected Setup™
□
12-bit SAR ADC: single-ended four
channels
■
CPU core subsystem
□
Arm® Cortex®-M4F core w/ clock
frequency of 30~160 MHz
Direct code execution from the external serial
flash memory (XIP)
□
ROM: 256 kB
Datasheet
Revision 3.3
03-Feb-2021
CFR0011-120-00
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© 2021 Dialog Semiconductor
DA16200
Ultra Low Power Wi-Fi SoC
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Hardware accelerators
□
□
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SRAM: 512 kB
□
□
□
General HW CRC engine
OTP: 8 kB
HW zeroing function for fast booting
Retention Memory: 48 kB
Pseudo random number generator
(PRNG)
■
Power management unit
□
□
On-Chip RTC
■
■
Complete software stack
Wake-up control of fast booting or full
booting with minimal initialization time
□
□
Comprehensive networking software stack
Provides TCP/IP stack: in the form of
network socket APIs
□
□
Integrated DC-DC and LDOs
Supports three ultra-low power Sleep
modes
Advanced security
□
□
Secure booting
■
■
Clock source
Secure debugging using JTAG/SWD and
UART ports
□
□
□
40 MHz crystal (± 20 ppm) for master
clock (initial + temp + aging)
□
Secure asset storage
32.768 kHz crystal (± 250 ppm) for RTC
clock
■
Built-in hardware crypto engines for advanced
security
Integrated 32 kHz RC oscillator
□
□
TLS/DTLS security protocol functions
Supply
Crypto engine for key deliberate generic
security functions: AES (128,192,256),
DES/3DES, SHA1/224/256, RSA, DH,
ECC, CHACHA, and TRNG
□
Single operating voltage: 2.1 V to 3.6 V
(typical: 3.3 V)
□
□
Digital I/O Supply Voltage: 1.8 V / 3.3 V
Black-out and brown-out detector
■
■
Package type
□
□
6 mm × 6 mm, 0.4 mm pitch, 48-Pin, QFN
3.8 mm × 3.8 mm, 0.4 mm pitch, 72-Pin,
fcCSP
Operating temperature range
-40 °C to 85 °C
□
Applications
■
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Security systems
Door locks
Thermostats
Garage door openers
Blinds
Lighting control
Sprinkler systems
Video camera security systems
Smart appliances
Video doorbell
Asset tracker
Datasheet
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03-Feb-2021
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© 2021 Dialog Semiconductor
DA16200
Ultra Low Power Wi-Fi SoC
System Diagram
Figure 1: System Diagram
Datasheet
Revision 3.3
03-Feb-2021
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© 2021 Dialog Semiconductor
DA16200
Ultra Low Power Wi-Fi SoC
Contents
General Description ............................................................................................................................ 1
Key Features ........................................................................................................................................ 1
Applications ......................................................................................................................................... 2
System Diagram .................................................................................................................................. 3
Contents ............................................................................................................................................... 4
Figures.................................................................................................................................................. 6
Tables ................................................................................................................................................... 7
1
2
3
4
Terms and Definitions................................................................................................................. 10
References ................................................................................................................................... 10
Block Diagram ............................................................................................................................. 11
Pinout ........................................................................................................................................... 13
4.1 48-Pin QFN ......................................................................................................................... 13
4.2 72-Pin fcCSP....................................................................................................................... 14
4.3 Pin Multiplexing................................................................................................................... 17
5
Electrical Specification............................................................................................................... 18
5.1 Absolute Maximum Ratings ................................................................................................ 18
5.2 Recommended Operating Conditions................................................................................. 18
5.3 Electrical Characteristics..................................................................................................... 19
5.3.1
5.3.2
5.3.3
DC Parameters for Normal GPIOs ...................................................................... 19
DC Parameters for RTC Block ............................................................................ 20
DC Parameters for Digital Wake-Up.................................................................... 20
5.4 Radio Characteristics.......................................................................................................... 21
5.4.1
5.4.2
WLAN Receiver Characteristics .......................................................................... 21
WLAN Transmitter Characteristics ...................................................................... 22
5.5 Current Consumption.......................................................................................................... 24
5.6 ESD Ratings........................................................................................................................ 25
5.7 Brown-Out and Black-Out................................................................................................... 26
5.8 Clock Electrical Characteristics........................................................................................... 26
5.8.1
5.8.2
RTC Clock Source............................................................................................... 26
Main Clock Source............................................................................................... 28
6
Power Management..................................................................................................................... 29
6.1 Power On Sequence........................................................................................................... 29
6.2 Power Management Unit..................................................................................................... 30
6.3 Low Power Operation Mode ............................................................................................... 31
6.3.1
6.3.2
6.3.3
Sleep Mode 1....................................................................................................... 31
Sleep Mode 2....................................................................................................... 31
Sleep Mode 3....................................................................................................... 31
7
Core System ................................................................................................................................ 31
7.1 Arm Cortex-M4F Processor ................................................................................................ 31
7.2 Wi-Fi Processor................................................................................................................... 32
7.3 Memory ............................................................................................................................... 32
7.3.1
Internal Memory................................................................................................... 32
7.4 RTC..................................................................................................................................... 36
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DA16200
Ultra Low Power Wi-Fi SoC
7.4.1
7.4.2
Wake-up Controller.............................................................................................. 36
Retention I/O Function......................................................................................... 37
7.5 Pulse Counter ..................................................................................................................... 38
7.5.1
7.5.2
Introduction .......................................................................................................... 38
Functional Description ......................................................................................... 38
7.6 HW Accelerators ................................................................................................................. 39
7.6.1
7.6.2
7.6.3
Zeroing of SRAM ................................................................................................. 39
CRC Calculation .................................................................................................. 39
Pseudo Random Number Generator (PRNG)..................................................... 39
7.7 DMA Operation ................................................................................................................... 40
7.7.1
7.7.2
DMA1................................................................................................................... 40
DMA2 (Fast DMA) ............................................................................................... 42
7.8 Simple Memory Protection.................................................................................................. 43
7.9 Bus Protection of Serial Slave Interfaces............................................................................ 44
7.10 Watchdog Timer.................................................................................................................. 44
7.11 Clock Generator.................................................................................................................. 46
8
9
Crypto Engine.............................................................................................................................. 47
Peripherals................................................................................................................................... 48
9.1 QSPI Master with XIP Feature............................................................................................ 48
9.2 SPI Master .......................................................................................................................... 50
9.3 SPI Slave ............................................................................................................................ 51
9.4 SDIO.................................................................................................................................... 54
9.5 I2C Interface........................................................................................................................ 55
9.5.1
9.5.2
I2C Master ........................................................................................................... 55
I2C Slave ............................................................................................................. 57
9.6 SD/SDeMMC....................................................................................................................... 58
9.6.1 Block Diagram ..................................................................................................... 58
9.7 I2S....................................................................................................................................... 59
9.7.1
9.7.2
9.7.3
Block Diagram ..................................................................................................... 60
I2S Clock Scheme ............................................................................................... 61
I2S Transmit and Receive Timing Diagram......................................................... 62
9.8 ADC (Aux 12-bit)................................................................................................................. 64
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
Overview.............................................................................................................. 64
Timing Diagram ................................................................................................... 64
DMA Transfer ...................................................................................................... 65
Sensor Wake-up.................................................................................................. 65
ADC Ports............................................................................................................ 65
9.9 GPIO ................................................................................................................................... 66
9.9.1
Antenna Switching Diversity ................................................................................ 66
............................................................................................................................. 67
9.10 UART
9.10.1 RS-232................................................................................................................. 69
9.10.2 RS-485................................................................................................................. 69
9.10.3 Baud Rate............................................................................................................ 70
9.10.4 Hardware Flow Control........................................................................................ 70
9.10.5 Interrupts.............................................................................................................. 71
9.10.6 DMA Interface...................................................................................................... 71
9.11 PWM
............................................................................................................................. 72
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DA16200
Ultra Low Power Wi-Fi SoC
9.11.1 Timing Diagram ................................................................................................... 73
9.12 Debug Interface................................................................................................................... 73
9.13 Bluetooth Coexistence ........................................................................................................ 75
9.13.1 Interface Configuration ........................................................................................ 75
9.13.2 Operation Scenario.............................................................................................. 75
10 Applications Schematic.............................................................................................................. 76
10.1 Typical Application: QFN, 3.3 V Flash ................................................................................ 76
10.2 Typical Application: QFN, 1.8 V Flash ................................................................................ 78
10.3 Typical Application: fcCSP,1.8 V Flash Normal Power Mode............................................. 80
10.4 Typical Application: fcCSP,1.8 V Flash Low Power Mode.................................................. 82
11 Package Information................................................................................................................... 84
11.1 Moisture Sensitivity Level (MSL)......................................................................................... 84
11.2 Top View: QFN and fcCSP ................................................................................................. 84
11.3 Dimension: 48-Pin QFN ...................................................................................................... 85
11.4 Dimension: 72-Pin fcCSP.................................................................................................... 86
11.5 Land Pattern: 48-Pin QFN .................................................................................................. 87
11.6 Land Pattern: 72-Pin fcCSP................................................................................................ 88
11.7 Soldering Information.......................................................................................................... 89
11.7.1 Recommended Condition for Reflow Soldering .................................................. 89
12 Ordering Information .................................................................................................................. 91
Revision History ................................................................................................................................ 92
Figures
Figure 1: System Diagram..................................................................................................................... 3
Figure 2: Hardware Block Diagram ..................................................................................................... 11
Figure 3: Software Block Diagram....................................................................................................... 11
Figure 4: DA16200 QFN48 Pinout Diagram (Top View) ..................................................................... 13
Figure 5: DA16200 fcCSP72 Pinout Diagram (Top View)................................................................... 14
Figure 6: Brown-Out and Black-Out Levels......................................................................................... 26
Figure 7: RTC Crystal Connections - QFN.......................................................................................... 27
Figure 8: RTC Crystal Connections – fcCSP ...................................................................................... 27
Figure 9: Crystal Clock Connections - QFN ........................................................................................ 28
Figure 10: Crystal Clock Connections - fcCSP.................................................................................... 28
Figure 11: Power On Sequence .......................................................................................................... 29
Figure 12: Power Management Block Diagram................................................................................... 30
Figure 13: OTP Block Diagram ........................................................................................................... 33
Figure 14: Memory Map ...................................................................................................................... 35
Figure 15: Memory Map: Peripherals.................................................................................................. 35
Figure 16: Pulse Counter Block Diagram............................................................................................ 38
Figure 17: DMA1 Controller Block Diagram ........................................................................................ 40
Figure 18: DMA1 State Machine ......................................................................................................... 41
Figure 19: DMA2 Block Diagram......................................................................................................... 43
Figure 20: Watchdog Timer Block Diagram ........................................................................................ 44
Figure 21: Watchdog Operation Flow Diagram................................................................................... 45
Figure 22: Clock Tree Diagram ........................................................................................................... 46
Figure 23: QSPI Master Block Diagram .............................................................................................. 49
Figure 24: QSPI Master Timing Diagram (Mode 0)............................................................................. 49
Figure 25: SPI Master Timing Diagram (Mode 0)................................................................................ 50
Figure 26: SPI Slave Block Diagram ................................................................................................... 51
Figure 27: 8-byte Control Type............................................................................................................ 51
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DA16200
Ultra Low Power Wi-Fi SoC
Figure 28: 4-byte Control Type............................................................................................................ 51
Figure 29: SPI Slave Timing Diagram ................................................................................................. 53
Figure 30: SDIO Slave Block Diagram................................................................................................ 54
Figure 31: SDIO Slave Timing Diagram.............................................................................................. 55
Figure 32: I2C Master Timing Diagram ............................................................................................... 56
Figure 33: I2C Slave Timing Diagram ................................................................................................. 57
Figure 34: SD/eMMC Block Diagram .................................................................................................. 59
Figure 35: SD/eMMC Master Timing Diagram .................................................................................... 59
Figure 36: I2S Block Diagram.............................................................................................................. 60
Figure 37: I2S Clock Scheme.............................................................................................................. 61
Figure 38: I2S Timing Diagram ........................................................................................................... 62
Figure 39: Left Justified Mode Timing Diagram................................................................................... 62
Figure 40: Right Justified Mode Timing Diagram ................................................................................ 62
Figure 41: I2S Transmit Timing Diagram ............................................................................................ 62
Figure 42: I2S Receive Timing Diagram ............................................................................................. 62
Figure 43: ADC Control Block Diagram............................................................................................... 64
Figure 44: 12-bit ADC Timing Diagram ............................................................................................... 64
Figure 45: Antenna Switching Internal Block Diagram........................................................................ 66
Figure 46: Antenna Switching Timing Diagram................................................................................... 67
Figure 47: DA16200 UART Block Diagram......................................................................................... 68
Figure 48: Serial Data Format............................................................................................................. 69
Figure 49: Receiver Serial Data Sampling Points ............................................................................... 69
Figure 50: UARTTXDOE Output Signal for UART RS-485................................................................. 69
Figure 51: UART Hardware Flow Control............................................................................................ 70
Figure 52: PWM Block Diagram .......................................................................................................... 72
Figure 53: PWM Timing Diagram ........................................................................................................ 73
Figure 54: JTAG Timing Diagram........................................................................................................ 73
Figure 55: Bluetooth Coexistence Interface ........................................................................................ 75
Figure 56: Typical Application – QFN, 3.3 V Flash ............................................................................. 76
Figure 57: Typical Application – QFN, 1.8 V Flash ............................................................................. 78
Figure 58: Typical Application – fcCSP, 1.8 V Flash, Normal Power Mode........................................ 80
Figure 59: Typical Application – fcCSP, 1.8 V Flash, Low Power Mode............................................. 82
Figure 60: DA16200 48-Pin QFN Package ......................................................................................... 84
Figure 61: DA16200 72-Pin fcCSP Package....................................................................................... 84
Figure 62: Top View ............................................................................................................................ 85
Figure 63: Bottom View ....................................................................................................................... 85
Figure 64: Side View ........................................................................................................................... 85
Figure 65: DA16200 48-Pin QFN Package Dimensions ..................................................................... 85
Figure 66: Top View ............................................................................................................................ 86
Figure 67: Bottom View ....................................................................................................................... 86
Figure 68: Side View ........................................................................................................................... 86
Figure 69: DA16200 72-Pin fcCSP Package Dimensions................................................................... 86
Figure 70: DA16200 48-Pin QFN Land Pattern................................................................................... 87
Figure 71: DA16200 72-Pin FcCSP Land Pattern............................................................................... 88
Figure 72: Typical PCB Mounting Process Flow................................................................................. 89
Figure 73: Reflow Condition ................................................................................................................ 90
Tables
Table 1: Pin Description ...................................................................................................................... 15
Table 2: Pin Type Definition ................................................................................................................ 16
Table 3: DA16200 Pin Multiplexing ..................................................................................................... 17
Table 4: Absolute Maximum Ratings................................................................................................... 18
Table 5: Recommended Operating Conditions ................................................................................... 18
Table 6: DC Parameters for Normal GPIOs, 1.8 V IO......................................................................... 19
Table 7: DC Parameters for Normal GPIOs, 3.3 V IO......................................................................... 19
Table 8: DC Parameters for RTC Block, 3.3 V VBAT ......................................................................... 20
Datasheet
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DA16200
Ultra Low Power Wi-Fi SoC
Table 9: DC Parameters for RTC Block, 2.1 V VBAT ......................................................................... 20
Table 10: DC Parameters for Digital Wake-Up, 3.3 V VBAT and 1.8/3.3 V IO................................... 20
Table 11: DC Parameters for Digital Wake-Up, 2.1 V VBAT and 1.8 V IO......................................... 20
Table 12: WLAN Receiver Characteristics – QFN .............................................................................. 21
Table 13: WLAN Receiver Characteristics – fcCSP............................................................................ 21
Table 14: WLAN Transmitter Characteristics – QFN .......................................................................... 22
Table 15: WLAN Transmitter Characteristics – fcCSP (Normal Power Mode) ................................... 22
Table 16: WLAN Transmitter Characteristics – fcCSP (Low Power Mode) ........................................ 23
Table 17: Current Consumption in Active State – QFN ...................................................................... 24
Table 18: Current Consumption in Active State – fcCSP (Normal Power Mode) ............................... 24
Table 19: Current Consumption in Active State – fcCSP (Low Power Mode) .................................... 24
Table 20: Current Consumption in Low Power Operation................................................................... 25
Table 21: QFN Package...................................................................................................................... 25
Table 22: fcCSP Package ................................................................................................................... 25
Table 23: Brown-Out and Black-Out Voltage Levels........................................................................... 26
Table 24: RTC Crystal Requirements ................................................................................................. 27
Table 25: WLAN Crystal Clock Requirements .................................................................................... 28
Table 26: Power On Sequence Timing Requirements........................................................................ 29
Table 27: OTP Map ............................................................................................................................. 34
Table 28: RTC Pin Description............................................................................................................ 36
Table 29: Wake-up Sources................................................................................................................ 36
Table 30: I/O Power Domain ............................................................................................................... 37
Table 31: DMA1 Served Peripherals................................................................................................... 41
Table 32: HW Acceleration Crypto Algorithms in DA16200................................................................ 47
Table 33: QSPI Master Timing Parameters ........................................................................................ 49
Table 34: SPI Master Pin Configuration.............................................................................................. 50
Table 35: SPI Master Timing Parameters ........................................................................................... 50
Table 36: Control Field of the 8-byte Control Type ............................................................................. 51
Table 37: Control Field of the 4-byte Control Type ............................................................................. 52
Table 38: SPI Slave Pin Configuration................................................................................................ 52
Table 39: SPI Slave Timing Parameters ............................................................................................. 53
Table 40: SDIO Slave Pin Configuration............................................................................................. 54
Table 41: SDIO Slave Timing Parameters .......................................................................................... 55
Table 42: I2C Master Pin Configuration .............................................................................................. 55
Table 43: I2C Master Timing Parameters ........................................................................................... 56
Table 44: I2C Slave Pin Configuration ................................................................................................ 57
Table 45: I2C Slave Timing Parameters ............................................................................................. 57
Table 46: SD/eMMC Master Pin Configuration ................................................................................... 58
Table 47: SD/eMMC Master Timing Parameters ................................................................................ 59
Table 48: I2S Pin Configuration .......................................................................................................... 60
Table 49: I2S Clock Selection Guide................................................................................................... 61
Table 50: I2S Transmit Timing Parameters......................................................................................... 63
Table 51: I2S Receive Timing Parameters.......................................................................................... 63
Table 52: DC Specification.................................................................................................................. 65
Table 53: ADC Pin Configuration ........................................................................................................ 65
Table 54: Control Bits to Enable and Disable Hardware Flow Control ............................................... 70
Table 55: UART Interrupt Signals ....................................................................................................... 71
Table 56: UART Pin Configuration...................................................................................................... 71
Table 57: PWM Pin Configuration....................................................................................................... 72
Table 58: PWM Timing Diagram Description ...................................................................................... 73
Table 59: JTAG Timing Parameters.................................................................................................... 74
Table 60: JTAG Pin Configuration....................................................................................................... 74
Table 61: Components for DA16200 QFN, 3.3 V Flash Mode............................................................ 77
Table 62: IO Power Domain ................................................................................................................ 77
Table 63: Component for DA16200 QFN, 1.8 V Flash Mode.............................................................. 79
Table 64: IO Power Domain ................................................................................................................ 79
Table 65: Component for DA16200 fcCSP, 1.8 V Flash, Normal Power Mode.................................. 81
Table 66: IO Power Domain ................................................................................................................ 81
Table 67: Component for DA16200 fcCSP, 1.8 V Flash, Low Power Mode....................................... 83
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DA16200
Ultra Low Power Wi-Fi SoC
Table 68: IO Power Domain ................................................................................................................ 83
Table 69: Typical Reflow Profile (Lead Free): J-STD-020C................................................................ 90
Table 70: Ordering Information (Samples).......................................................................................... 91
Table 71: Ordering Information (Production)....................................................................................... 91
Datasheet
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DA16200
Ultra Low Power Wi-Fi SoC
1
Terms and Definitions
API
Application Programming Interface
CRC
DMA
DAC
GPIO
HW
Cyclic Redundancy Check
Direct Memory Access
Digital-to-Analog Converter
General Purpose Input/Output
Hardware
I2C
Inter-Integrated Circuit
Inter-IC Sound
I2S
IoT
Internet of Things
JTAG
LDO
LLI
Joint Test Action Group
Low-Dropout Regulator
Linked-List Item
NVIC
NVRAM
PLL
Nested Vectored Interrupt Controller
Non-Volatile RAM
Phase-Locked Loop
PRNG
PWM
QSPI
RTC
SAR ADC
SPI
Pseudo Random Number Generator
Pulse Width Modulation
Quad-Lane SPI
Real-Time Clock
Successive Approximation Analog-to-Digital Converter
Serial Peripheral Interface
Software
SW
SWD
UART
XIP
Serial Wire Debug
Universal Asynchronous Receivers and Transmitter
eXecute in Place
TAP
Test Access Port
2
References
[1] ARM Cortex M4 Processor Technical Reference Manual
[2] DA16200_Example_Application_Guide.pdf
[3] ITU-T O.150, General Requirements for Instrumentation for Performance Measurements on
Digital Transmission Equipment, 1996
[4] Arm TrustZone® CryptoCell-312, Software Integrators Manual, Revision r1p1.
[5] IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture
[6] DA16200_SDK_Programmer_Guide.pdf
[7] AMBA AHB bus specification, Revision 3.0 https://developer.arm.com/documentation/ihi0033/bb
Datasheet
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DA16200
Ultra Low Power Wi-Fi SoC
3
Block Diagram
Figure 2 shows the DA16200 hardware (HW) block diagram.
Figure 2: Hardware Block Diagram
Figure 3 shows the DA16200 software (SW) block diagram.
User Application
Home Appliance/Sensor Network/Door Lock/Light, IoT.
Provisioning
Protocol
mDNS / xmDNS / DNS-SD / CoAP / Jason
NetX-APP
DHCP/ DNS/ HTTP1.0 / HTTP1.1
CLI Handler
upper Level
TLS / DTLS
Wi-Fi
Supplicant
TCP/UDP
NetX-Duo
80211 Link Layer
IP
802.11 Upper MAC
802.11 Lower MAC
ThreadX
RTOS
Wi-Fi PHY
Device Driver
Figure 3: Software Block Diagram
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DA16200
Ultra Low Power Wi-Fi SoC
The following descriptions are about the SW block diagrams:
●
Kernel layer
○
Real Time Operating System
●
The Wi-Fi layer is divided into four layers:
○
Lower MAC
– SW module to control/handle HW Wi-Fi MAC/PHY and interfaces with Upper MAC layer
Upper MAC
○
– SW module to control/handle Wi-Fi control/handle to interface with supplicant
– Wi-Fi Link layer: Interface layer between Upper MAC and supplicant
– Supplicant: SW module to control/management to operate Wi-Fi operation
Network subsystem layer
○
○
– Used to control/handle network operation
– Main protocols are IP, TCP, and UDP
– Other necessary protocols are supported
Security layer
– Crypto operation engine is ported to use crypto HW engine
●
TLS/TCP and DTLS/UDP APIs are supported to handle security operation:
○
User application layer
– Variable sample codes are supported in SDK – sample codes use supported APIs
– TCP Client/Server, UDP Client/Server, TLS Client/Server
– HTTP/HTTPs download, OTA Update usage, and MQTT usage
Customer applications can be included and implemented easily in the SDK.
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DA16200
Ultra Low Power Wi-Fi SoC
4
Pinout
4.1 48-Pin QFN
Figure 4: DA16200 QFN48 Pinout Diagram (Top View)
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DA16200
Ultra Low Power Wi-Fi SoC
4.2 72-Pin fcCSP
A7
A5
RTC_PWR_
KEY
A1
A3
A9
A11
VDD_DA
/PA
GND
GPIOA0
GND
ANT
B8
B2
B4
B6
B10
B12
VDD_DA
/PA
GPIOA2
RTC_XI
GND
GND
GND
C1
C3
C5
C7
C9
C11
VDD_DI
O1
GPIOA1
RTC_XO
GND
GND
GND
D6
D12
D2
D4
D8
D10
RTC_WA
KE_UP
VDD_AN
A
GPIOA5
GPIOA3
GND
GND
E7
E1
E3
E5
E9
E11
RTC_GP
O
GPIOA7
GPIOA6
GND
GND
RBIAS
F2
F4
F6
F8
F10
F12
GPIOA10
GPIOA4
GND
GND
GND
GND
G1
G3
G5
G7
G9
G11
GPIOA11
GPIOA8
GND
GND
GND
RF_XI
H6
H2
H8
H10
H12
H4
RTC_WA
KE_UP2
GPIOA9
GND
GND
RF_XO
GND
J3
J5
J7
J9
J11
J1
DCDC_FB
GND
F_CSN
F_IO2
TCLK
TMS
K12
K2
K6
K10
K4
K8
GPIOC7
GND
F_IO3
GPIOC8
F_CLK
F_IO0
L3
L9
L1
L5
L7
L11
VDD_DI
G
UART_T
XD
DCDC_LX
GND
F_IO1
GPIOC6
M10
M4
M6
M12
M2
M8
UART_R
XD
VDD_FDI
O
GND
GND
VBAT
DIO2
Figure 5: DA16200 fcCSP72 Pinout Diagram (Top View)
Datasheet
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Ultra Low Power Wi-Fi SoC
Table 1: Pin Description
QFN
#Pin
fcCSP Pin Name
#Pin
Type
Drive
(mA)
Initial
State
Description
(Table 2)
(Note 1)
1
2
3
4
5
6
7
GND
GND
VDD
AIO
AI
Ground
D12
E11
G11
H12
J11
J9
VDD_ANA
RBIAS
RF_XI
RF_XO
TMS
RF VDD
External reference resistor pin
40 MHz crystal clock input
40 MHz crystal clock output
JTAG I/F, SWDIO
AO
DIO
DIO
2/4/8/12
2/4/8/12
I-PU
I-PD
TCLK
JTAG I/F, SWCLK, General Purpose
I/O
8
K10
K12
L11
L9
GPIOC8
DIO
DIO
DIO
DO
2/4/8/12
2/4/8/12
2/4/8/12
2/4/8/12
2/4/8/12
I-PD
I-PD
I-PD
O
General Purpose I/O
General Purpose I/O
General Purpose I/O
UART transmit data
UART receive data
9
GPIOC7
10
11
12
13
GPIOC6
UART_TXD
UART_RXD
VDD_DIO2
M10
M8
DI
I
VDD
Supply power for digital I/O
GPIOC6~GPIOC8, TMS/TCLK,
TXD/RXD
14
15
16
17
18
19
20
21
K8
L7
J7
F_IO0
DIO
DIO
DIO
DIO
DIO
DIO
VDD
AIO
External Flash Memory I/F
External Flash Memory I/F
External Flash Memory I/F
External Flash Memory I/F
External Flash Memory I/F
External Flash Memory I/F
Flash IO Power
F_IO1
F_IO2
K6
J5
F_IO3
F_CSN
F_CLK
VDD_FDIO
K4
M4
FDIO_LDO_
OUT
Flash and IO LDO output and connect
to external cap. For flash LDO
22
23
24
25
26
L3
H6
M2
L1
J1
VDD_DIG
VDD
DI
Digital power and connect to external
cap. For DIG LDO
RTC_WAKE
_UP2
RTC block wake-up signal
VBAT
VDD
AIO
AIO
Supply power for internal DC-DC,
DIO_LDO, and analog IP
DCDC_LX
DCDC_FB
Connection from power MOSFETs to
the Inductor in internal DCDC
Feedback voltage from the output of
the power supply in internal DCDC
27
28
29
30
31
G1
F2
H2
G3
E1
GPIOA11
GPIOA10
GPIOA9
GPIOA8
GPIOA7
DIO
DIO
DIO
DIO
DIO
2/4/8/12
2/4/8/12
2/4/8/12
2/4/8/12
2/4/8/12
I-PD
I-PD
I-PD
I-PD
I-PD
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
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DA16200
Ultra Low Power Wi-Fi SoC
32
33
34
35
E3
D2
F4
C1
GPIOA6
GPIOA5
GPIOA4
VDD_DIO1
DIO
DIO
DIO
VDD
2/4/8/12
2/4/8/12
2/4/8/12
I-PD
I-PD
I-PD
General Purpose I/O
General Purpose I/O
General Purpose I/O
Supply power for digital I/O
GPIOA0~GPIOA11
36
37
38
39
40
41
42
D4
B2
C3
A3
C5
B4
A5
GPIOA3
GPIOA2
GPIOA1
GPIOA0
RTC_XO
RTC_XI
AI/DIO
AI/DIO
AI/DIO
AI/DIO
AO
2/4/8/12
2/4/8/12
2/4/8/12
2/4/8/12
I-PD
I-PD
I-PD
I-PD
Aux.ADC input/General Purpose I/O
Aux.ADC input/General Purpose I/O
Aux.ADC input/General Purpose I/O
Aux.ADC input/General Purpose I/O
32.768 kHz crystal clock output
32.768 kHz crystal clock input
AI
RTC_PWR_
KEY
DI
RTC block enable signal
43
D6
RTC_WAKE
_UP
DI
RTC block wake-up signal
44
45
46
E7
RTC_GPO
VDD_DA
VDD_PA
DO
General Purpose Output
A7,
B8
VDD
VDD
Tx DA power and RTC block power
Supply power for integrated power
amplifier
47
48
GND
ANT
GND
AI
Ground
ANT
A11
fcCSP GND Pin A1, A9, B6, B10, B12, C7, C9, C11, D8, D10, E5, E9, F6, F8, F10, F12, G5, G7, G9, H4, H8,
H10, J3, K2, L5, M6, M12
Note 1 Status of RTC_PWR_KEY is asserted and digital power (VDD_DIG) is stable.
Table 2: Pin Type Definition
Pin Type
DI
Description
Pin Type
AI
Description
Digital input
Analog input
DO
Digital output
AO
Analog output
DIO
Digital input/output
Digital input/output open drain
Pull-up resistor (fixed)
Pull-down resistor (fixed)
Power
AIO
Analog input/output
Back drive protection
Switchable pull-up resistor
Switchable pull-down resistor
Ground
DIOD
PU
BP
SPU
SPD
GND
PD
PWR
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Ultra Low Power Wi-Fi SoC
4.3 Pin Multiplexing
This device provides various interfaces to support many kinds of applications. It is possible to control
each pin according to the required application in reference to the pin multiplexing illustrated in
Table 3. Pin control can be realized through register setting. This device can use a maximum of 16
GPIO pins and each of the GPIO pins multiplexes signals of various functions. In particular, four pins
from GPIOA0 to GPIOA3 multiplex analog signals, which also can be realized through register
setting.
Table 3: DA16200 Pin Multiplexing
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Ultra Low Power Wi-Fi SoC
5
Electrical Specification
5.1 Absolute Maximum Ratings
Table 4: Absolute Maximum Ratings
Parameter
QFN Pins
fcCSP Pins
Min
VSS
Max
Units
VBAT, VDD_DA, VDD_PA
VDD_DIO1
24, 45, 46
M2, A7,B8
3.9
3.9
3.9
3.9
3.9
V
V
V
V
V
V
V
°C
35
13
20
21
22
2
C1
M8
M4
-
VSS
VSS
VSS
VSS
VSS
VSS
-40
VDD_DIO2
VDD_FDIO
FDIO_LDO_OUT
VDD_DIG
L3
D12
1.32
1.65
+85
VDD_ANA
Operating temperature range (TA)
5.2 Recommended Operating Conditions
Table 5: Recommended Operating Conditions
Parameter
QFN Pins
fcCSP Pins
Min
Typ
Max
3.6
Units
M2, A7, B8
(Note 1)
VBAT, VDD_DA, VDD_PA
24, 45, 46
2.1
V
V
A7, B8
VDD_DA, VDD_PA
-
1.45
(Note 2)
VDD_DIO1
VDD_DIO2
VDD_FDIO
FDIO_LDO_OUT
VDD_DIG
35
13
20
21
22
C1
M8
M4
-
1.62
1.62
1.62
1.62
3.6
V
V
V
V
V
3.6
3.6
1.92
L3
1.1
1.37
(Note 2)
VDD_ANA
2
D12
V
Operating temperature range (TA)
-40
+85
°C
Note 1 QFN, fcCSP Normal power mode.
Note 2 fcCSP Low power mode.
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Ultra Low Power Wi-Fi SoC
5.3 Electrical Characteristics
5.3.1
DC Parameters for Normal GPIOs
Table 6: DC Parameters for Normal GPIOs, 1.8 V IO
Parameter
Symbol Condition
Min
Typ
Max
Units
Guaranteed logic Low
level
0.3 ×
DVDD
Input Low Voltage
VIL
VIH
VSS
V
Guaranteed logic High
level
Input High Voltage
0.7 × DVDD
DVDD
V
0.2 ×
DVDD
Output Low Voltage VOL
Output High Voltage VOH
DVDD=Min.
VSS
V
V
DVDD=Min.
0.8 × DVDD
DVDD
32.4
Pull-up Resistor
RPU
RPD
VPAD=VIH, DIO=Min.
VPAD=VIL, DIO=Min.
kΩ
Pull-down Resistor
32.4
(DVDD = 1.8 V, VDD_DIO1, VDD_DIO2 Logic Level)
Table 7: DC Parameters for Normal GPIOs, 3.3 V IO
Parameter
Symbol Condition
Min
Typ
Max
Units
Guaranteed logic Low
level
Input Low Voltage
VIL
VIH
VSS
0.8
V
Guaranteed logic High
level
Input High Voltage
2.0
DVDD
V
Output Low Voltage VOL
Output High Voltage VOH
DVDD=Min.
VSS
2.4
0.4
DVDD
19.4
V
V
DVDD=Min.
Pull-up Resistor
RPU
RPD
VPAD=VIH, DIO=Min.
VPAD=VIL, DIO=Min.
kΩ
Pull-down Resistor
16.0
(DVDD= 3.3 V, VDD_DIO1, VDD_DIO2 Logic Level)
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Ultra Low Power Wi-Fi SoC
5.3.2
DC Parameters for RTC Block
There are several control pins in the RTC block. For details, see Section 7.4.
Table 8: DC Parameters for RTC Block, 3.3 V VBAT
Parameter
Symbol Condition
Min
Typ
Max
Units
Guaranteed logic Low
level
Input Low Voltage
VIL
VIH
VSS
0.6
V
Guaranteed logic High
level
Input High Voltage
2.2
VBAT
V
(RTC block: RTC_PWR_KEY, RTC_WAKE_UP, RTC_WAKE_UP2)
Table 9: DC Parameters for RTC Block, 2.1 V VBAT
Parameter
Symbol Condition
Min
Typ
Max
Units
Guaranteed logic Low
level
Input Low Voltage
VIL
VIH
VSS
0.3
V
Guaranteed logic High
level
Input High Voltage
1.6
VBAT
V
(RTC block: RTC_PWR_KEY, RTC_WAKE_UP, RTC_WAKE_UP2)
5.3.3
DC Parameters for Digital Wake-Up
Several GPIOs can be used for wake-up. For details, see Section 7.4.1.
To use Digital Wake-up, the IO voltage should not be higher than the VBAT value.
Table 10: DC Parameters for Digital Wake-Up, 3.3 V VBAT and 1.8/3.3 V IO
Parameter
Symbol Condition
Min
Typ
Max
Units
Guaranteed logic Low
level
Input Low Voltage
VIL
VIH
VSS
0.5
V
Guaranteed logic High
level
Input High Voltage
1.4
DVDD
V
(DVDD= 1.8/3.3 V, VDD_DIO1, VDD_DIO2 Logic Level, DVDD should not be higher than the VBAT value)
Table 11: DC Parameters for Digital Wake-Up, 2.1 V VBAT and 1.8 V IO
Parameter
Symbol Condition
Min
Typ
Max
Units
Guaranteed logic Low
level
Input Low Voltage
VIL
VIH
VSS
0.3
V
Guaranteed logic High
level
Input High Voltage
1.3
DVDD
V
(DVDD= 1.8 V, VDD_DIO1, VDD_DIO2 Logic Level, DVDD should not be higher than the VBAT value)
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Ultra Low Power Wi-Fi SoC
5.4 Radio Characteristics
5.4.1
WLAN Receiver Characteristics
TA = +25 °C, VBAT = 3.3 V. Parameters are measured at ANT pin on CH1 (2412 MHz).
Table 12: WLAN Receiver Characteristics – QFN
Parameter
Condition
Min
-100.5
-96
-91
-92
-92
-90
-83
-77
-92
-74
-4
Typ
-99.5
-95
-90
-91
-91
-89
-82
-76
-91
-73
0
Max
-97.5
-93
-88
-89
-89
-87
-80
-74
-89
-71
0
Units
1 Mbps DSSS
2 Mbps DSSS
11 Mbps CCK
6 Mbps OFDM
9 Mbps OFDM
18 Mbps OFDM
36 Mbps OFDM
54 Mbps OFDM
MCS0(GF)
Sensitivity
(8 % PER for 11b rates,
10 % PER for 11g/11n rates)
dBm
MCS7(GF)
Maximum input level
802.11b
(8 % PER for 11b rates,
10 % PER for 11g/11n rates)
802.11g
-10
-4
-3
Table 13: WLAN Receiver Characteristics – fcCSP
Parameter
Condition
Min
-100.5
-96
-91
-92
-92
-90
-83
-77
-92
-74
-4
Typ
-99.5
-95
-90
-91
-91
-89
-82
-76
-91
-73
0
Max
-97.5
-93
-88
-89
-89
-87
-80
-74
-89
-71
0
Units
1Mbps DSSS
2Mbps DSSS
11Mbps CCK
6Mbps OFDM
9Mbps OFDM
18Mbps OFDM
36Mbps OFDM
54Mbps OFDM
MCS0(GF)
Sensitivity
(8 % PER for 11b rates,
10 % PER for 11g/11n rates)
dBm
MCS7(GF)
Maximum input level
802.11b
(8 % PER for 11b rates,
10 % PER for 11g/11n rates)
802.11g
-10
-4
-3
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Ultra Low Power Wi-Fi SoC
5.4.2
WLAN Transmitter Characteristics
TA = +25 °C, VBAT = 3.3 V. Parameters are measured at ANT pin on CH1 (2412 MHz).
Table 14: WLAN Transmitter Characteristics – QFN
Parameter
Condition
Min
17.5
17.5
17.5
17.5
16.5
16.5
16.5
16.5
15.5
15.5
14.0
13.0
16.5
13.0
-20
Typ
20.0
20.0
20.0
20.0
19.0
19.0
19.0
19.0
18.0
18.0
16.5
15.5
19.0
15.5
Max
21.0
21.0
21.0
21.0
20.0
20.0
20.0
20.0
19.0
19.0
17.5
16.5
20.0
16.5
+20
Units
1 Mbps DSSS
2 Mbps DSSS
5.5 Mbps CCK
11 Mbps CCK
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
18 Mbps OFDM
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
MCS0 OFDM
MCS7 OFDM
Maximum Output Power measured
from IEEE spectral mask and EVM
dBm
Transmit center frequency accuracy
ppm
Table 15: WLAN Transmitter Characteristics – fcCSP (Normal Power Mode)
Parameter
Condition
Min
16.0
16.0
16.0
16.0
15.5
15.5
15.5
15.5
14.5
14.5
13.0
12.0
15.5
12.0
-20
Typ
18.5
18.5
18.5
18.5
18.0
18.0
18.0
18.0
17.0
17.0
15.5
14.5
18.0
14.5
Max
19.5
19.5
19.5
19.5
19.0
19.0
19.0
19.0
18.0
18.0
16.5
15.5
19.0
15.5
+20
Units
1 Mbps DSSS
2 Mbps DSSS
5.5 Mbps CCK
11 Mbps CCK
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
18 Mbps OFDM
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
MCS0 OFDM
MCS7 OFDM
Maximum Output Power measured
form IEEE spectral mask and EVM
dBm
Transmit center frequency accuracy
ppm
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Ultra Low Power Wi-Fi SoC
Table 16: WLAN Transmitter Characteristics – fcCSP (Low Power Mode)
Parameter
Condition
Min
7.5
7.5
7.5
7.5
6.0
6.0
6.0
6.0
3.5
3.5
0
Typ
9.5
9.5
9.5
9.5
8.0
8.0
8.0
8.0
5.5
5.5
2.0
2.0
8.0
2.0
Max
10.5
10.5
10.5
10.5
9.0
Units
dBm
ppm
1 Mbps DSSS
2 Mbps DSSS
5.5 Mbps CCK
11 Mbps CCK
6 Mbps OFDM
9 Mbps OFDM
12 Mbps OFDM
18 Mbps OFDM
24 Mbps OFDM
36 Mbps OFDM
48 Mbps OFDM
54 Mbps OFDM
MCS0 OFDM
MCS7 OFDM
9.0
9.0
Maximum Output Power measured
form IEEE spectral mask and EVM
9.0
6.5
6.5
3.0
0
3.0
6.0
0
9.0
3.0
Transmit center frequency accuracy
-20
+20
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Ultra Low Power Wi-Fi SoC
5.5 Current Consumption
TA = +25 °C, VBAT = 3.3 V, w/ CPU clock 80 MHz.
Table 17: Current Consumption in Active State – QFN
Parameter
Condition
1 Mbps DSSS
Min
260
240
180
180
25
Typ
280
260
200
200
29
Max
320
300
240
240
51
Units
@ 20.0 dBm
@ 19.0 dBm
@ 15.5 dBm
@ 15.5 dBm
6 Mbps OFDM
54 Mbps OFDM
MCS7
TX
RX
ACTIVE
No signal (Note 1)
mA
1 Mbps DSSS (Note 1)
1 Mbps DSSS
54 Mbps OFDM
MCS7
26.5
27
30.5
37.5
38.5
38.6
53
54
29
54
29
54
Note 1 Low Current Mode and CPU clock 30 MHz.
Table 18: Current Consumption in Active State – fcCSP (Normal Power Mode)
Parameter
Condition
1 Mbps DSSS
Min
250
230
190
190
25
Typ
270
250
210
210
28.4
29.7
36.5
38
Max
310
290
250
250
51
Units
@ 18.5 dBm
@ 18.0 dBm
@ 14.0 dBm
@ 14.0 dBm
6 Mbps OFDM
54 Mbps OFDM
MCS7
TX
RX
ACTIVE
No signal (Note 1)
mA
1 Mbps DSSS (Note 1)
1 Mbps DSSS
54 Mbps OFDM
MCS7
26.5
27
53
54
29
54
29
38
54
Note 1 Low Current Mode and CPU clock 30 MHz.
Table 19: Current Consumption in Active State – fcCSP (Low Power Mode)
Parameter
Condition
1 Mbps DSSS
Min
63
Typ
85
Max
100
100
90
Units
@ 9.5 dBm
@ 8.0 dBm
@ 2.0 dBm
@ 2.0 dBm
6 Mbps OFDM
54 Mbps OFDM
MCS7
63
85
TX
RX
48
70
48
70
90
ACTIVE
No signal (Note 1)
25
28.4
29.7
37.5
39.2
39.2
51
mA
1 Mbps DSSS (Note 1)
1 Mbps DSSS
54 Mbps OFDM
MCS7
26.5
27
53
54
29
54
29
54
Note 1 Low Current Mode and CPU clock 30 MHz.
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Ultra Low Power Wi-Fi SoC
Table 20: Current Consumption in Low Power Operation
Parameter
Condition
Sleep 1
Sleep 2
Sleep 3
Min
Typ
0.2
1.8
3.5
Max
Units
Low Power Operation
µA
5.6 ESD Ratings
Table 21: QFN Package
Reliability Test
Standards
Test Conditions
± 2,000 V
Result
Human Body Model (HBM)
Charge Device Mode (CDM)
JEDEC EIA/JESD22-A114
JEDEC EIA/JESD22-C101
Pass
Pass
± 500 V
Table 22: fcCSP Package
Reliability Test
Standards
Test Conditions
± 2,000 V
Result
Pass
Human Body Model (HBM)
Charge Device Mode (CDM)
JEDEC EIA/JESD22-A114
JEDEC EIA/JESD22-C101
± 500 V
Pass
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Ultra Low Power Wi-Fi SoC
5.7 Brown-Out and Black-Out
The device enters a brown-out condition whenever the input voltage dips below VBROWN (see
Table 23). This condition must be considered during design of the power supply routing, especially if
the SoC is operated from a battery. High-current operations, like TX operation, cause a dip in the
supply voltage, potentially triggering a Brown-Out. The resistance includes the internal resistance of
the battery, contact resistance of the battery holder (for example, four contacts for two AA batteries),
wiring resistance, and PCB routing resistance.
Brown-Out
Operated
Condition
Brown-Out
Operated
Condition
Normal operated Condition
Black-Out Operated Condition
Normal operated Condition
VBAT(V)
Battery Discharge
Exit ＂Brown-Out＂ Condition
Exit ＂Black-Out＂ Condition
Enter ＂Black-Out＂ Condition
-> Battery Voltage is down
Enter ＂Brown-Out＂ Condition
Time(sec)
Time(sec)
Time(sec)
BR_OUT_VBAT(V)
Brown-Out Detector Hysteresis
BL_OUT_VBAT(V)
Black-Out Detector
Hysteresis
Figure 6: Brown-Out and Black-Out Levels
Brown-out and black-out conditions only operate in normal mode. The black-out condition is
equivalent to a hardware reset event in which all states within the device are lost. Table 23 lists the
brown-out and black-out voltage levels.
Table 23: Brown-Out and Black-Out Voltage Levels
Condition
Vbrown-out
Vblack-out
Voltage
2.10 V (Note 1)
1.75 V (Note 1)
Hysteresis
Operation
S/W Control
Full boot
90 mV
90 mV
Note 1 Recommended voltage level. Adjustable depending on the application condition.
5.8 Clock Electrical Characteristics
DA16200 needs two clock sources. One is the 32.768 kHz clock used by the RTC block, and the
other is the 40 MHz clock for the internal processor and Wi-Fi system. More specifically, the 40 MHz
clock is used as a source clock for the internal PLL, while the PLL output is used for the internal
processor and Wi-Fi system block.
5.8.1
RTC Clock Source
The 32.768 kHz RTC clock source is necessary for the free-running counter in the RTC block. The
RTC block of the SoC contains an internal 32.768 kHz RC oscillator as well, which is used as a clock
for chip initialization before the external 32.768 kHz crystal reaches the stable time in the initial stage.
It is necessary to convert it into an external clock for accurate clock counting after the initialization
stage. This process is executed through the register setting. Table 24 shows the suitable loading
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capacitor value and required tolerance. Figure 7 and Figure 8 show connections for the RTC crystal
clock.
RTC_XI 41
32.768kHz
RTC_XO 40
Figure 7: RTC Crystal Connections - QFN
RTC_XI B4
32.768kHz
RTC_XO C5
Figure 8: RTC Crystal Connections – fcCSP
Table 24 lists the RTC crystal requirements.
Table 24: RTC Crystal Requirements
Parameter
Condition
Min
Typ
Max
Units
kHz
ppm
Ω
Frequency
32.768
Frequency accuracy
Crystal ESR
Initial + temp + aging
-250
+250
90
32.768 kHz, C1 = C2 = 9 pF
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5.8.2
Main Clock Source
DA16200 contains a crystal oscillator for the main clock source which supports the external crystal
clock. Basically, the external clock is 40 MHz. Table 25 shows the load capacitor value and required
clock tolerance for 40 MHz. Figure 9 and Figure 10 show the crystal clock connections.
RF_XI 4
40MHz
RF_XO 5
Figure 9: Crystal Clock Connections - QFN
RF_XI G11
40MHz
RF_XO H12
Figure 10: Crystal Clock Connections - fcCSP
Table 25 lists the WLAN crystal requirements.
Table 25: WLAN Crystal Clock Requirements
Parameter
Condition
Min
Typ
Max
Units
MHz
Frequency
40
Frequency accuracy
Crystal ESR
Initial + temp + aging
-20
+20
60
ppm
40 MHz, C1 = C2 = 6 pF
Ω
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6
Power Management
DA16200 has an RTC block which provides power management and function control for low power
operation. In normal operation, the RTC block is always powered on when RTC_PWR_KEY is
enabled. The RTC block also has a control function for DA16200’s internal power supplying
components, like LDOs, DC-DCs, and power switches.
6.1 Power On Sequence
The sequence after the initial switching from power-off to power-on is shown in Figure 11.
The RTC_PWR_KEY of DA16200 is a pin that enables the RTC block. Once RTC_PWR_KEY is
enabled after VBAT power is supplied, all the internal regulators are turned on automatically in the
sequence predefined by the RTC block.
Once RTC_PWR_KEY is turned on, LDOs for both XTAL and digital I/O are turned on shortly and
then the DC-DC regulator is turned on according to the predefined interval. The enabling intervals
can also be modified in the register settings after initial power-up.
VBAT
50% VBAT
T0
IO Voltage
50% IO
POWER_KEY
CLK_32K
50% VBAT
T1
T2
T3
Figure 11: Power On Sequence
Table 26: Power On Sequence Timing Requirements
Name
T0
Description
Min
Typ
Max
Unit
ms
VBAT power-on time from 10 % to 90 % of VBAT
IO voltage and VCC supply
T1
0
ms
T2
RTC_PWR_KEY turn-on time from 50 % VBAT to
50 % POWER_KEY * Note 1
5*T0
ms
T3
Internal RC oscillator wake-up time
217
µs
Note 1 if the T0 = 10 ms to turn on VBAT, the recommended T2 is 50 ms for the safe booting operation. It
would be externally controlled by MCU or it would be implemented using RC filter at the input of
RTC_PWR_KEY. The recommended C is 470 nF or 1uF (not to exceed 1uF) and R value is chosen to
have T2 delay. For example, R and C values will be 82 kΩ and 1 uF when T0 = 10 ms.
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6.2 Power Management Unit
DA16200 has one internal DC-DC converter and several LDOs to supply power to all internal sub-
blocks. Power management does the on-off control of these regulators and is implemented through
the register setting inside the RTC block.
VDD_PA, VDD_RF
QFN,
fcCSP low power
fcCSP normal power
RF Block
1.4V
1.1V
DCDC
VBAT
Digital Core /
Memory
DIG_LDO
RTC Block
1.8V
Flash control
/ External
Flash Memory
FDIO_LDO
VDD_FDIO
VDD_DIO1
VDD_DIO2
Using the same power supply as
external device ( ex.CPU) ( 1.8V or 3.3V)
GPIOs
Figure 12: Power Management Block Diagram
Details of the internal DC-DC converters and LDOs are explained below:
●
●
●
DC-DC converter: from the power supply of external VBAT input, it generates 1.4 V power for the
digital LDO and RF block
LDO for digital Blocks: from the DC-DC output, it generates 1.1 V power which is used for digital
blocks
LDO for I/O and external flash memory:
○
○
This LDO output is used only for 1.8 V digital I/O applications
From external VBAT power input, it generates 1.8 V output voltage which is used for digital
I/O power domain in 1.8 V digital I/O applications
○
○
It is also used for external flash memory
For 3.3 V digital I/O applications, external power (3.3 V) is directly supplied for digital I/O
power
●
FDIO_LDO_OUT supports only 1.8 V
With the internal DC-DC converters and LDOs, all the power necessary for DA16200’s internal sub-
blocks are sufficiently generated.
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6.3 Low Power Operation Mode
DA16200 provides three Sleep modes as low power operation modes.
6.3.1
Sleep Mode 1
Sleep mode 1 is an operational mode in which the RTC_PWR_KEY is not turned to high yet. The
RTC_PWR_KEY is in the LOW state and the DA16200MOD is only supplied with VBAT power. With
all the internal blocks off in Sleep mode 1, only the leakage current from a minimal number of internal
blocks connected to VBAT remains.
6.3.2
Sleep Mode 2
Sleep mode 2 is an operational mode in which the RTC_PWR_KEY is set to high and the RTC block
is running. Sleep mode 2 is activated by setting RTC registers to control the power management unit
via a command from the CPU.
To turn Sleep mode 2 back to Sleep mode 1, set RTC_PWR_KEY to low.
Changing the state of the device from Sleep mode 2 to an ACTIVE state happens in one of two
ways:
●
●
The counter value is reached that is set by the CPU before entering Sleep mode 2
An external wake-up event occurs via the RTC_WAKE_UP pin
6.3.3
Sleep Mode 3
Sleep mode 3 is a low power but fully connected Wi-Fi mode of operation. Sleep mode 3 checks for
incoming Wi-Fi network data traffic at regular intervals set by the user. For example, every one
second, three seconds, five seconds, and so on. The exact time interval is programmable.
Sleep mode 3 is activated by software commands. For more information, see Ref. [6].
A device can come out of Sleep mode 3 and into a fully ACTIVE state before the next targeted wake-
up time interval via a GPIO wake-up.
7
Core System
7.1 Arm Cortex-M4F Processor
The Cortex-M4F processor is a low-power processor that features low gate count, low interrupt
latency, low-cost debug, and includes floating point arithmetic functionality. The processor is
intended for deeply embedded applications that require fast interrupt response features.
The features of the Cortex-M4F processor in DA16200 are summarized below:
■
■
■
■
■
■
■
Operation clock frequency is up to 160 MHz
32-bit Arm Cortex-M4F architecture optimized for embedded applications
Thumb-2 mixed 16/32-bit instruction set
Hardware division and fast multiplication
Includes Nested Vectored Interrupt Controller (NVIC)
SysTick timer provided by Cortex-M4F processor
Supports both standard JTAG (5-wire) and the low-pin-count Arm SWD (2-wire, TCLK/TMS)
debug interfaces
■
Cortex-M4F is binary compatible with Cortex-M3
For more information on the Arm Cortex-M4F, see Ref. [1].
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7.2 Wi-Fi Processor
DA16200 includes an internal MCU (Arm Cortex-M4F) to completely offload the host MCU along with
an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast and secure
WLAN and Internet connections with 256-bit encryption. It supports the station, SoftAP, and Wi-Fi
Direct modes. It also supports WPA/WPA2 personal and enterprise security, WPA2 SI, WPA3 SAE,
OWE, and WPS 2.0. It includes an embedded IPv4 and IPv6 TCP/IP stack.
7.3 Memory
7.3.1
Internal Memory
DA16200 contains four types of internal memories and also supports an external serial flash memory
interface. The roles and functions of each memory are described in the following subsections.
7.3.1.1
ROM
This memory contains boot loader, system kernel, network stack, and various kinds of drivers for
interfaces and peripherals.
7.3.1.2
SRAM
This memory is used as data space for all codes running on the internal CPU. All codes run on serial
flash memory via I-Cache (XIP mode). All the contents in this memory disappear in the low-power
Sleep mode.
The address range of the internal SRAM is from 0x0000_8000 to 0x0000_FFFF, and the controller of
this memory supports the swap operation for the internal CPU. To do a swap operation of the
controller, add the offset value to the SRAM address for read operation only.
If the offset value is 0x2080_0000, the controller will do a swap to reverse the byte order for a scalar
32-bit value. If the offset value is 0x2040_0000, the controller will do a swap to reverse the halfword
(16-bit) order for a scalar 32-bit value. For example, if the value of address 0x0000_8000 is
0x12345678, reading address 0x2080_8000 will output value 0x78563412 and reading address
0x2040_8000 will output value 0x56781234.
7.3.1.3
Retention Memory
This memory is a kind of non-volatile memory and is used to save and manage essential information
that should be preserved even in the low-power Sleep mode of the DA16200.
7.3.1.4
OTP
DA16200 includes a one-time electrically field programmable non-volatile CMOS memory. The array
can be programmed by 1 bit and read by 32 bits. Since the OTP controller is designed internally, it is
possible to execute read/write by commands through register setting.
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AHB-CPU
AHB Slave
OTP IF
OTP Controller
OTP Memory
Figure 13: OTP Block Diagram
This memory is to protect and manage major information essential for mass production and
management of products, such as booting information, MAC address, serial number, and others.
The OTP is also used for storing secret information which is used for the advanced security functions
like secure booting, secure debugging, and secure asset storage. But this secret information cannot
be accessed in a normal way of CPU read or write access so that it is protected from the external
access.
The OTP controller translates a request into the corresponding control sequence for the OTP cell to
be in one of the following modes:
●
●
●
Standby mode: it is used to reduce the power consumption when the OTP is not used
The OTP cell is powered but is less than the power consumption in Active mode
Operation mode: for the OTP to operate correctly, OTP must be in Operation mode
Program, Read, or Test mode can be operated after the Operation mode is set
○
○
Program mode: when OTP is instantiated, the SoC has all bits in 0s and 1s are loaded into the
SoC through programming
○
○
The program mode provides the functionality for programming a 1-bit into an OTP position
Immediately after programming the bit at the selected memory cell (program operation), a
verification operation follows to check for successful programming results with sufficient
margin
●
●
Read mode: in this mode, the contents of the OTP cell are read at reactive AHB address space
Test mode: tests can be performed during wafer sort, final test, or in-system/in-field, depending
on the test plan used by the end users
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Table 27: OTP Map
Offset
Field
Size (Bytes)
0x000
Dialog Reserved
1024
0x100
MAC Address #0 Low
MAC Address #0 High
MAC Address #1 Low
MAC Address #1 High
MAC Address #2 Low
MAC Address #2 High
MAC Address #3 Low
MAC Address #3 High
XTAL Offset #0
4
0x101
4
0x102
4
0x103
4
0x104
4
0x105
4
0x106
4
4
0x107
0x10A
4
0x10B
XTAL Offset #1
4
0x10C to 0x7FF
User Area
7128
7.3.1.5
Serial Flash Interface
DA16200 supports an external serial memory interface, QSPI, explained in Section 9.1. This memory
is used for storing DA16200’s software code, including user application code, its predefined data,
and various configuration data in the form of NVRAM.
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7.3.1.6
Memory Map
Figure 15 shows the various peripherals that are part of the DA16200 and how they are mapped to
the processor memory.
Address Map of Memories for Masters
0x2000_0000
Not used
Address Map of DA16200
0xFFFF_FFFF
Not used
0xF000_0000
System Control
Space(for CM4F)
0xE000_0000
0x00FC_0000
0x00F8_0000
Retention Memory
0x0020_0000
Not used
Not used
0x7000_0000
0x6000_0000
0x5000_0000
0x4000_0000
0x3000_0000
0x2000_0000
PHY
System Peripherals
APB Peripherals
Not used
0x0030_0000
0x0010_0000
I-Cache
Int. SRAM
Reserved
0x0008_0000
0x0004_0000
Not used
Memories
Mask ROM
0x0000_0000
0x0000_0000
Figure 14: Memory Map
0x5010_0000
0x500F_0000
Not used
PSK_SHA1
I-Cache Ctrl.
HSU
0x4001_0000
0x500E_0000
Reserved
0x4002_0000
DMA1
0x4000_F000
0x4000_E000
0x4020_0000
0x500D_0000
0x500C_0000
0x500B_0000
0x500A_0000
0x5009_0000
0x5008_0000
0x5007_0000
0x5006_0000
0x5005_0000
0x5004_0000
0x5003_0000
0x5002_0000
0x5001_0000
Flash Host Ctrl.
TA2SYNC
Reserved
Reserved
RTC Interface
Slave Interface
Reserved
0x4000_B000
0x4000_A000
0x4000_9000
0x4000_8000
0x4000_7000
PWM
Not used
0x4001_8000
UART2
GPIO2
0x4001_7000
WatchDog Timer
DMA2
Aux. ADC
I2C Master
0x4001_6000
UART1
Reserved
0x4001_5000
Reserved
Fast HW
Reserved
SD/eMMC
(SDIO Host)
0x4011_8000
0x4011_0000
0x4000_3000
0x4000_2000
0x4000_1000
0x4000_0000
0x4001_3000
CC312_APBC
CC312_APBS
Security
Dual Timer
0x4001_2000
Timer1
UART0
GPIO1
GPIO0
SDIO Device
0x4001_1000
System Controller
Timer0
0x5000_0000
0x4001_0000
0x4010_0000
APB Peripherals
System Peripherals
Figure 15: Memory Map: Peripherals
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7.4 RTC
Among the pins in DA16200, four special pins are directly connected to the RTC block, which are
RTC_PWR_KEY, RTC_GPO, RTC_WAKE_UP, and RTC_WAKE_UP2.
Table 28: RTC Pin Description
Pin Number
Pin Name
Description
QFN
fcCSP
RTC_PWR_KEY represents a power key for the RTC block. When
this pin is enabled, the RTC starts to work by following a
predefined power-up sequence and eventually all the necessary
power is supplied to all the sub-blocks including the main digital
block in DA16200. When disabled, all blocks are powered off and
this mode is defined as Sleep mode 1. DA16200 consumes
minimum leakage current in Sleep mode 1.
RTC_PWR_KEY
42
A5
This pin is an output and high level is 'VBAT'.
It has three different functions:
●
●
●
GPO function: its output value can be set as ‘1’ or ‘0’ via
register setting. It can keep the value even in Sleep mode
Flash control function: when in Sleep mode, it becomes ‘0’;
when in Active mode, it is ‘1’
RTC_GPO
44
E7
Sensor wake-up function: when the sensor wake-up function
is used (Section 9.8.4), a programmable periodic signal is
provided for an external device. Inside the RTC, there are
registers to set count values
This pin is an input pin for receiving an external event signal from
an external device like a sensor. The RTC block detects an
external event signal via this pin and wakes up DA16200 from
Sleep mode 2 or Sleep mode 3.
RTC_WAKE_UP
RTC_WAKE_UP2
43
23
D6
H6
DA16200 contains not only an on-chip oscillator that uses a 32.768 kHz external crystal but also an
internal 32.768 kHz RC oscillator for faster initialization, which leads to prompt clock generation after
power-up and is used until the external crystal becomes stable. Afterwards, the input source can be
switched to the external crystal via a register setting.
The RTC block has a 36-bit real time counter. Its resolution is equal to one clock period of 32.768
kHz. The count value can be read via the register read command.
7.4.1
Wake-up Controller
The wake-up controller is designed to wake up DA16200 from a Sleep mode by an external signal. It
detects an edge trigger of the wake-up signal and selects either the rising edge or the falling edge.
Also, the wake-up signal must be maintained for at least 200 µs upon occurrence of transition on one
side.
When it comes to the source of wake-up, 11 digital I/Os in addition to the two pins directly connected
to the RTC block can be used. Although up to 11 digital I/Os are available for use, the maximum
number of digital I/Os that are simultaneously available is eight. Table 29 describes the digital I/Os
that are available for simultaneous use.
Table 29: Wake-up Sources
QFN and fcCSP Package
Input Selection = 0
GPIOA4
Input Selection = 1
X
X
X
GPIOA5
GPIOA6
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QFN and fcCSP Package
Input Selection = 0
GPIOA7
Input Selection = 1
X
GPIOA8
X
GPIOA9
GPIOC6
GPIOC7
GPIOC8
GPIOA10
GPIOA11
For more information on the wake-up source selection, see the input selection register:
0x50091008[25:16].
The wake-up controller is in the RTC block. RTC registers can set several parameters and identify
which pin is used to wake up the SoC by checking the status register after wake-up.
DA16200 has another wake-up function using analog sources, which is described in Section 9.8.4.
Using the Aux-ADC, DA16200 detects whether it exceeds the predefined threshold value. If it detects
the wanted condition, it will wake up from a Sleep mode. Four ports (GPIOA[3:0]) are used for this
function.
7.4.2
Retention I/O Function
DA16200 I/O has a Retention mode. During this mode, I/O cells retain the previous state values at
the core side inputs. When it is required to maintain the value of a specific GPIO in Sleep mode, this
function will be used. For example, to maintain HIGH value on GPIOA4 in Sleep mode, it is required
to set the value of GPIOA4 to HIGH and set the register bit of RTC block (0x5009_1018:BIT[27:24])
to enable retention to the proper value described in Table 30 before going to the Sleep mode. For
GPIOA4, BIT[25] should be set to HIGH, then GPIOA4 can keep the value HIGH during the Sleep
mode.
The retention enable register is comprised of three bits in total, and the I/O power domains covered
by each of the bits are described in Table 30.
Table 30: I/O Power Domain
[25] DIO1
[26] DIO2
GPIOC[8:6]
[27] FDIO
F_CLK
GPIOA[11:4]
TCLK/TMS
F_CSN
UART0_RXD/UART0_TXD
F_IO0 to F_IO3
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7.5 Pulse Counter
7.5.1
Introduction
The pulse counter is a module that counts the number of rising or falling edges of input signals. And
this counter module can run even in Sleep mode. It includes one 32-bit up-counter. The input
channel can be set with a register setting among the 11 digital I/Os. It also has a glitch filter that is
designed to remove the unwanted trigger of an input signal.
7.5.2
Functional Description
Pulse
Count
CLK_32kHz
PCLK
Int
Counter
Int
Pulse
Edge
Ext.
Pad
Mux.
Glitch
Filter
Edge
Select
ㅣ
ㅣ
Gli_En
Gli_Thresh
Count_En
Count_Rst
Int_Clr
Int_Thresh
Edge_Sel
Mux_SEL
Figure 16: Pulse Counter Block Diagram
7.5.2.1
Input
Available input channels are described in Table 29. It uses the same input sources with the wake-up
controller. By register setting, input channels can be selected among 11 digital I/Os.
7.5.2.2
Clock
The operation clock of the pulse counter is 32 kHz.
7.5.2.3
Counter
As described in Figure 16, the pulse counter is activated by several counter control signals. With a
register setting, input signals can be selected on either the rising edges or falling edges. To enable
the glitch filter module, the Gli_En and Gli_Thresh register values need to be set. The pulses whose
cycles are shorter than the Gli_Thresh value are removed. The counter is a 32-bit up-counter and the
counter value can be reset to zero by Count_Rst.
7.5.2.4
Interrupts
An interrupt occurs when the counter values reaches the Interrupt Threshold value (Int_Thresh). In
Sleep mode, this interrupt can be used as a wake-up source.
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7.6 HW Accelerators
7.6.1
Zeroing of SRAM
DA16200 provides a function to quickly set a constant value for the set SRAM area. This function is
mainly used to initialize the set SRAM area to zero and can be used even when SRAM is used.
For example, assuming that the entire 512 KB SRAM is being initialized, the processing time is 8192
cycles based on the CPU clock, that is, the maximum processing time is 8192 cycles irrespective of
the SRAM size to be initialized.
For more information to use this function, see Ref. [2].
7.6.2
CRC Calculation
The CRC algorithm detects the corruption of data during transmission and detects a higher
percentage of errors than a simple checksum. The CRC calculation consists of an iterative algorithm
involving XOR and shifts operations that is executed much faster in hardware than in software. The
CRC calculator is mainly used to check the flash image and the features of CRC calculator in
DA16200 are summarized below:
■
■
■
Operation clock frequency is up to 160 MHz, the same as CPU clock
Supports 8-bit, 16-bit, and 32-bit data paths
Performs CRC operation simultaneously in real time during data transfer on the selected AHB
bus
■
Operation type of CRC calculation
□
CRC-32: generator polynomial is G(x) = x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 +
x^10 +x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
□
□
CRC-16 CCITT: generator polynomial is G(x) = x^16 + x^12 + x^5 +1
CRC-16 IBM: generator polynomial is G(x) = x^16 + x^15 + x^2 +1
For more information to use this function, see Ref. [2].
7.6.3
Pseudo Random Number Generator (PRNG)
DA16200 provides a function, PRNG, to generate a pseudo random number. The features of PRNG
in DA16200 are summarized as follows:
■
■
Operation clock frequency is up to 160 MHz, the same as CPU clock
Supports partial parallel processing of 8-bit, 16-bit, and 32-bit unit
Generator polynomial is G(x) = x^31 + x^28 + 1 (Ref. [3])
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7.7 DMA Operation
7.7.1
DMA1
DA16200 includes a DMA controller of its own with a single AHB master. The DMA1 has sixteen
channels for fast data transfers from/to I2S, I2C, UARTs, and ADC to/from any on-chip RAM. The
DMA requests of each module are directly connected to the dedicated DMA channels. Each DMA
channel has a priority level, a smaller channel number standing for a higher priority.
Figure 17: DMA1 Controller Block Diagram
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Table 31: DMA1 Served Peripherals
DMA Channel
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10
Channel 11
Channel 12
Channel 13
Channel 14
Channel 15
Module Name
Direction
T/RX
RX
Transfer Size
Word
Mem-to-mem
I2S
Word
I2S
TX
Word
I2C
RX
Byte
I2C
TX
Byte
UART0
RX
Byte
UART0
TX
Byte
UART1
RX
Byte
UART1
TX
Byte
ADCFIFO[0]
ADCFIFO[1]
ADCFIFO[2]
ADCFIFO[3]
UART2
READ
READ
READ
READ
RX
Halfword
Halfword
Halfword
Halfword
Byte
UART2
TX
Byte
Mem-to-mem
T/RX
Word
DA16200’s DMA1 controller supports the Linked-List Item (LLI) function that can sequentially operate
multiple DMA tasks. It is possible to reduce the SW burden and process delay with this function.
Figure 18 shows the DMA1 state machine.
Request
Finish IDLE0 Start
W_FIRST9
INIT10
R_FIRST1
R_FIRST_LOAD11
Arbitration
necessary
R_COMMAND2
R_SRC_ADDR3
R_DST_ADDR4
Start next DMA task
C_NEXT13
Next descriptor
doesn't exist
Next descriptor
exist
R_NEXT_LOAD12
R_NEXT8
R_DATA5
W_DATA6
LLI
No arbitration
necessary, and DMA
task not finished
W_COMMNAD7
Arbitration necessary, or finish current DMA task
Current DMA task
not finished
(arbitration necessary)
Figure 18: DMA1 State Machine
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●
●
●
●
●
●
●
IDLE: waits for the DMA request. When the DMA request appears, the state moves to R_FIRST
R_FIRST: reads the address of the first DMA descriptor (head node of the linked list)
R_COMMAND: reads the Command Field of the DMA descriptor
R_SRC_ADDR: reads the Src_start_addr Field of the DMA descriptor
R_DST_ADDR: reads the Dst_start_addr Field of the DMA descriptor
R_DATA: reads the data from the source address
W_DATA: writes the data read in the R_DATA state to the destination address. By the
information written in the DMA descriptor, if data read/write is required, the state moves to
R_DATA. If the DMA task is required to be suspended or stopped, the state moves to
W_COMMAND
●
●
R_NEXT: reads the next_descriptor field to check whether the next DMA task exists or not,
before stopping the current DMA task
W_FIRST: writes the address of the next DMA descriptor read in R_NEXT to the memory region
where the first address of the DMA descriptor is stored. If arbitration is required, the state moves
to IDLE state. If the current DMA channel is required to be operated, the state moves to R_FIRST
state
●
INIT, R_FIRST_LOAD, R_NEXT_LOAD, and C_NEXT: reduce the critical path delay in the DMA
block. These states generate one clock delay
7.7.2
DMA2 (Fast DMA)
DMA2 (Fast DMA) controller consists of a master read port, a master write port, and a slave port for
configuration register setting. Fast DMA performs bulk data transfers, data reading from the source
address range, and data writing to the destination address range. Fast DMA is mainly used for fast
data transfer from memory to memory.
The features of Fast DMA in DA16200 are summarized as follows:
■
■
■
■
■
Transfer size is programmable from 1 byte to 1 Megabytes
Up to four channels can be set at the same time
LLI function of ring type is supported by using configuration registers of four channels
Interrupt enable can be set for each channel
Provides a hold function to pause data transfer for each channel
The basic unit of bus transmission is 32-bit and has a function to automatically correct address align,
even if the source and destination addresses are not in word units.
For example, assuming that the transfer size is 23 bytes, the source base address is 0x001 for read
access, and the destination base address is 0x102 for write access, the number of bytes per
transaction is performed as follows:
●
Source base address [1:0] = 0x1: the master read port of fast DMA performs read access with
the following sequences:
○
1 -> 2 -> 4 -> 4 -> 4 -> 4 -> 4 bytes
●
Destination base address [1:0] = 0x2: the master write port of fast DMA performs write access
with the following sequences:
○
2 -> 4 -> 4 -> 4 -> 4 -> 4 -> 1 bytes
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Figure 19 shows the DMA2 block diagram.
AHB
BusMatrix
M0
M1
S
DMA2
Configuration
Figure 19: DMA2 Block Diagram
7.8 Simple Memory Protection
DA16200 provides simple protection for internal SRAM, ROM, and Retention Memory.
The memory controllers are AMBA AHB slaves and simple protection operates between the main
AHB bus and the AHB slave port of the memory controllers.
The features of memory protection in DA16200 are summarized as follows:
■
Memory protection provides the function to set the security area of each memory that should be
protected
■
The setting unit to set the security area for each memory is different:
□
□
□
SRAM: 1 kB/unit
MROM: 16 bytes/unit
Retention Memory: 4 bytes/unit
■
■
■
■
Provides the access protection for the security zone for each AHB master
Provides the write protection function for each AHB master
Provides the read protection function for each AHB master
Latency is 0 cycle
The index numbers to distinguish AHB masters are:
●
●
●
●
●
●
●
●
0x0: Cortex M4 – DCode bus
0x1: Cortex M4 – ICode bus
0x2: Cortex M4 – System bus
0x3: MAC DMA
0x4: DMA1
0x5: SD/eMMC (SD Host)
0x6: Serial Slave Interface (SPI, I2C, SDIO)
0x7: DMA2_M0 (read port)
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●
●
●
●
●
0x8: DMA2_M1 (write port)
0x9: DMA of Crypto Engine
0xA: QSPI master – flash controller with XIP
0xB: Hardware Security Unit for Temporal Key Integrity Protocol (HSU for TKIP)
0xC: SPI master for another external SPI slaves
For more information to use this function, see Ref. [2].
7.9 Bus Protection of Serial Slave Interfaces
DA16200 supports a variety of serial slave interfaces, including SPI, I2C, and SDIO slaves.
When DA16200 interfaces with an external host, it is necessary to provide the access to the
authorized area. Therefore, DA16200 provides bus protection for serial slave interfaces.
The features of bus protection in DA16200 are summarized as follows:
■
■
Up to two accessible areas can be set and the setting unit is 4-byte
The bus protection provides the write/read protection function outside the set area
For more information to use this function, see Ref. [2].
7.10 Watchdog Timer
The watchdog timer in DA16200 is based on a 32-bit down-counter that is initialized from the reload
register, WDOGLOAD. The watchdog timer generates a regular interrupt, WDOGINT, depending on
the programmed value. The counter decrements by one on each positive clock edge of WDOGCLK
when the clock enable, WDOGCLKEN, is HIGH.
The watchdog monitors the interrupt and asserts a reset request signal, WDOGRES, when the
counter reaches 0, and the counter is stopped. On the next enabled WDOGCLK clock edge, the
counter is reloaded from the WDOGLOAD register and the countdown sequence continues. If the
interrupt is not cleared by the time the counter reaches 0 for a second time, the watchdog timer
reasserts the reset signal.
The watchdog timer applies a reset to the system in the event of a software failure, providing a way
to recover from software crashes. The watchdog unit can be enabled or disabled as required.
Figure 20 shows the watchdog timer block diagram.
Figure 20: Watchdog Timer Block Diagram
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Figure 21 shows the flow diagram for the watchdog operation.
Counter reloaded
and count down
Count down
Without
without reprogram
reprogram
Watchdog is
programmed
Counter
reaches zero
Counter
reaches zero
If the INTEN bit in the
If the RESET bit in the
WDOGCONTROL register WDOGCONTROL register
is set to 1, WDOGINT is
asserted
is set to 1, WDOGERS is
asserted
Figure 21: Watchdog Operation Flow Diagram
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7.11 Clock Generator
The generation of the system's clocks is described in detail in Figure 22.
PHY Clock
Generator
Divide by
PLL_CLK_DIV_0_CPU
HCLK_FR
PLL480M
XTAL40M
Free running
modules
CK
EN
CPU Core (CM4F)
BusMatrix
CG
CG
CK
EN
CK
EN
Internal SRAM
Mask ROM
CG
CG
CG
CK
EN
CK
EN
PHY Bus
Divide by
CLK_DIV_EMMC
SD/eMMC
Divide by
PLL_CLK_DIV_1_XFC
HCLK_XFC
CK
EN
QSPI Flash
Controller
CG
CG
2nd SPI Host
Controller
CK
EN
Divide by
PLL_CLK_DIV_2_UART
CLK_UART
UART_0
UART_1
UART_2
Divide by
PLL_CLK_DIV_3_OTP
CLK_OTP
OTP
Divide by 2
CLK_AUXA
Divide by
Divide by
CLK_DIV_AUXA
PLL_CLK_DIV_6_AUXA
Aux. ADC
Divide by
PLL_CLK_DIV_7_C312
HCLK_CC312
CK
EN
CG
CC312 (Security IP)
Divide by
PLL_CLK_DIV_5_I2S
CLK_I2S
Divide by
CLK_DIV_I2S
I2S
I/O PAD
Figure 22: Clock Tree Diagram
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8
Crypto Engine
HW crypto engine can be used for accelerating many crypto algorithms, such as hashing, secret key
generation, and others.
Table 32 shows the supported HW acceleration crypto algorithms in DA16200. This table is cited
from Ref. [4]. How to use these crypto functions is explained in Ref. [2].
Table 32: HW Acceleration Crypto Algorithms in DA16200
Algorithm
Mode
Key Sizes
ECB, CBC, CTR, OFB,
CMAC, CBC-MAC,
AESCCM, AES-CCM*, AES-
GCM
AES
128 bits, 192 bits, and 256 bits.
AES key wrapping
N/A
N/A
All
Chacha and Chacha-Poly1305
Diffie-hellman
N/A
●
●
ANSI X9.42-2003: Public Key
Cryptography for the Financial
Services Industry: Agreement of
Symmetric Keys Using Discrete
Logarithm Cryptography
N/A
1024 bits, 2048 bits, and 3072 bits.
Public-Key Cryptography Standards
(PKCS) #3: Diffie Hellman Key
Agreement Standard
ECC key generation
ECIES
N/A
N/A
N/A
N/A
NIST curves and 25519 curves.
NIST curves and 25519 curves.
NIST curves and ED25519.
ECDSA
ECDH
NIST curves and 25519 curves.
Hash
SHA1, SHA224 and SHA256. N/A
N/A N/A
HKDF
HMAC
SHA1, SHA224 and SHA256. N/A
KDF
N/A
NIST SP 800-108: Recommendation for
Key Derivation Using Pseudorandom
Functions
CMAC or HMAC.
RSA PKCS#1 operations
●
●
Public-Key Cryptography Standards
(PKCS) #1 v2.1: RSA Cryptography
Specifications
Encryption and signature
schemes.
2048 bits, 3072 bits, and 4096 bits.
Public-Key Cryptography Standards
(PKCS) #1 v1.5: RSA Encryption
RSA key generation
N/A
2048 bits and 3072 bits.
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9
Peripherals
This section describes the peripherals that are supported by the DA16200 device.
9.1 QSPI Master with XIP Feature
QSPI master supports 4-line SPI communication with commercial flash memory devices and uses a
Motorola SPI-compatible interface among SPI communication modes. The highest communication
speed is the same as the AMBA bus clock, and the speed is adjustable in integer multiples. The
designed QSPI supports 4-/2-/1-line types depending on the purpose. These types should be
combined. Especially when the 1-line communication mode is used, it can be used as the SPI
master.
QSPI master is an IP for communication between the flash memory and AMBA AHB bus and is
designed to support XIP. The features of the QSPI master are summarized as follows:
Serial flash interface:
●
SPI compatible serial bus interface
○
Configurable SPI I/O modes:
– Single I/O mode
– Dual I/O mode
– Quad I/O mode
○
○
○
JEDEC Standard: JESD216B
24-bit and 32-bit addressing
Supports to access flash with XIP mode
– Read access without command
– Read access without address and command
Programmable SPI clock phase and polarity
Maximum number of SPI CS is four that can be operated
○
○
●
Compatible with serial NOR flash devices, such as Macronix, Micron, Spansion, ESMT, and ISSI
AMBA slave interface
●
●
●
●
●
●
●
Compliance to the AMBA AHB bus specification, Rev 3.0 [7]
Direct code execution: directly addressable access without additional driver software
Supports single and incrementing burst transfer (SINGLE, INCR, INCR4, INCR8, INCR16)
Supports byte, half-word, and word transaction
AMBA slave interface is optional to access configuration and status registers
Simple timer is used to check the completion time of flash operation
XIP path of QSPI master supports HW remapping function to execute selected boot image for
over-the-air programming (OTA)
AMBA master interface
●
●
Compliance to the AMBA AHB bus specification, Rev 3.0 [7]
Supports DMA operation to access serial flash devices
○
○
Automatic copy of code image from serial flash to system RAM
Automatic programming of code image from system RAM to serial flash
●
●
●
Performs a mem-to-mem copy in units of 32 bits, regardless of the address and length
Supports single and incrementing burst transfer (SINGLE, INCR, INCR4, INCR8, INCR16)
Supports byte, half-word, and word transaction
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Figure 23 shows the QSPI Master Block Diagram.
AHB
BusMatrix
XIP path
Configuration
DMA
I-Cache
Controller
S
M
S0
S1
AHB
Bus
AHB
Bus
QSPI
Master
External
Serial
NOR Flash
AHB
Bus
with XIP feature
M
DMA
AHB
Bus
Figure 23: QSPI Master Block Diagram
Figure 24 shows the timing diagram for the QSPI master.
TCSB.OF
TCLK.ON
TDO.DLY
TDI.SU
F
QSPI_CSB
QSPI_CLK
QSPI_D[3:0]
Figure 24: QSPI Master Timing Diagram (Mode 0)
Table 33 lists the timing parameters for the QSPI master.
Table 33: QSPI Master Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
MHz
%
QSPI_CLK frequency
QSPI_CLK clock duty
FCLK
10
120
50
TCLK
1st CLK active rising transition time
TCLK.ON
0.5 ×TCLK
ns
(Note 1)
QSPI_CSB non-active rising transition time
QSPI_D[3:0] input setup time
TCSB.OFF
TDI.SU
0
6
TCLK
ns
ns
ns
QSPI_D[3:0] output delay time
TDO.DLY
2
Note 1 TCLK = (FCLK× 106)-1 seconds.
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9.2 SPI Master
QSPI can use the SPI master with the use of a single line interface. Table 34 shows the pin definition
of the SPI master interface. SPI signal timing is the same as QSPI.
To use DA16200 as an SPI master, the CSB signal can be used with any of the GPIO pins. CSB
[3:1] can be selected from the GPIO special function by setting the registers in the GPIO.
Table 34: SPI Master Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
fcCSP
GPIOx
GPIOA6
GPIOA7
GPIOA8
GPIOA9
GPIOA10
GPIOA11
O
O
E_SPI_CSB[3:1]
E_SPI_CSB[0]
32
31
30
29
28
27
E3
E1
G3
H2
F2
G1
O
E_SPI_CLK
I/O
I/O
I/O
I/O
E_SPI_MOSI or E_SPI_D[0]
E_SPI_MISO or E_SPI_D[1]
E_SPI_D[2]
E_SPI_D[3]
TCSB.OF
TCLK.ON
TDO.DLY
TDI.SU
F
E_SPI_CSB
E_SPI_CLK
E_SPI_D[3:0]
Figure 25: SPI Master Timing Diagram (Mode 0)
Table 35: SPI Master Timing Parameters
Parameter
Symbol
Min
Typ
Max
Unit
MHz
%
QSPI_CLK frequency
FCLK
5
60
QSPI_CLK clock duty
50
TCLK
1st CLK active rising transition time
TCLK.ON
0.5 × TCLK
ns
(Note 1)
QSPI_CSB non-active rising transition time TCSB.OFF
0
6
TCLK
ns
ns
ns
QSPI_D[3:0] input setup time
QSPI_D[3:0] output delay time
Note 1 TCLK = (FCLK× 106)-1 seconds.
TDI.SU
TDO.DLY
2
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9.3 SPI Slave
The SPI slave interface supports that an external host can control the DA16200. The range of the
SPI clock speed is the same as that of the internal bus clock speed. The SPI slave supports both the
Burst mode and Non-burst mode. In the Burst mode, SPI_CSB remains active from the start to the
end of communication. In the Non-burst mode, SPI_CLK remains active at every eight bits.
Address
Decoder
Command
Decoder
APB bus
Controller
SPI Signals
Data
Decoder
Figure 26: SPI Slave Block Diagram
Communication protocols of the SPI slave interface use either 4-byte or 8-byte control signals.
Between the two available communication protocols, the CPU chooses one before initiating the
control.
Figure 27 and Figure 28 shows the 8-byte and 4-byte control types.
SPI_CSB
SPI_CLK
D [ 31 : 24 ]
C [ 7 : 0 ]
L [ 23 : 16 ]
L [ 15 : 8 ]
L [ 7 : 0 ]
D [ 7 : 0 ]
D [ 15 : 8 ]
D [ 23 : 16 ]
SPI_MOSI
A [ 31 : 24 ]
A [ 23 : 16 ]
A [ 15 : 8 ]
A [ 7 : 0 ]
Figure 27: 8-byte Control Type
SPI_CSB
SPI_CLK
L [ 7 : 0 ]
D [ 23 : 16 ]
D [ 31 : 24 ]
SPI_MOSI
A [ 15 : 8 ]
A [ 7 : 0 ]
C [ 7 : 0 ]
D [ 7 : 0 ]
D [ 15 : 8 ]
Figure 28: 4-byte Control Type
The 8-byte control type uses a 4-byte address, 1-byte control, and 3-byte length. The 4-byte address
displays the address of registers subject to internal access. The 1-byte control is for communication
control and 3-byte length shows the length of data subject to continuous access in bytes. Hence,
when the 8-byte control type is applied, the maximal length of data subject to continuous access is
16 MB.
The 4-byte control type uses a 2-byte address, 1-byte control, and 1-byte length. The 2-byte address
displays the address of registers subject to internal access. The 1-byte control is for communication
control and 1-byte length shows the length of data subject to continuous access in bytes. Since the
32-bit address map is used internally, the 2-byte address is not enough to express everything. Thus,
the upper 2-byte base address is designated, and then the lower 2-byte address is used.
Table 36 and Table 37 shows the meaning of each bit in the 1-byte control in the 8-byte control type
and the 4-byte control type, respectively.
Table 36: Control Field of the 8-byte Control Type
Control Bit
Abr.
Description
7
Auto Inc.
1 = Internal Address auto-increment
0 = Address fixed
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Control Bit
Abr.
Description
6
Read/Write
1 = Read
0 = Write
5:0
Not used. Set all bits to ‘0’
Table 37: Control Field of the 4-byte Control Type
Control Bit
Abr.
Description
7
6
Auto Inc.
1 = Internal address auto-increment
1 = Read
0 = Address fixed
0 = Write
Read/Write
Common
5
1 = Refer base address as common area
1 = Refer to register value
Length field upper
0 = Refer base address
0 = Refer to length field
4
Length section
Length[12:8]
3:0
Table 38 shows the pin definition of the SPI slave interface.
Table 38: SPI Slave Pin Configuration
Pin Number
Pin Name
I/O
Function Name
SPI_CSB
QFN
37
32
36
31
38
29
27
39
30
28
fcCSP
GPIOA2
GPIOA6
GPIOA3
GPIOA7
GPIOA1
GPIOA9
GPIOA11
GPIOA0
GPIOA8
GPIOA10
B2
I
I
E3
D4
I
SPI_CLK
E1
I
C3
I
H2
I
SPI_MOSI
SPI_MISO
G1
A3
I
O
O
O
G3
F2
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Figure 29 shows the timing diagram for the SPI slave.
SPI_CSB
TSCLKOFF
TCSBOFF
TSCLKL
TSCLKH
TSCLKON
SPI_CLK
(CPOL=0)
TSCLKL
TSCLKH
SPI_CLK
(CPOL=1)
TSSU
TMSU
TMHD
SPI_MOSI
SPI_MISO
MSB
LSB
LSB
TTR
Figure 29: SPI Slave Timing Diagram
Table 39 lists the timing parameters for the SPI slave.
Table 39: SPI Slave Timing Parameters
Parameter
Symbol Min
Typ
Max
Unit
MHz
%
SCLK frequency
SCLK clock duty
Non active duration
FSCLK
-
-
50
40
TSCLKOFF 400
-
-
-
-
ns
TSCLKL(CPOL=0)
1st CLK active rising transition time
CSB non active rising transition time
MOSI setup time
TSCLKON
TCSBOFF
TMSU
ns
ns
ns
TSCLKH (CPOL=1)
TSCLKH (CPOL=0)
TSCLKL (CPOL=1)
-
-
-
TSCLK
8
(Note 1)
MOSI hold time
MISO delay time
TMHD
TSSU
8
-
-
-
TSCLK
8
ns
ns
MISO transition time (10 % to 90 %
transition)
TTR
-
4
5
ns
Note 1 TSCLK = 0.5 × (FSCLK x 106)-1 second.
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9.4 SDIO
SDIO is a full/high speed card suitable for memory card and I/O card applications with low power
consumption. The full/high speed card supports SPI, 1-bit SD, and 4-bit SD transfer modes at the full
clock range of 0 to 50 MHz. To be compatible with the serviceable SDIO clock, the internal BUS
clock needs to be set to minimum 50 MHz. The CIS and CSA areas are located inside the internal
memory and the SDIO registers (CCCR and FBR) are programmed by the SD host.
Command
Decoder
Fn0 / Fn1
Decoder
DAT
Decoder
APB bus
Interface
Response
Generator
CRC
Generator
REG.
2 port
DMA
Control
Memory
Controller
Figure 30: SDIO Slave Block Diagram
Table 40 shows the pin definition of the SDIO interface.
The GPIOA4 and GPIOA5 pins are set to SDIO CMD and CLK by default. If SDIO initialization is
done and SDIO communication is enabled, then the SDIO data pin setting is done automatically. In
other words, when the SDIO communication is detected, the pin used as the SDIO data among the
GPIO pins is automatically activated in the SDIO use mode. However, the auto setting function is not
supported for the F_xxx pin used as the flash function.
Table 40: SDIO Slave Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
34
fcCSP
F4
GPIOA4
GPIOA5
GPIOA9
GPIOA8
GPIOA7
GPIOA6
I/O
I
SDIO_CMD
SDIO_CLK
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
33
D2
29
H2
I/O
I/O
I/O
I/O
30
G3
31
E1
32
E3
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Figure 31 shows the timing diagram for the SDIO slave.
TCO.DLY
TDO.DLY
TCI.SU
TDI.SU
SDIO_CLK
SDIO_D[3:0]
SDIO_CMD
Figure 31: SDIO Slave Timing Diagram
Table 41 lists the timing parameters for the SDIO slave.
Table 41: SDIO Slave Timing Parameters
Parameter
Symbol
Min
Typ
-
Max
Unit
MHz
%
SDIO_CLK frequency
FSCLK
-
50
SDIO_CLK clock duty
50
SDIO_CMD input setup time
SDIO_CMD output delay time
SDIO_D[3:0] input setup time
SDIO_D[3:0] output delay time
TCI.SU
3
3
ns
TCO.DLY
TDI.SU
11 (Note 1)
11 (Note 1)
ns
ns
TDO.DLY
ns
Note 1 SDIO signals can set previous output from half cycle.
9.5 I2C Interface
9.5.1
I2C Master
DA16200 includes an I2C master module. Four ranges of clock speed are supported: standard (100
kHz), fast (400 kHz), fast plus (1.0 MHz) and High Speed (3.4 MHz) mode. Table 42 shows the pin
definition of the I2C master interface.
Table 42: I2C Master Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
38
fcCSP
C3
GPIOA1
GPIOA5
GPIOA9
GPIOA0
GPIOA4
GPIOA8
O
33
D2
O
I2C_CLK
29
H2
O
39
A3
I/O
I/O
I/O
34
F4
I2C_SDA
32
G3
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Figure 32 shows the I2C timing diagram. The timing diagram is the same as that of the I2C slave
timing diagram.
TR
...
SDA
TR
TSU;DAT
TVD;ACK
cont.
...
TLOW
SCL
THD;STA
THD;DAT
THIGH
S
TBUF
...
SDA
SCL
cont.
...
THD;STA
TSU;STO
TSU;STA
Sr
P
S
Figure 32: I2C Master Timing Diagram
Table 43 lists the I2C master timing parameters.
Table 43: I2C Master Timing Parameters
Fast Mode
High Speed Mode
Parameter
Symbol
Unit
Min
Max
Min
Max
Operating Bus clock frequency
SCL clock frequency
Fop_clk
FSCLK
30
120
30
120
MHz
kHz
3400
(Note 2)
100
400
100
Clock Duty (Note 1)
Hold time of START
40
0.2
60
-
40
60
-
%
μs
μs
μs
μs
THD;STA
TLOW
0.2
Low period of the SCL clock
High period of the SCL clock
Setup time for START condition
1.27
1.23
1.1
-
0.55
0.45
0.37
-
THIGH
-
-
TSU;STA
-
-
3x Top_clk
(Note 3)
3x Top_clk
(Note 3)
Data hold time
Data setup time
THD;DAT
-
-
μs
μs
TLOW
TLOW
TSU;DAT
-
-
- THD;DAT
- THD;DAT
TR
Rise time of both SDA and SCL
Setup time for STOP condition
Data valid acknowledge time
0.02
0.36
0.3
0.05
0.45
0.05
μs
μs
μs
(Note 4)
TSU;STO
-
-
-
-
3x Top_clk
(Note 3)
3x Top_clk
(Note 3)
TVD;ACK
Buffer free time between
START and STOP condition
TBUF
0.5
-
0.5
-
μs
Note 1 Clock duty ratio = (THIGH /TSCLK) × 100[%], TSCLK = 1/FSCLK.
Note 2 Max. clock = 3.4 MHz (TSCLK = 294 ns) over 40 MHz of the Fop_clk
.
Max. clock = 1.0 MHz (TSCLK = 1000 ns) under 40 MHz of the Fop_clk.
Note 3 Top_clk = (1 / Fop_clk ) x 106 μsec.
Note 4 TR depends on a pull-up resistor value.
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9.5.2
I2C Slave
The I2C slave interface supports that an external host can control the DA16200. The pin mux
condition is defined in Table 44. Four ranges of clock speed are supported: standard (100 kHz), fast
(400 kHz), fast plus (1.0 MHz) and High Speed (3.4 MHz) mode.
Table 44: I2C Slave Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
38
36
33
31
39
37
34
32
fcCSP
C3
GPIOA1
GPIOA3
GPIOA5
GPIOA7
GPIOA0
GPIOA2
GPIOA4
GPIOA6
I
I
D4
I2C_CLK
D2
I
E1
I
A3
I/O
I/O
I/O
I/O
B2
I2C_SDA
F4
E3
Figure 33 shows the I2C slave timing diagram.
TR
...
SDA
TR
TSU;DAT
TVD;ACK
cont.
...
TLOW
SCL
THD;STA
THD;DAT
THIGH
S
TBUF
...
SDA
SCL
cont.
...
THD;STA
TSU;STO
TSU;STA
Sr
P
S
Figure 33: I2C Slave Timing Diagram
Table 45 lists the I2C slave timing parameters.
Table 45: I2C Slave Timing Parameters
Fast Mode
High Speed Mode
Parameter
Symbol
Unit
Min
Max
Min
Max
SCL clock frequency
100
400
100
3400
kHz
FSCLK
(Note 2)
Clock Duty (Note 1)
Hold time of START
40
0.6
1.3
1.2
0.6
60
-
40
60
-
%
μs
μs
μs
μs
THD;STA
TLOW
0.26
0.15
0.14
0.26
Low period of the SCL clock
High period of the SCL clock
Setup time for START condition
-
-
THIGH
-
-
TSU;STA
-
-
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Fast Mode
High Speed Mode
Parameter
Symbol
Unit
Min
Max
Min
Max
Data hold time
THD;DAT
TSU;DAT
TR
0
0.1
0.02
0.6
-
-
0
0.05
-
-
μs
μs
μs
μs
μs
Data setup time
-
0.3
-
-
Rise time of both SDA and SCL
Setup time for STOP condition
Data valid acknowledge time
0.12
TSU;STO
TVD;ACK
0.26
-
-
-
-
Buffer free time between
START and STOP condition
TBUF
1.3
-
0.5
-
μs
Note 1 Clock duty ratio = (THIGH/TSCLK) × 100[%], TSCLK = 1/FSCLK
Note 2 Max. clock = 3.4 MHz (TSCLK = 294 ns) over 40 MHz of the Fop_clk
Max. clock = 1.0 MHz (TSCLK = 1000 ns) under 40 MHz of the Fop_clk.
.
.
9.6 SD/SDeMMC
The SD/eMMC host IP provides the function for DA16200 to access SD or eMMC cards. This
SD/eMMC host IP only supports a 4-bit data bus and the maximum clock rate is 50 MHz. The
maximum data rate is 25 MB/s (200 Mbps) under the 4-bit data bus and 50 MHz clock.
The SD/eMMC pin mux condition is defined in Table 46.
Table 46: SD/eMMC Master Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
34
33
29
30
31
32
28
38
fcCSP
F4
GPIOA4
GPIOA5
GPIOA9
GPIOA8
GPIOA7
GPIOA6
GPIOA10
GPIOA1
I/O
O
SD/eMMC_CMD
SD/eMMC_CLK
SD/eMMC_D0
SD/eMMC_D1
SD/eMMC_D2
SD/eMMC_D3
D2
H2
I/O
I/O
I/O
I/O
I
G3
E1
E3
F2
SD/eMMC_WRP
C3
I
9.6.1
Block Diagram
Figure 34 shows the block diagram of the SD/eMMC host IP and includes the control register, clock
control, command/response pipe, data pipe, and AHB master interface blocks.
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HCLK
AHB
Control
Clock
Slave
Registers
Control
32
HCMD
CMD/RSP
Pipe
HDATA[3:0]
4
AHB
Master
AHB
FIFO
Data
Pipe
32
32
Figure 34: SD/eMMC Block Diagram
Figure 35 shows the timing diagram for the SD/eMMC master.
TCO.DLY
TDO.DLY
TCI.SU
TDI.SU
SD/eMMC_CLK
SD/eMMC_D[3:0]
SD/eMMC_CMD
Figure 35: SD/eMMC Master Timing Diagram
Table 47 lists the timing parameters for the SD/eMMC master.
Table 47: SD/eMMC Master Timing Parameters
Parameter
Symbol
Min
Typ
-
Max
Unit
MHz
%
SD/eMMC_CLK frequency
FSCLK
-
50
SD/eMMC_CLK clock duty
50
SD/eMMC_CMD input setup time
SD/eMMC_CMD output delay time
SD/eMMC_D[3:0] input setup time
SD/eMMC_D[3:0] output delay time
TCI.SU
TCO.DLY
TDI.SU
8
8
ns
3
8
ns
ns
TDO.DLY
ns
9.7 I2S
DA16200 provides an I2S interface. Once an I2S block receives audio data through the DMA, that
audio data is sent to the external port according to the I2S standard. To use the external DAC, output
through the GPIO port is possible when a register setting is made according to the pin configuration
(Table 48).
The I2S also provides a receive function. However, I2S transmission and reception functions cannot
be used at the same time. The transmit and receive functions can be selected by register setting. If
the I2S signal is input from outside after the reception function is set, the audio signal can be
decoded, stored in the FIFO, and read out through the DMA. The decodable reception function
provides 8/16/24/32-bit modes and can receive either mono or stereo.
Using the I2S clock divider register, the internal PLL clock can be variably applied to the I2S clock
source. The available I2S clock source is 24/48 MHz. There is also a way to apply the I2S clock
source directly from outside using the GPIO pin. For accurate I2S audio sampling, the I2S clock
source can be input to external GPIO pins. It needs to select the GPIO pin setting as the I2S clock
input and apply the appropriate clock source. The available I2S clock pins are shown in Table 48.
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Table 48: I2S Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
38
33
29
39
34
30
36
31
37
32
36
28
fcCSP
C3
D2
H2
A3
GPIOA1
GPIOA5
GPIOA9
GPIOA0
GPIOA4
GPIOA8
GPIOA3
GPIOA7
GPIOA2
GPIOA6
GPIOA3
GPIOA10
O
O
O
O
O
O
O
O
I/O
I/O
I
I2S_MCLK
F4
I2S_BCLK
G3
D4
E1
I2S_LRCK
I2S_SDO
B2
E3
D4
F2
I2S_CLK_IN
I
9.7.1
Block Diagram
I2S has the following features:
■
■
■
■
■
Master Clock Mode only
I2S Data pin can work in either Input mode or Output mode
Clock source can be "internal 480 MHz/N" (currently using 24 MHz) or "external clock source"
Max Sampling Rate: 48 KHz
Mono/Stereo Mode
Figure 36: I2S Block Diagram
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9.7.2
I2S Clock Scheme
The I2S uses a 24 MHz clock as default from the RF reference clock (40 MHz), so it can support
46.875 KHz of sampling rate. External clock sources are needed to support the standard sampling
rate. See Table 49.
Figure 37: I2S Clock Scheme
Table 49: I2S Clock Selection Guide
Parameter
Units
KHz
LRCK
BCLK
MCLK
Fs
8
12
16
24
32
44.1
46.875
48
64Fs
512Fs
0.512
4.096
0.768
6.144
1.024
1.536
2.048
2.8224
3
3.072
MHz
8.192 12.288 16.384 22.5792
24
24.576 MHz
1
N
Clk Div2
6
4
3
2
2
1
1
(=1,2,3…)
24
I2S_CLK
24.576 24.576 24.576 24.576 32.768 22.5792
(Internal
PLL)
24.576 MHz
NOTE
To confirm the exact LRCK operation, drive the Clock source at I2S_CLK.
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9.7.3
I2S Transmit and Receive Timing Diagram
I2S output is possible in the following three modes. The main clock (MCLK) always outputs in 512×fs.
●
I2S Mode
Right Channel
LRCK
Left Channel
SCLK
SDATA
-1
+1
-1
+1
MSB
-2
-3
+3
+2
LSB
MSB
-2
-3
-4
+3
+2
LSB
Figure 38: I2S Timing Diagram
●
Left Justified Mode
Left Channel
LRCK
Right Channel
SCLK
SDATA
-1
+1
LSB
-1
+1
LSB
MSB
-2
-3
+3
+2
MSB
-2
-3
-4
+3
+2
Figure 39: Left Justified Mode Timing Diagram
●
Right Justified Mode
Right Channel
Left Channel
LRCK
SCLK
14
15
14
SDATA
15
13
13
2
1
0
2
1
0
Figure 40: Right Justified Mode Timing Diagram
T2
fBCLK
T3
I2S_BCLK
I2S_SDO
T4
(falling edge)
T5
I2S_SDO
(rising edge)
Figure 41: I2S Transmit Timing Diagram
T4
T2
fBCLK
T3
I2S_BCLK
I2S_SDO
T5
Figure 42: I2S Receive Timing Diagram
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Table 50: I2S Transmit Timing Parameters
Description
Timing
fBCLK
T2
Min
Typ
Max
3.072
½ fBCLK
½ fBCLK
-
Unit
MHz
ns
I2S_BCLK frequency
-
-
High period of the BCLK clock
Low period of the BCLK clock
I2S_SDO output hold (falling edge)
I2S_SDO output hold (rising edge)
T3
-
ns
T4
160
160
ns
T5
-
ns
Table 51: I2S Receive Timing Parameters
Description
Timing
fBCLK
T2
Min
-
Typ
Max
3.072
½ fBCLK
½ fBCLK
-
Unit
MHz
ns
I2S_BCLK frequency
High period of the BCLK clock
Low period of the BCLK clock
I2S_SDO input setup time
I2S_SDO input hold time
-
T3
-
ns
T4
15
60
ns
T5
-
ns
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9.8 ADC (Aux 12-bit)
9.8.1
Overview
DA16200 includes a high precision, ultra-low power, and wide dynamic range SAR ADC with a 12-bit
resolution. It has a 4-channel single-end ADC.
Analog input is measured by four pins from GPIOA0 to GPIOA3, and pin selection is changed
through the register setting.
Figure 43 shows the control block diagram.
VI_N[1]
ADC
12b
Max : 1Ms
CH_SEL
Ready
VI_N[2]
VI_N[3]
VI_N[4]
Counter
16-bit
Figure 43: ADC Control Block Diagram
9.8.2
Timing Diagram
The input is digitized at a maximum of 1.0 Msps throughput rate. And the maximum input clock rate
is 15 MHz.
Figure 44 shows the conversion timing, and Table 52 describes the DC specifications.
CLK
15MHz
15*CLK
15*CLK
15*CLK
15*CLK
15*CLK
15*CLK
AUXADC_EN
OSC_EN
N+1
N+4
N+2
N+3
N
SAMPLE
1M
D<11:0>
N
N+1
N+2
N+3
CLKOUT
1M
Figure 44: 12-bit ADC Timing Diagram
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Table 52: DC Specification
Description
Min
4
Typ
Max
12
15
1
Unit
Bits
Resolution
12
Max clock input
Conversion frequency
Accuracy:
MHz
MHz
●
●
SNR
●
●
67.2
61.7
●
●
dB
dB
SNDR
Analog input voltage
0
1.4
V
Reference voltage
0.7
10
V
Input tolerance (approximately)
mV
9.8.3
DMA Transfer
There are four ADC channel settings available. Once the input data of each channel reaches the
FIFO level, it is possible to read the data through the DMA path.
9.8.4
Sensor Wake-up
The DA16200 has an external sensor wake-up function that uses the analog input signal through an
Aux ADC. Even in Sleep modes, it detects the change of an external analog signal, wakes up from
Sleep mode, and converts the DA16200 into a normal operation. This function can be used in up to
four channels. Also, when multiple external sensors are used, analog signals are detected while the
channel are automatically changed. For example, if all four channels are set as input sources which
have their threshold register respectively, the channels are measured sequentially from 0 to 3.
If one of the four values exceeds the allowed range of values set by the threshold register, the
DA16200 awakes from the Sleep mode. The value setting of the input change can be either over
threshold or under threshold.
9.8.5
ADC Ports
Table 53 shows the pin definition of the ADC.
Table 53: ADC Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
fcCSP
GPIOA3
GPIOA2
GPIOA1
GPIOA0
36
D4
B2
C3
A3
A
A
A
A
Analog signal
Analog signal
Analog signal
Analog signal
37
38
39
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9.9 GPIO
All digital pads can be used as GPIO, and each GPIO port is mixed with a multi-functional interface.
The GPIO features of DA16200 are listed below:
■
■
■
■
■
■
Input or output lines in a programmable direction
Word and half word read/write access
Address-masked byte writes to facilitate quick bit set and clear operations
Address-based byte reads to facilitate quick bit test operations
Maskable interrupt generation based on input value change
Possible to be output signal of PWM[3:0], external interrupt, QSPI_CSB[3:1], RF_SW[1:0], and
UART_TXDOE[2:0] on the GPIO pins:
□
It provides special functions for GPIO pin use. PWM [3:0], external interrupt, QSPI_CSB [3:1],
RF_SW [1:0], and UART_TXDOE [2:0] signals can be output by selecting unused pins
among the GPIO pins. It is possible to select the function to be output from the GPIO register
setting and select the remaining GPIO pin without using it to output the specific function to
the desired GPIO pins
9.9.1
Antenna Switching Diversity
DA16200 provides the antenna switching diversity function for performance improvement in a multi-
path environment. A PHY block measures the RSSI of each antenna and selects the antenna with
the largest RSSI. The selected antenna is also used for transmission. To use this function, an
external switching element is required, and switching control is done through the GPIO. Two GPIOs
can be used for switching control, and for this purpose any unused pins among the GPIO pins can be
selected. The control signal can be changed by register setting to suit the external switching device.
Antenna1
RF Switch
DA16200
Antenna2
ANT
GPIO
2
Figure 45: Antenna Switching Internal Block Diagram
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If the Antenna Switching Diversity function is enabled, the function is automatically done by PHY
hardware block. The basic operation scheme is as follows:
●
●
●
The antenna's RSSI decision is made for 11b PPDU, except for 11g/n PPDU
When PHY hardware detects the existence of 11b PPDU, it stores the RSSI
After the switch to another antenna, the RSSI is stored and a decision is made about which
antenna has better RSSI
●
●
This operation is done during 11b PPDU's preamble duration to protect corruption of 11b PPDU
data reception
The decided antenna is not changed until there is a new 11b PPDU
Example case when RSSI of Antenna 2 is higher
11b PPDU
Preamble Header
11g/n PPDU
11b PPDU
Preamble Header
PSDU
PSDU
Antenna
Time
1
2
2
1
2
Figure 46: Antenna Switching Timing Diagram
For reference, this antenna switching diversity is different from MRC (Maximum Ratio Combining).
9.10 UART
DA16200 provides three UARTs, features of which are described below:
■
■
■
■
■
■
■
■
Programmable use of UART (UART1 and UART2)
Compliance to the AMBA AHB bus specification [7] for easy integration into SoC implementation
Supports both byte and word access for reduction of bus burden
Supports both RS-232 and RS-485
Separate 32×8 bit transmit and 32×12 bit receive FIFO memory buffers to reduce CPU interrupts
Programmable FIFO disabling for 1-byte depth
Programmable baud rate generator
Standard asynchronous communication bits (start, stop, and parity), which are added prior to
transmission and removed on reception
■
■
■
■
■
Independent masking of transmit FIFO, receive FIFO, and receive timeout
Supports for DMA
False start bit detection
Programmable flow control (CTS/RTS, UART1)
Fully programmable serial interface characteristics:
□
□
□
□
Data can be of 5, 6, 7, or 8 bits
Even, odd, stick, or no-parity bit generation and detection
1- or 2- stop bit generation
Baud rate generation
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Figure 47: DA16200 UART Block Diagram
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9.10.1 RS-232
As the serial communication between the UART and the selected device is asynchronous, additional
bits (start and stop) are inserted into the data line to indicate the beginning and end. With these bits,
two devices can be synchronized. This structure of serial data accompanied by start and stop bits is
referred to as a character, as shown in Figure 48.
Bit Time
Data
Start
Data bits
5 - 8
Parity
Stop
1- or 2-
One Character
Figure 48: Serial Data Format
An additional parity bit may be added to the serial character. This bit appears between the last data
bit and the stop bit(s) in the character structure. It provides the UART with the ability to do simple
error checking on the received data.
The UART Line Control Register is used to control the serial character characteristics. The individual
bits of the data word are sent after the start bit, starting with the least significant bit (LSB). These are
followed by the optional parity bit, followed by the stop bit(s), which can be 1 or 2.
Serial Data In
Start
Data Bit 0 (LSB)
Data Bit 1
8
16
16
Figure 49: Receiver Serial Data Sampling Points
All the bits in the transmission are transmitted for exactly the same time duration. This is referred to
as a Bit Period or Bit Time. One Bit Time equals 16 baud clocks. To ensure stability on the line, the
receiver samples the serial input data at approximately the mid-point of the Bit Time, once the start
bit has been detected. As the exact number of baud clocks that each bit was transmitted for is
known, calculating the mid-point for sampling is not difficult, that is every 16 baud clocks after the
mid-point sample of the start bit. Figure 49 shows the sampling points of the first couple of bits in a
serial character.
9.10.2 RS-485
DA16200 UART supports RS-485. A UART485EN register (0x054) is required to be assigned to
enable the RS-485. In order to use RS-485, an additional signal (UARTTXDOE) is required to notice
TXD intervals. This signal can be an output by selecting any of the unused GPIO pins.
Figure 50: UARTTXDOE Output Signal for UART RS-485
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9.10.3 Baud Rate
The UART clock frequency (FUARTCLK) is fixed at 80 MHz. The Baud Rate Divisor can be
calculated as (FUARTCLK / (16 x Baud Rate)). The Baud Rate Divisor is comprised of the integer
part (UART_INTBRDIV) and fractional part (UART_FRABRDIV). The maximum baud rate of
DA16200 UART is 2.5 MBaud.
The example below shows how to calculate the divisor value.
If the required baud rate is 921600 with 80 MHz FUARTCLK, the Baud Rate Divisor becomes:
(8 x 107) / (16 x 921600) = 5.425.
This means that the integer value is 5 and the fractional value is 0.425.
Then, the fraction part becomes integer ((0.425 x 64) + 0.5) = 27.
Then, the generated baud rate divider is 5 + 27/64 = 5.422.
Finally, the generated baud rate becomes (8 x 107) / (16 x 5.422) = 922169.
And the error between the required baud rate and the generated baud rate is:
(922169 – 921600) / 921600 x100 = 0.062 %
9.10.4 Hardware Flow Control
The hardware flow control feature is fully selectable, and serial data flow is controlled by using
nUARTRTS output and nUARTCTS input signals. Figure 51 shows how two different UARTs can
communicate using hardware flow control.
Figure 51: UART Hardware Flow Control
When RTS flow control is enabled, nUARTRTS signal is asserted until the receive FIFO is filled up to
programmed level. When CTS flow control is enabled, the transmitter can transmit the data when the
nUARTCTS signal is asserted. CTSEn (CTS enable) and RTSEn (RTS enable) bits are determined
by 14th (RTS) and 15th bit (CTS) of UARTCR register.
Table 54: Control Bits to Enable and Disable Hardware Flow Control
CTSEn
RTSEn
Description
1
1
0
0
1
0
1
0
Both RTS and CTS flow control are enabled
Only CTS flow control is enabled
Only RTS flow control is enabled
Both RTS and CTS flow control are disabled
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9.10.5 Interrupts
The DA16200 UART block provides five interrupt signals by separate interrupt lines. Each interrupt
conditions are Modem Status, Receive FIFO Request, Transmit FIFO Request, Receive Timeout and
Reception Error. These conditions are logically ORed to provide a single combined interrupt,
UARTINTR. Table 55 shows the interrupt signals.
Table 55: UART Interrupt Signals
Signal Name
UARTMSINTR
UARTRXINTR
UARTTXINTR
UARTRTINTR
UARTEINTR
UARTINTR
Description
UART Modem Status Interrupt
UART Receive FIFO Interrupt
UART Transmit FIFO Interrupt
UART Receive Timeout Interrupt
UART Error Interrupt
UART Interrupt. Five Interrupt signals are combined by OR function
9.10.6 DMA Interface
The DA16200 UART block can generate DMA request signals with register settings by using a DMA
interrupt generator module to connect to DA16200 DMA Controller (DMA1). The DMA operation of
the UART is controlled with the DMA Control Register.
The DA16200 UART provides four DMA signals and receives two DMA signals, two signals to
transmit (TXDMASREQ, TXDMABREQ), which are cleared by a TX clear signal (TXDMACLR) and
two signals to receive (RXDMASREQ, RXDMABREQ), which are cleared by a RX clear signal
(RXDMACLR).
When the DMA interface is not used, the TXDMACLR and RXDMACLR lines should be connected to
a logic 0.
Table 56 shows the pin definition of the UART interface.
Table 56: UART Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
12
11
31
33
36
38
32
34
37
39
33
34
27
9
fcCSP
M10
L9
UART0_RXD
UART0_TXD
GPIOA7
GPIOA5
GPIOA3
GPIOA1
GPIOA6
GPIOA4
GPIOA2
GPIOA0
GPIOA5
GPIOA4
GPIOA11
GPIOC7
I
O
I
UART0_RXD
UART0_TXD
E1
D2
I
UART1_RXD
UART1_TXD
D4
I
C3
I
E3
O
O
O
O
I
F4
B2
A3
D2
UART1_CTS
UART1_RTS
F4
O
I
G1
K12
UART2_RXD
I
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Ultra Low Power Wi-Fi SoC
Pin Number
Pin Name
I/O
Function Name
QFN
28
fcCSP
F2
GPIOA10
GPIOC6
O
O
UART2_TXD
10
L11
9.11 PWM
Pulse Width Modulation (PWM) is a modulation technique used to encode a message into a pulse
signal. The blocks are designed to adjust output pulse duration by the CPU bus clock (HCLK).
Figure 52 shows the structure of the PWM block.
Counter
PWM OUT
PWM Block 0
PWM OUT
PWM OUT
PWM OUT
PWM Block 1
HCLK
PWMBlock 2
Register
PWMBlock 3
AHB
Bus
Matrix
Counter (Period)
AHB Bus
Counter (High Duty)
Register
Figure 52: PWM Block Diagram
Table 57 shows the pin definition of the PWM interface. GPIOx means that PWM signals can go out
through any GPIO pins via a register setting.
Table 57: PWM Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
fcCSP
GPIOx
PWM[3:0] output
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9.11.1 Timing Diagram
Table 58 shows the relation between the internal bus clock and PWM output wave patterns.
Figure 53 shows the conversion timing diagram. a and b can be adjusted through the register setting,
and PWM wave patterns vary depending on the ratio. a controls the high width of pulses (nCycle
High), while b controls the general cycle (nCycle Period).
BUS CLK
a
PWM
b
Figure 53: PWM Timing Diagram
Table 58: PWM Timing Diagram Description
Time
Description
a
b
Bus Clock Period × (nCycle High + 1)
Bus Clock Period × (nCycle Period + 1)
9.12 Debug Interface
DA16200 supports both IEEE Standard 1149.1 JTAG (5-wire) and the low-pin-count Arm SWD (2-
wire, TCLK/TMS) debug interfaces. The SWD protocol can handle the same debug features as the
JTAG.
The JTAG port is an IEEE standard that defines a test access port (TAP) and boundary scan
architecture for digital integrated circuits and provides a standardized serial interface to control the
associated test logic. For detailed information on the operation of the JTAG port and TAP controller,
see Ref. [5].
Figure 54 shows the JTAG timing diagram.
Figure 54: JTAG Timing Diagram
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Table 59 shows the JTAG timing parameters.
Table 59: JTAG Timing Parameters
Parameter Number
Parameter
fTCK
Parameter Name
Clock Frequency
Clock Period
Min
Max
15
Unit
MHz
ns
J1
J2
tTCK
1/fTCK
tTCK/2
tTCK/2
J3
tCL
Clock Low Period
Clock High Period
TMS Setup Time
TMS Hold Time
TDI Setup Time
TDI Hold Time
ns
J4
tCH
ns
J7
tTMS_SU
tTMS_HO
tTDI_SU
tTDI_HO
tTDO_HO
1
16
1
J8
J9
J10
J11
16
TDO Hold Time
15
Table 60 shows the pin definition of the JTAG interface.
Table 60: JTAG Pin Configuration
Pin Number
Pin Name
I/O
Function Name
QFN
fcCSP
TMS
6
J11
I/O
Data
TCLK
7
J9
I
I
Clock
GPIOC8
GPIOC7
GPIOC6
8
K10
K12
L11
TDI: Data Input
TDO: Data Output
nTRST: Reset
9
O
I
10
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9.13 Bluetooth Coexistence
DA16200 provides the Bluetooth coexistence function to be properly aligned with external devices
activated at 2.4 GHz.
9.13.1 Interface Configuration
The following three pins can be set in pin multiplexing:
●
●
●
BT_sig0 (oWlanAct)
It indicates that Output, WLAN is currently active
BT_sig1 (iBtAct)
It indicates that Input, BT/BLE is currently active
BT_sig2 (iBTPri)
It indicates that Input (Optional), BT/BLE has a higher priority
○
○
○
A variety of configurable settings are available, including active high/low, manual force mode, use
status of the optional iBTPri function, and whether or not to switch oWlanAct to active in the event of
TX/RX/TRX.
oWlanAct
iBtAct
iBtPri
DA16200
BT/BLE
Figure 55: Bluetooth Coexistence Interface
9.13.2 Operation Scenario
The Bluetooth coexistence can be turned on/off by the configurable register, and the activation
scenarios based on the status of each pin are described below:
●
●
●
BT_sig0 (oWlanAct)
When asserted, external BT/BLE is expected to stop occupying RF
BT_sig1 (iBtAct)
When asserted, DA16200 stops occupying RF
BT_sig2 (iBTPri)
○
○
○
○
It is optional and thus may not be used
If it is used and DA16200’s iBtAct = Active while iBTPri = Non-Active, DA16200 may ignore
iBtAct
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10 Applications Schematic
10.1 Typical Application: QFN, 3.3 V Flash
Figure 56 shows the schematics for an application that uses the DA16200 in 3.3 V Flash mode.
Note: Remove R3 and C12 when MCU controls RTC_PWR_KEYꢀ
C13
C12
C11
RF1
R4
C17
L2
C10
L3
C15
C19
C18
VDD_DIO1
VSS
(1.8V ~ 3.3V)
GPIOA3
1
2
36
35
34
33
32
31
30
29
28
27
26
25
VDD_DIO1
VDD_ANA
R1
C1
RBIAS
RF_XI
GPIOA4
GPIOA5
GPIOA6
GPIOA7
GPIOA8
GPIOA9
GPIOA10
GPIOA11
DCDC_FB
DCDC_LX
3
DA16200
QFN
C9
4
C2
C3
RF_XO
5
TMS
TCLK
6
7
GPIOC8
8
GPIOC7
9
GPIOC6
10
11
12
UART_TXD
UART_RXD
L1
C8
VBAT (3.3V)
VDD_DIO2
(1.8V ~ 3.3V)
C7
U1
C4
R5
C5
R2
C6
VDD_FDIO
( Connect to
External Flash)
RTC_GPO (High/Low)
Figure 56: Typical Application – QFN, 3.3 V Flash
The power supply of the External Flash memory is the same as VDD_FDIO.
VDD_DIO1/2 can be connected to the same power source as the external component that is
connected to the DA16200.
Remove R3 and C12 when MCU control ‘RTC_PWR_KEY’.
Table 61 lists the components for an application that uses the DA16200 QFN in 3.3 V Flash mode.
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Table 61: Components for DA16200 QFN, 3.3 V Flash Mode
Quantity Part Reference
Value
Description
1
R1
30 kΩ (1 %)
These values may be changed by crystal component
characteristics and board condition.
2
C2, C3
1.2pF
Part: FCX-07L
5
1
1
1
1
C1, C4, C5, C7, C9
1µF
C6
R2
L1
470nF
10 kΩ
4.7µH
10µF
LQM21PN4R7MGH (Murata)
C8
These values may be changed by crystal component
characteristics and board condition.
2
C10, C11
15pF
Part: TFX-03
Remove when MCU control ‘RTC_PWR_KEY’.
This value should be chosen by customer application
to achieve the enough delay time depending on the
power-on time of VBAT.
1
R3
470 kΩ
For detail information, see Section 6.1
Remove when MCU control ‘RTC_PWR_KEY’.
This value should be chosen by customer application
to achieve the enough delay time depending on the
power-on time of VBAT. Not to exceed 1uF.
1
C12
1uF
For detail information, see Section 6.1
2
1
1
1
1
2
1
R4, R5
C13
4.7 kΩ
4.7µF
DNI
C15
Optional
L3
2.2 nH
0.5pF
1pF
C17
Optional
Optional
Optional
C18, C19
L2
1.8nH
Optional, load switch for disconnecting VBAT for
VDD_FDIO
1
U1
(Use any 5 % tolerance)
Table 62: IO Power Domain
IO Power Domain
VDD_DIO1
VDD_DIO2
VDD_FDIO
GPIOA[11:0]
GPIOC[8:6], TMS, TCLK, UART_TXD, UART_RXD
F_IO[3:0], F_CSN, F_CLK
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10.2 Typical Application: QFN, 1.8 V Flash
Figure 57 shows the schematics for an application that uses the DA16200 QFN in 1.8 V Flash mode.
Note: Remove R3 and C12 when MCU controls RTC_PWR_KEYꢀ
C13
C12
RF1
R4
C17
L2
C11
C10
L3
C15
C19
C18
VDD_DIO1
VSS
(1.8V ~ 3.3V)
GPIOA3
1
2
36
35
34
33
32
31
30
29
28
27
26
25
VDD_DIO1
VDD_ANA
R1
C1
RBIAS
RF_XI
GPIOA4
GPIOA5
GPIOA6
GPIOA7
GPIOA8
GPIOA9
GPIOA10
GPIOA11
DCDC_FB
DCDC_LX
3
DA16200
QFN
C9
4
C2
C3
RF_XO
5
TMS
TCLK
6
7
GPIOC8
8
GPIOC7
9
GPIOC6
10
11
12
UART_TXD
UART_RXD
L1
C8
VBAT (3.3V)
VDD_DIO2
(1.8V ~ 3.3V)
C7
C4
R5
C5
R2
C6
VDD_FDIO
( Connect to
External Flash)
Figure 57: Typical Application – QFN, 1.8 V Flash
The power supply of the External Flash memory is the same as VDD_FDIO.
VDD_DIO1/2 can be connected to the same power source as the external component that is
connected to the DA16200.
Remove R3 and C12 when MCU control ‘RTC_PWR_KEY’.
Table 63 lists the components for an application that uses the DA16200 QFN in 1.8 V Flash mode.
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Ultra Low Power Wi-Fi SoC
Table 63: Component for DA16200 QFN, 1.8 V Flash Mode
Quantity Part Reference
Value
Description
1
R1
30 kΩ (1 %)
These values may be changed by crystal component
characteristics and board condition.
2
C2, C3
1.2 pF
Part: FCX-07L
5
1
1
1
1
C1, C4, C5, C7, C9
1 µF
C6
R2
L1
470 nF
10 kΩ
4.7 µH
10 µF
LQM21PN4R7MGH (Murata)
C8
These values may be changed by crystal component
characteristics and board condition.
2
C10, C11
15 pF
Part: TFX-03
Remove when MCU control ‘RTC_PWR_KEY’.
This value should be chosen by customer application
to achieve the enough delay time depending on the
power-on time of VBAT.
1
R3
470 kΩ
For detail information, see Section 6.1
Remove when MCU control ‘RTC_PWR_KEY’.
This value should be chosen by customer application
to achieve the enough delay time depending on the
power-on time of VBAT. Not to exceed 1uF.
1
C12
1uF
For detail information, see Section 6.1
2
1
1
1
1
2
1
R4, R5
C13
4.7 kΩ
4.7 µF
DNI
C15
Optional
L3
2.2 nH
0.5 pF
1 pF
C17
Optional
Optional
Optional
C18, C19
L2
1.8 nH
(Use any 5 % tolerance)
Table 64: IO Power Domain
IO Power Domain
VDD_DIO1
VDD_DIO2
VDD_FDIO
GPIOA[11:0]
GPIOC[8:6], TMS, TCLK, UART_TXD, UART_RXD
F_IO[3:0], F_CSN, F_CLK
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10.3 Typical Application: fcCSP,1.8 V Flash Normal Power Mode
Figure 58 shows the schematics for an application that uses the DA16200 fcCSP in 1.8 V Flash
mode.
RF1
Note: Remove R3 and C12 when MCU controls RTC_PWR_KEYꢀ
C17
L2
L3
C11
C10
C15
C18 C19
R4
C13
A7
A5
RTC_PWR_
KEY
A1
A3
A9
A11
VDD_DA
/PA
GND
GPIOA0
GND
ANT
C9
VDD_DIO1
( 1.8V ~ 3.3V)
B8
B2
B4
B6
B10
B12
VDD_DA
/PA
GPIOA2
RTC_XI
GND
GND
GND
C1
VDD_DI
O1
C3
C5
C7
C9
C11
GPIOA1
RTC_XO
GND
GND
GND
GPIOA3
GPIOA5
GPIOA6
C1
R1
D12
VDD_AN
A
D6
RTC_WAKE
_UP
D2
D4
D8
D10
GPIOA5
GPIOA3
GND
GND
GPIOA7
E1
E3
E5
E7
E9
E11
GPIOA7
GPIOA6
GND
RTC_GPO
GND
RBIAS
GPIOA4
GPIOA10
GPIOA8
F2
F4
F6
F8
F10
F12
GPIOA10
GPIOA4
GND
GND
GND
GND
C2
C3
GPIOA11
G1
G3
G5
G7
G9
G11
GPIOA11
GPIOA8
GND
GND
GND
RF_XI
H6
RTC_WAKE
_UP2
GPIOA9
H2
H8
H10
H12
H4
GPIOA9
GND
GND
RF_XO
GND
RTC_WAKE_UP2
TMS
TCLK
J3
J5
J7
J9
J11
J1
R5
DCDC_FB
GND
F_CSN
F_IO2
TCLK
TMS
GPIOC7
K12
K2
K6
K10
K4
K8
GPIOC7
GND
F_IO3
GPIOC8
F_CLK
F_IO0
GPIOC8
GPIOC6
L1
C8
L3
VDD_DI
G
L9
UART_T
XD
L1
L5
L7
L11
DCDC_LX
GND
F_IO1
GPIOC6
M10
M4
VDD_FDI
O
M6
M12
M2
M8
UART_R
XD
GND
GND
VBAT
DIO2
C6
C5
R2
C4
C7
VBAT
Figure 58: Typical Application – fcCSP, 1.8 V Flash, Normal Power Mode
The power supply of the External Flash memory is the same as VDD_FDIO.
VDD_DIO1/2 can be connected to the same power source as the external component that is
connected to the DA16200.
Remove R3 and C12 when MCU control ‘RTC_PWR_KEY’.
Table 65 lists the components for an application that uses the DA16200 fcCSP in 1.8 V Flash mode.
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Ultra Low Power Wi-Fi SoC
Table 65: Component for DA16200 fcCSP, 1.8 V Flash, Normal Power Mode
Quantity Part Reference
Value
Description
1
2
R1
30 kΩ (1 %)
1.2 pF
C2, C3
These values may be changed by crystal component
characteristics and board condition.
Part: FCX-07L
1
4
1
1
1
1
2
C6
470 nF
1 µF
C1, C4, C5, C9
C7
2.2 µF
10 kΩ
4.7 µH
10 µF
15 pF
R2
L1
LQM21PN4R7MGH (Murata)
C8
C10, C11
These values may be changed by crystal component
characteristics and board condition.
Part: TFX-03
1
1
R3
Remove when MCU control ‘RTC_PWR_KEY’.
This value should be chosen by customer application
to achieve the enough delay time depending on the
power-on time of VBAT.
470 kΩ
For detail information, see Section 6.1
C12
Remove when MCU control ‘RTC_PWR_KEY’.
This value should be chosen by customer application
to achieve the enough delay time depending on the
power-on time of VBAT. Not to exceed 1uF.
1uF
For detail information, see Section 6.1
1
1
1
1
1
2
1
R4, R5
C13
4.7 kΩ
4.7 µF
0.5 pF
2.7 nH
0.5 pF
1 pF
C15
Normal power mode
Normal power mode
Optional
L3
C17
C18, C19
L2
Optional
1.8 nH
Optional
(Use any 5 % tolerance)
Table 66: IO Power Domain
IO Power Domain
VDD_DIO1
VDD_DIO2
GPIOA[11:0]
GPIOC[8:6], TMS, TCLK, UART_TXD, UART_RXD
F_IO[3:0], F_CSN, F_CLK
VDD_FDIO (Note 1)
Note 1 VDD_FDIO is internally connected to FDIO_LDO_OUT.
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10.4 Typical Application: fcCSP,1.8 V Flash Low Power Mode
Figure 59 shows the schematics for an application that uses the DA16200 fcCSP in 1.8 V Flash
mode.
RF1
Note: Remove R3 and C12 when MCU controls RTC_PWR_KEYꢀ
C17
L2
L3
C11
C10
C15
C18 C19
R4
C13
A7
A5
RTC_PWR_
KEY
A1
A3
A9
A11
VDD_DA
/PA
GND
GPIOA0
GND
ANT
C9
B8
VDD_DIO1
( 1.8V ~ 3.3V)
B2
B4
B6
B10
B12
VDD_DA
/PA
GPIOA2
RTC_XI
GND
GND
GND
C1
C3
C5
C7
C9
C11
VDD_DI
O1
GPIOA1
RTC_XO
GND
GND
GND
GPIOA3
GPIOA5
GPIOA6
C1
R1
D12
VDD_AN
A
D6
RTC_WAKE
_UP
D2
D4
D8
D10
GPIOA5
GPIOA3
GND
GND
GPIOA7
E1
E3
E5
E7
E9
E11
GPIOA7
GPIOA6
GND
RTC_GPO
GND
RBIAS
GPIOA4
GPIOA10
GPIOA8
F2
F4
F6
F8
F10
F12
GPIOA10
GPIOA4
GND
GND
GND
GND
C2
C3
GPIOA11
G1
G3
G5
G7
G9
G11
GPIOA11
GPIOA8
GND
GND
GND
RF_XI
H6
RTC_WAKE
_UP2
GPIOA9
H2
H8
H10
H12
H4
GPIOA9
GND
GND
RF_XO
GND
RTC_WAKE_UP2
TMS
TCLK
J3
J5
J7
J9
J11
J1
R5
DCDC_FB
GND
F_CSN
F_IO2
TCLK
TMS
GPIOC7
K12
K2
K6
K10
K4
K8
GPIOC7
GND
F_IO3
GPIOC8
F_CLK
F_IO0
GPIOC8
GPIOC6
L1
C8
L3
L9
L1
L5
L7
L11
VDD_DI
G
UART_T
XD
DCDC_LX
GND
F_IO1
GPIOC6
M10
UART_R
XD
M4
M6
M12
M2
M8
VDD_FDI
O
GND
GND
VBAT
DIO2
C6
C5
R2
C4
C7
VBAT
Figure 59: Typical Application – fcCSP, 1.8 V Flash, Low Power Mode
The power supply of the External Flash memory is the same as VDD_FDIO.
VDD_DIO1/2 can be connected to the same power source as the external component that is
connected to the DA16200.
Remove R3 and C12 when MCU control ‘RTC_PWR_KEY’.
Table 67 lists the components for an application that uses the DA16200 fcCSP in 1.8 V Flash mode.
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Table 67: Component for DA16200 fcCSP, 1.8 V Flash, Low Power Mode
Quantity Part Reference
Value
Description
1
2
R1
30 kΩ (1 %)
1.2 pF
C2, C3
These values may be changed by crystal component
characteristics and board condition.
Part: FCX-07L
1
4
1
1
1
1
2
C6
470 nF
1 µF
C1, C4, C5, C9
C7
2.2 µF
10 kΩ
4.7 µH
10 µF
15 pF
R2
L1
LQM21PN4R7MGH (Murata)
C8
C10, C11
These values may be changed by crystal component
characteristics and board condition.
Part: TFX-03
1
1
R3
Remove when MCU control ‘RTC_PWR_KEY’.
This value should be chosen by customer application
to achieve the enough delay time depending on the
power-on time of VBAT.
470 kΩ
For detail information, see Section 6.1
C12
Remove when MCU control ‘RTC_PWR_KEY’.
This value should be chosen by customer application
to achieve the enough delay time depending on the
power-on time of VBAT. Not to exceed 1uF.
1uF
For detail information, see Section 6.1
1
1
1
1
1
2
1
R4, R5
C13
4.7 kΩ
4.7 µF
DNI
C15
Low power mode
Low power mode
Optional
L3
2.2 nH
0.5 pF
1 pF
C17
C18, C19
L2
Optional
1.8 nH
Optional
(Use any 5 % tolerance)
Table 68: IO Power Domain
IO Power Domain
VDD_DIO1
VDD_DIO2
GPIOA[11:0]
GPIOC[8:6], TMS, TCLK, UART_TXD, UART_RXD
F_IO[3:0], F_CSN, F_CLK
VDD_FDIO (Note 1)
Note 1 VDD_FDIO is internally connected to FDIO_LDO_OUT.
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11 Package Information
11.1 Moisture Sensitivity Level (MSL)
The MSL is an indicator for the maximum allowable time period (floor life time) in which a moisture
sensitive plastic device, once removed from the dry bag, can be exposed to an environment with a
maximum temperature of 30 °C and a maximum relative humidity of 60 % RH before the solder
reflow process.
QFN and fcCSP packages are qualified for MSL 3.
MSL Level
MSL 4
Floor Life Time
72 hours
MSL 3
168 hours
MSL 2A
MSL 2
4 weeks
1 year
MSL 1
Unlimited at 30 °C/85 %RH
11.2 Top View: QFN and fcCSP
Figure 60: DA16200 48-Pin QFN Package
Figure 61: DA16200 72-Pin fcCSP Package
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11.3 Dimension: 48-Pin QFN
Figure 62: Top View
Figure 63: Bottom View
Figure 65: DA16200 48-Pin QFN Package
Dimensions
Figure 64: Side View
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11.4 Dimension: 72-Pin fcCSP
Figure 66: Top View
Figure 67: Bottom View
Figure 69: DA16200 72-Pin fcCSP Package
Dimensions
Figure 68: Side View
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11.5 Land Pattern: 48-Pin QFN
Unit: Millimeters (mm)
Pad: Metal mask = 1:1
6.6
4.6
0.7
24
13
25
12
6.6 4.6
0.4
36
1
0.22
37
48
0.3
Figure 70: DA16200 48-Pin QFN Land Pattern
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11.6 Land Pattern: 72-Pin fcCSP
Unit: Millimeters (mm)
Pad: Metal mask = 1:1
3.8
3.11
0.25
0.4
A
B
C
D
E
F
G
H
J
K
L
M
3.11 3.8
1 2 3 4 5 6 7 8 9 10 1112
Figure 71: DA16200 72-Pin FcCSP Land Pattern
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11.7 Soldering Information
11.7.1 Recommended Condition for Reflow Soldering
Figure 72 shows the typical process flow to install surface mount packages to the PCB.
The reflow profile depends on the solder paste being used and the recommendations from the paste
manufacturer should be followed to determine the proper reflow profile. Figure 72 shows a typical
reflow profile when a no-clean paste is used. Oven time above liquidus (260 °C for lead-free solder)
is 30 to 60 seconds.
Since solder joints are not exposed in QFN packages, any retouch is not possible and the whole
package has to be removed if the surface mount process results in shorts or opens. Furthermore,
rework of QFN packages can be a challenge due to their small size. In most applications, QFNs will
be installed on smaller, thinner, and denser PCBs, and introduces further challenges due to handling
and heating issues. Since reflow of adjacent parts is not desirable during rework, the proximity of
other components may further complicate this process. Because of the product dependent
complexities, the following steps only provide a guideline and a starting point for the development of
a successful rework process for the QFN packages.
The rework process involves the following steps:
1. Component removal
2. Site redress
3. Solder paste application
4. Component placement
5. Component attachment
Figure 72: Typical PCB Mounting Process Flow
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Table 69: Typical Reflow Profile (Lead Free): J-STD-020C
Profile Feature
Lead Free SMD
Average ramp up rate (Tsmax to Tp)
3 °C/s Max.
Preheat
●
●
●
Temperature Min (Tsmin
Temperature Max (Tsmax
Time (Tsmax to Tsmin
)
●
●
●
150 °C
200 °C
)
)
60 to 180 seconds
Time maintained above
●
●
Temperature (TL)
Time (tL)
●
●
217 °C
60 to 150 seconds
Peak/Classification temperature (Tp)
Time within 5 °C of peak temperature (tp)
Ramp down rate
260 °C
20 to 40 seconds
6 °C/s Max.
8 minutes Max.
Time from 25 °C to peak temperature
Figure 73: Reflow Condition
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12 Ordering Information
The ordering number consists of the part number followed by a suffix indicating the packing method.
For details and availability, please consult Dialog Semiconductor’s customer support portal or your
local sales representative.
Table 70: Ordering Information (Samples)
Part Number
Package
QFN48
Size (mm)
6 × 6
Shipment Form
Pack Quantity
100/500
DA16200-00000A32
DA16200-00000F22
Reel
Reel
fcCSP72
3.8 × 3.8
100/500
Table 71: Ordering Information (Production)
Part Number
Package
QFN48
Size (mm)
6 × 6
Shipment Form
Pack Quantity
3000
DA16200-00000A32
DA16200-00000F22
Reel
Reel
fcCSP72
3.8 × 3.8
4000
Part Number Legend:
DA16200-RRXXXYYZ
RR: Chip revision number
XXX: variant (000: No Flash)
YY: package code (A3: QFN48, F2: fcCSP72)
Z: packing method (1: Tray, 2: Reel, A: Mini-Reel)
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Revision History
Revision
Date
Description
●
●
Table 1 Updated Pinout Description
Section 6.1 Added Note for Power on Sequence and Updated
Table 26 and Figure 11
3.3
03-Fab-2021
●
●
Section 9.7.3 Fixed typo
Section 10 Updated RC Delay Description (Table 61, Table 63,
Table 65, Table 67 and Figure 56, Figure 57, Figure 58, Figure
59)
●
●
●
●
●
●
●
Section 6.3 Updated Sleep mode Description
Removed F_xx pins in Interface Parts
Section 4.3 (Table 3) Updated Pin Multiplexing
Section 9.8 (Table 52) Updated ADC Reference Voltage
Section 9.5.1 and 9.5.2 Updated I2C Speed Description
Section 9.5 Updated I2C interface (Table 43) and (Table 45)
3.2
28-Sep-2020
Section 9.7.1 and 9.7.2 Added, I2S Description, Block Diagram,
and Clock Scheme
●
Section 9.8.2 Table 52 Swapped SNDR, SNR value
●
●
●
●
●
●
●
●
●
Section 3, Modified Description to Network subsystem layer.
Section 3, Figure 2 Modified Hardware Block diagram
Section 4.2 (Table 1), Reset state changed to Initial state.
Section 4.3 (Table 3) Updated Pin multiplexing.
Section 5.2 (Table 5) Updated FDIO_LDO_OUT value
Section 5.3 Updated Electrical Characteristics
Section 5.4.2 (Table 14) Updated fcCSP TX min/max value
Section 5.5 Updated Current Consumption value
Section 6.2 Added Description and Updated Power management
block diagram (Figure 12).
●
●
Section 6.3 Updated Sleep mode Description
3.1
3-Jul-2020
Section 7.4 (Table 28) Updated RTC_PWR_KEY description and
Remove one sentence which leads to misunderstanding.
Section 9.5.1 (Table 43),(Table 45) Updated I2C Speed
Section 9.9.1 Added Diversity Description and (Figure 46)
Section 9.10.3 Added UART Baud rate Description
●
●
●
●
Section 10.1, 10.2 Updated QFN Application Schematic (Figure
56),(Figure 57) and Description.
●
Section 10.3, 10.4 Updated fcCSP Application Schematic (Figure
58),(Figure 59) and Description, (Table 65),(Table 67). And Added
note after table IO Power Domain
●
●
Page 93 Updated Description about Reach and RoHS
Compliance
3.0
26-Mar-2020
Final release
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Revision
Date
Description
●
●
●
●
●
●
●
●
●
●
●
Feature, Wi-Fi Alliance certification: Detailed added
Section 5.4.1 and 5.4.2 measurement condition CH1 added
Section 9.10.1 RS-232 added
Section 9.10.3 Hardware Flow Control added
Section 9.10.4 Interrupts added
Table 3 Pin Multiplexing changed
Section 11.1 MSL added
Figure 54. DA16200 fcCSP Package Top view added
Application circuit (QFN, fcCSP) BOM changed
Feature deleted: DPD function support
2.9
11-Feb-2020
Rx and Tx min/max value added for the QFN package (Table 12
and Table 14)
●
Rx and Tx min/max value added for the fcCSP package (Table 13
and Table 15)
●
●
Table 17 and Table 20 updated
ESD ratings added for the QFN and fcCSP packages in Table 21
and Table 22
●
●
●
●
●
Pin name "RTC_SEN_OUT" changed to "RTC_GPO"
Pull-down resistor added in Figure50, Figure51, Figure52
QFN48 package "RTC_WAKE_UP" and "RTC_WAKE_UP2"
fcCSP72 package "RTC_WAKE_UP"
2.3
2.2
5-Sep-2019
Ordering information sample and production pack quantity
updated
●
●
Application circuit revised in QFN and fcCSP package
RTC_WAKE_UP pull-down resistor added
●
●
Added Figure 71: DA16200 72-Pin fcCSP Land Pattern
AC characteristics and current consumption of fcCSP data
updated in Table 13, Table 15, and Table 18
12-Aug-2019
●
●
Ordering information added
Added "3.8 mm × 3.8 mm, 0.4 mm pitch, 72-Pin, fcCSP" in
package type in key features
●
●
Added Figure 5, Figure 8, and Figure 10
Added pin numbers for fcCSP package in Table 1, Table 28,
Table 34, Table 38, Table 40, Table 42, Table 44, Table 46, Table
48, Table 53, Table 56, and Table 60
●
●
●
Added "GPIOC6~GPIOC8, TMS/TCLK, TXD/RXD" in the
description of Pin13/M8 in Table 1
Added "GPIOA0~GPIOA11" in the description of Pin35/C1 in
Table 1
2.1
30-Jul-2019
Added "fcCSP GND Pin
A1,A9,B6,B10,B12,C7,C9,C11,D8,D10,F6,F8,F10,F12,G5,G7,G9,
H4,H8,H10,J3,K2,L5,M6,M12,E5" in Table 1
●
●
●
●
●
●
●
In Table 3 SPI master contents updated
Added information on fcCSP pins in section 5.1 and 5.2
Added Table 13, Table 15, and Table 18
Added section 10.3
Updated section 11.1 to include information on fcCSP
Added section 11.4
Changed the caption of Table 27 to "OTP Map"
2.0
03-Jul-2019
Preliminary datasheet
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Status Definitions
Revision
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Definition
This datasheet contains the design specifications for product development.
Specifications may be changed in any manner without notice.
1.<n>
Target
Development
This datasheet contains the specifications and preliminary characterization
data for products in pre-production. Specifications may be changed at any
time without notice in order to improve the design.
2.<n>
3.<n>
Preliminary
Qualification
This datasheet contains the final specifications for products in volume
production. The specifications may be changed at any time in order to
improve the design, manufacturing and supply. Major specification changes
are communicated via Customer Product Notifications. Datasheet changes
are communicated via www.dialog-semiconductor.com.
Final
Production
Archived
This datasheet contains the specifications for discontinued products. The
information is provided for reference only.
4.<n>
Obsolete
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