74LVQ244SCX [ETC]
Dual 4-Bit Non-Inverting Buffer/Driver ; 双4位非反相缓冲器/驱动器\n
| 型号： | 74LVQ244SCX |
| 厂家： | 
ETC |
| 描述： | Dual 4-Bit Non-Inverting Buffer/Driver
|
| 文件： | 总6页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1992
Revised June 2001
74LVQ244
Low Voltage Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
Features
■ Ideal for low power/low noise 3.3V applications
The LVQ244 is an octal buffer and line driver designed to
be employed as a memory address driver, clock driver and
bus oriented transmitter or receiver which provides
improved PC board density.
■ Implements patented EMI reduction circuitry
■ Available in SOIC JEDEC, SOIC EIAJ and QSOP pack-
ages
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Improved latch-up immunity
■ Guaranteed incident wave switching into 75Ω
■ 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ244SC
74LVQ244SJ
Package Number
M20B
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
M20D
74LVQ244QSC
MQA20
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Truth Tables
Inputs
Outputs
OE1
In
(Pins 12, 14, 16, 18)
L
L
L
H
X
L
H
Z
Pin Descriptions
Pin Names
Description
H
OE1, OE2
I0–I7
3-STATE Output Enable Inputs
Inputs
Outputs
Inputs
OE2
In
(Pins 3, 5, 7, 9)
O0–O7
Outputs
L
L
L
H
X
L
H
Z
H
H = HIGH Voltage Level L = LOW Voltage Level
X = Immaterial Z = High Impedance
© 2001 Fairchild Semiconductor Corporation
DS011356
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Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
2.0V to 3.6V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Operating Temperature (TA)
−40°C to +85°C
DC Output Diode Current (IOK
)
Minimum Input Edge Rate ∆V/∆t
V
V
O = −0.5V
−20 mA
+20 mA
V
IN from 0.8V to 2.0V
O = VCC + 0.5V
VCC @ 3.0V
125 mV/ns
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
or Sink Current (IO)
±50 mA
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
DC VCC or Ground Current
(ICC or IGND
)
±400 mA
Storage Temperature (TSTG
DC Latch-Up Source or
Sink Current
)
−65°C to +150°C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
±300 mA
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
Typ
Guaranteed Limits
Minimum High Level
Input Voltage
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
OUT = −50 µA
IN = VIL or VIH (Note 3)
3.0
1.5
2.0
2.0
V
VIL
Maximum Low Level
Input Voltage
V
3.0
3.0
3.0
3.0
3.0
1.5
0.8
2.9
0.8
2.9
V
V
V
V
V
VOH
Minimum High Level
Output Voltage
2.99
I
V
2.58
0.1
2.48
0.1
I
I
OH = −12 mA
OUT = 50 µA
VOL
Maximum Low Level
Output Voltage
0.002
V
IN = VIL or VIH (Note 3)
OL = 12 mA
VI = VCC, GND
0.36
±0.1
0.44
I
IIN
Maximum Input Leakage Current
Minimum Dynamic (Note 4)
Output Current
3.6
3.6
3.6
±1.0
36
µA
mA
mA
IOLD
IOHD
ICC
V
V
V
OLD = 0.8V Max (Note 5)
OHD = 2.0V Min (Note 5)
IN = VCC
−25
Maximum Quiescent
Supply Current
3.6
4.0
40.0
µA
or GND
IOZ
Maximum 3-STATE
Leakage Current
VI (OE) = VIL, VIH
VI = VCC, GND
3.6
±0.25
±2.5
µA
VO = VCC, GND
VOLP
VOLV
VIHD
VILD
Quiet Output
Maximum Dynamic VOL
3.3
3.3
3.3
3.3
0.4
−0.4
1.7
0.8
−0.8
2.0
V
V
V
V
(Note 6)(Note 7)
(Note 6)(Note 7)
(Note 6)(Note 8)
(Note 6)(Note 8)
Quiet Output
Minimum Dynamic VOL
Minimum High Level
Dynamic Input Voltage
Maximum Low Level
Dynamic Input Voltage
1.7
0.8
Note 3: All outputs loaded thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f = 1 MHz.
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2
AC Electrical Characteristics
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
Symbol
Parameter
VCC
C
L = 50 pF
C
Units
(V)
2.7
Min
2.0
2.0
2.5
2.5
1.0
1.0
Typ
8.4
7.0
9.6
8.0
10.8
9.0
1.0
1.0
Max
12.7
9.0
Min
tPHL
tPLH
tPZL
Propagation Delay
2.0
2.0
2.5
2.5
1.0
1.0
14.0
9.5
ns
ns
ns
ns
Data to Output
3.3 ± 0.3
2.7
Output Enable Time
16.9
12.0
19.0
13.5
1.5
18.0
12.5
20.0
14.0
1.5
tPZH
tPHZ
tPLZ
3.3 ± 0.3
2.7
Output Disable Time
3.3 ± 0.3
2.7
tOSHL
tOSLH
Output to Output
Skew Data to Output (Note 9)
3.3 ± 0.3
1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation Capacitance
Note 10: CPD is measured at 10 MHz.
Typ
4.5
70
Units
pF
Conditions
CIN
CPD (Note 10)
V
V
CC = Open
CC = 3.3V
pF
3
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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4
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package Number MQA20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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6
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