AD6435 [ETC]
XDSL INTERFACE|ADSL|INTERFACE|QFP|128PIN|PLASTIC ; xDSL接口| ADSL |界面| QFP | 128PIN |塑料\n
| 型号： | AD6435 |
| 厂家： | 
ETC |
| 描述： | XDSL INTERFACE|ADSL|INTERFACE|QFP|128PIN|PLASTIC
|
| 文件： | 总12页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
ADSL Chipset
AD6435
GENERAL D ESCRIP TIO N
FEATURES
T he AD6435 is part of the Analog Devices ADSL chipset, the
AD20msp910. It accompanies the AD6436 (DMT accelerator),
AD6437 (single-chip analog front end) and ADT SP-2183 (con-
trol and DSP). Object code is also supplied. Offering a flex-
ible, standard-based approach (designed to ANSI T 1.413,
Category 1) with low total bill of materials and high perfor-
mance, the chipset offers a straightforward approach to realizing
an ADSL modem.
Com ponent in Analog Devices DMT ADSL Chipset—
AD20m sp910
Designed to ANSI/ ETSI T1.413
Suitable for CO or Residence (ATU-R and ATU-C)
Perform s All Digital Interface Tasks:
Elastic Store; Byte-Stuffing/ Robbing
Synchronization and EOC and AOC Insertion/ Rem oval
CRC Generation/ Detection
Scram bler and Descram bler
Forw ard Error Correction/ Detection
Interleave/ Deinterleave
Absolute Maxim um Data Rate: 12 Mbps Sim plex/
4 Mbps Duplex
Sim ple Interface: Synchronous Sim plex and Duplex
Stream s
128-Lead TQFP
Operating Tem perature Range: –40؇C to +85؇C
3.3 V Operation, 400 m W
T he AD6435 interfaces the ADSL modem to the external sys-
tem, at either CO or RT modem. It implements all the bit-
stuffing/robbing and elastic store operations, and all digital
processing (block and forward error correction, scrambling,
interleaving, etc.). T he AD6435 has four simple synchronous
connections, duplex in and out, simplex in (only used at
AT U-C) and simplex out (used at AT U-R), which may be
treated as the AS0 Simplex and LS0 duplex stream of the stan-
dard. T hese have “clean” clock and data, and may operate
asynchronously of one another, or of the modem itself.
FUNCTIO NAL BLO CK D IAGRAM
BYPASS PORT
DUPLEX_TX
DUPLEX_RX
TRANSMIT
TO AD6436/AD6439
ELASTIC STORE,
FRAMING,
BYTE–STUFF/ROB
DIGITAL LOGIC,
FEC, CRC
INTERLEAVING
SIMPLEX_TX
(ATU-C)
RECEIVE
CONTROL
FROM AD6436/AD6439
SIMPLEX_RX
(ATU-R)
AD6435
INTERLEAVE RAM
TO ADTSP2183
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD6435–SPECIFICATIONS
P aram eter
Units
Com m ents
ABSOLUT E MAXIMUM SIMPLEX DAT A RAT E
12.288 Mbps
Absolute Maximum.
May not be achieved under realistic conditions.
Actual performance will depend on copper loop.
ABSOLUT E MAXIMUM DUPLEX DAT A RAT E
4.096 Mbps
Absolute Maximum.
May not be achieved under realistic conditions.
Actual performance will depend on copper loop.
INT ERNAL PLL FOR CLOCK REGENERAT ION
VDD SUPPLY VOLT AGE
176.64 MHz
3.3 V ± 10%
400 mW
Resolution is 172.5 Hz/Bit 0.076 Unit Intervals.
POWER DISSIPAT ION
T ypical
TA OPERAT ING T EMPERAT URE
–40°C to +85°C
Specifications are subject to change without notice.
ELECTRICAL SP ECIFICATIO NS
ABSO LUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Operating T emperature Range (Ambient) . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (5 sec) T QFP . . . . . . . . . . . . . . . . +280°C
P aram eter
Typ Value
Com m ents*
VOH
VOL
VIH
VIL
IIH
VDD–0.4 V dc
0.4 V dc
2.0 V dc
1.0 V dc
±500 nA
±500 nA
At IOH = –0.5 mA
At IOL = +1.0 mA
VIN = VDD = 3.6 V
VIN = 0 V, VDD = 3.6 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
IIL
*VDD = 3.3 V dc ± 10%.
O RD ERING GUID E
Model
Tem perature Range
P ackage D escription
128-Lead Plastic T hin Quad Flatpack
P ackage O ption
AD6435
–40°C to +85°C
ST -128
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6435 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–2–
REV. 0
AD6435
P IN CO NFIGURATIO N
D1
D0
102
101
100
99
98
97
96
95
94
1
2
A2
A3
A4
PIN 1
IDENTIFIER
TEST4
3
SIMPLX_TX
4
A5
SIMPLX_CLK
I
5
A6
SIMPLX_CLKO
VDD1
6
A7
7
VDD11
GND11
DSP_CLK
GND1
8
SIMPLX_RX
DUPLX_TX
DUPLX_CLKI
DUPLX_CLKO
DUPLX_RX
RX_BUF
VDD2
9
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A8
A9
A10
A11
A12
VDD10
GND10
A13
GND2
AD6435
DTIR
128 TQFP
TOP VIEW
(Not to Scale)
RFS
RX_FR
RX_FRM
RX_SDATA
RX_DREQ
RX_BS
TX_RX_SCLK
GND9
RX_SPFR
RX_SPFRI
TX_BUF
TFS
GND3
VDD3
VDD9
TX_FR
TX_FRM
TX_SDATA
TX_BS
TX_DREQ
MCLK
TX_SPFR
MCLK_OUT
TEST0
TEST1
RT_NCO
GND4
NM_OE
GND8
VDD4 32
VDD8
33
34
35
36
37
38
NC
NM_WE
M_A14
M_A13
M_A12
M_A11
M_A10
NC
PLL_GND
PLL_VDD
PLL_RBIAS
NC
NC = NO CONNECT
REV. 0
–3–
AD6435
P IN D ESCRIP TIO N
T he AD6435 contains 91 signal pins, 33 output pins, 35 input pins, and 24 bidirectional pins. T here are also 5 test pins and
28 digital supply pins, 2 analog supply pins, and 1 PLL bias pin for the PLL.
P IN FUNCTIO N D ESCRIP TIO NS
P in No.
P in Nam e
Type
D escription
1–2
3
D1, D0
I/O
16-Bit Data Bus for DSP Port. See also 111:114, 117:124, 127:128.
T ie to Ground T hrough a 10 kΩ Resistor.
Input Downstream Data at CO. Pin not used at RT .
Input Clock at CO for Downstream Data. Pin is not used at RT .
Recovered Downstream Clock at RT . Pin not used at CO.
3.3 V.
T EST 4
Input
4
SIMPLX_T X
SIMPLX_CLKI
SIMPLX_CLKO
VDD1
Input
5
Input
6
Output
Supply
Supply
Output
Input
7
8
GND1
Ground.
9
SIMPLX_RX
DUPLX_T X
DUPLX_CLKI
DUPLX_CLKO
DUPLX_RX
RX_BUF
Received Downstream Data at RT . Pin not used at CO.
Input Duplex Data.
10
11
12
13
14
Input
Input Duplex Clock.
Output
Output
Output
Recovered Duplex Clock.
Received Duplex Data Stream.
T ICL Bypass—RX Data Buffer. If T CIL is not used, this pin must have a
pull-up resistor.
15
VDD2
Supply
Supply
Output
Output
Output
Output
Input
3.3 V.
16
GND2
Ground.
17
RFS
T ICL Bypass—RX Byte Sync.
T ICL Bypass—RX Frame Sync. 10 kΩ to Ground.
T ICL Bypass—T ICL Superframe Sync.
T ICL Bypass—RX Interleaved Superframe Sync.
T ICL Bypass—T X Data Buffer.
T ICL Bypass—T X Byte Sync.
Ground.
18
RX_FR
RX_SPFR
RX_SPFRI
T X_BUF
T FS
19
20
21
22
Output
Supply
Supply
Output
Output
Output
23
GND3
24
VDD3
3.3 V.
25
T X_FR
T X_SPFR
MCLK_OUT
T EST 0
T EST 1
RT _NCO
GND4
T ICL Bypass—T X Frame Sync.
T ICL Bypass—T X Superframe Sync.
T ICL Bypass—Output MCLK.
No Connection.
26
27
28
29
No Connection.
30
Mode Pin, 1 = RT Mode, 0 = CO Mode.
Ground.
31
Supply
Supply
32
VDD4
3.3 V.
33, 34
35
NC
No Connect.
PLL_GND
PLL_VDD
PLL_RBIAS
NC
PLL Analog Ground.
PLL Analog Power.
36
37
T ie to Ground T hrough a 30 kΩ Resistor.
No Connect.
38
39
T EST 2
T EST 3
VDD5
Input
T ie to Ground T hrough a 10 kΩ Resistor.
No Connection.
40
T hree-State
Supply
Supply
I/O
41
3.3 V.
42
GND5
Ground.
43–50
51
M_D7–0
VDD6
Data for Interleave Ram.
3.3 V.
Supply
Supply
Output
52
GND6
Ground.
53–60
M_A0–7
Address Bus for Interleave Ram. See also Pins 60–66.
–4–
REV. 0
AD6435
P IN FUNCTIO N D ESCRIP TIO NS (Continued)
P in No.
P in Nam e
Type
D escription
61
GND7
Supply
Supply
Output
Output
Supply
Supply
Output
Input
Ground.
62
VDD6
3.3 V.
63–69
70
M_A8–14
NM_WE
VDD8
Address Bus for Interleave Ram. See also Pins 50–57.
Write Enable for Interleave Ram.
3.3 V.
71
72
GND8
Ground.
73
NM_OE
MCLK
Output Enable for Interleave Ram.
T he AD6435 Master Clk (35.328 MHz).
Data Request Provided by the AD6436.
T ransmit Byte Strobe Provided by the AD6435.
T ransmit Serial Data Provided by the AD6435.
T ransmit Frame Strobe Provided by the AD6436.
3.3 V.
74
75
T X _DREQ
T X _BS
T X _SDAT A
T X _FRM
VDD9
Input
76
Output
Output
Input
77
78
79
Supply
Supply
Input
80
GND9
Ground.
81
T X _RX_SCLK
RX_BS
T ransmit and Receive Serial Clock.
Receive Byte Strobe Provided by the AD6436.
Receive Data Request Provided by the AD6435.
Receive Serial Data Provided by the AD6436.
Receive Frame Strobe Provided by the AD6436.
82
Input
83
RX_DREQ
RX_SDAT A
RX_FRM
A13
Output
Input
84
85
Input
86
Input
14-Bit Address Bus for DSP Port. See also 86–90 and 94–101.
87
GND10
VDD10
A12–A8
DSP_CLK
GND11
VDD11
A7–0
Supply
Supply
Input
Ground.
88
3.3 V.
89–93
94
14-Bit Address Bus for DSP Port. See also 83 and 94–101.
Input
DSP Output Clock.
95
Supply
Supply
Supply
Supply
Supply
Input
Ground.
96
3.3 V.
97–104
105
106
107
108
109
110
111–114
115
116
117–124
125
126
127, 128
14-Bit Address Bus for DSP Port. See also 83 and 86–90.
VDD12
GND12
NCS
3.3 V.
Ground.
DSP Memory Select. Active Low.
NRD
Input
DSP Memory Read Enable, Active Low.
NWR
Input
DSP Write Enable, Active Low.
NRESET
D15–D12
VDD13
GND13
D11–D4
GND14
VDD14
D3–D2
Input
Reset Pin, Active Low.
I/O
16-Bit Data Bus for DSP Port. See also 1–2, 117–124, 127–128.
Supply
Supply
I/O
3.3 V.
Ground.
16-Bit Data Bus for DSP Port. See also 1–2, 111–114, 127–128.
Supply
Supply
I/O
Ground.
3.3 V.
16-Bit Data Bus for DSP Port. See also 1–2, 111–114, 117–124.
REV. 0
–5–
AD6435
When used as part of the AD20msp910 ADSL chipset, the
internal functionality is under the control of the firmware sup-
plied with the ADT SP2183, and the Messaging Protocol (MP)
implemented there. T his protocol supplies a hardware-neutral
method of controlling the operation of the ADSL chipset, which
will be compatible between different hardware implementations.
INTRO D UCTIO N
T he AD6435 is the interface chip in the AD20msp910 ADSL
chipset, connecting the core transceiver functions to the external
system. T he other portions within the AD20msp910 chipset are
the AD6436 (which connects to the AD6435 and is responsible
for the core DMT signal processing), the AD6437 analog front-
end IC, the AD816 driver/receiver and ADT SP2183, which is
used as the system control processor. An object code licence for
all modem software is supplied with the AD20msp910 chipset.
T he AD6435 can implement rate adaptive ADSL (RADSL).
T his is under the control of the MP, and several different modes
are supported.
T he AD6435 implements a generic interface, with straightfor-
ward synchronous clock and data streams corresponding to
simplex and duplex bearer channels. T hese can be considered as
the AS0 (simplex) and LS0 (duplex) streams as per the standard,
but can run at any rate; the “duplex” channel can be treated as
two independent streams, one up and one down. This implemen-
tation is a simplified variant of that described in ANSI T 1.413.
It is easy to use this structure to connect to the rest of the sys-
tem, or to external devices, such as framers or dedicated ICs for
particular protocols. Variants of the AD6435 with support for
specific functions or interfaces (e.g., AT M, Ethernet) are under
development.
T he absolute maximum data rate of the AD6435 is 12 Mbps
downstream, and 4 Mbps upstream. However, the rate depends
primarily on the channel conditions, and these rates will not be
achieved on real loops, with attenuation and crosstalk.
ADTSP2183 INTERFACE
RX_BUF
RFS
RX_FR
TX_RX_SCLK
T here are two main blocks within the AD6435:
RX_SPFR
RX_SPFRI
TX_DREQ
•
T he digital processing section (Digital Interface Area or
“DIA”), which is responsible for error correction, scram-
bling, interleaving, AOC and control operations. T his is
based on the earlier AD6442 device. T his is a highly pro-
grammable system, whose operation is not restricted to the
operating modes as defined in ANSI T 1.413, but which
could be used in variety of systems. T he DIA supports the
following codeword cases:
TX_FRM
TX_BUF
TX_BS
TX_FR
TX_SDATA
TFS
DTIR
TX_SPFR
RX_FRM
RX_BS
MCLK_OUT
RX_SDATA
RX_DREQ
DUPLX_RX
DUPLX_CLKO
DUPLX_CLKI
DUPLX_TX
M_A(14:0)
M_D(7:0)
NM_WE
NM_OE
a. One codeword per frame in the fact and/or interleaved
data portion of a frame.
SIMPLX_CLKI
SIMPLX_TX
b. Multiple codewords per frame in the fast and/or inter-
leaved data portion, providing the codeword length evenly
divides into the output (DME) frame length.
SIMPLX_CLKO
SIMPLX_RX
c. Multiple frames per codeword on the interleaved portion
of the frame only, up to 20 frames per codeword. T he
number of checkbytes must be an integer multiple of the
number of frames in the codeword.
CONTROL INTERFACE
Figure 1. Functional Diagram
d. Codewords may span superframes.
•
T he interface block (T ransceiver Interface and Control Logic
or “T ICL”), which handles the framing, signal buffering and
data retiming functions required to support clean synchronous
data streams. (This essentially corresponds to the transmission
convergence layer of a stack.) As some designs may not require
the TICL block, there is a bypass mode, in which this block is
powered down and there is access to the unformatted/unframed
data stream from the DIA.
INTERFACES
T he standard interface is a very straightforward buffered and
demultiplexed synchronous connection. It is physically the same
at both AT U-R and AT U-C, and presents four channels—
simplex in and out, duplex in and out—with just two signals per
connection, clock and data (obviously, only three of these chan-
nels can be used at an end; with the AT U-C using simplex_in
and the AT U-R simplex_out). T hese streams are independent
and can be used asynchronously of one another. No framing
signals are provided.
T his data sheet gives a user’s description of the AD6435. It
describes functionality and interfacing, but does not give any
details of the internal structure. For details of the internal struc-
ture, see the AD6435 User’s Manual, available on request.
T he “duplex” stream can be used as a true duplex carrier (same
rates upstream and downstream) or the two may be independent
(i.e., the chipset has two simplex downstream paths, one fast
and one slower, and one simplex upstream).
–6–
REV. 0
AD6435
Table I. Interface D escriptions
D escription
In general tx clock signals (i.e., duplex_clcki, simplex_clki)
are input to the AD6435, while the received data clock sig-
nals (duplex_clko, simplex_clko) are outputs. In other words,
the sending modem (at AT U-C or AT U-R) supplies the clock
to the AD6435, and the receiving modem’s AD6435 recovers it
(using a digital phase locked loop) and supplies it to the external
system. T he channels all have separate—independent—clocks.
Nam e
duplex_rx
Duplex data output from the AD6435 (i.e.,
data received).
Clock associated with duplex_rx (output).
Duplex data input to the AD6435 (i.e.,
data to be transmitted).
Clock associated with duplex_tx input.
Simplex data output from the AD6435.
AT U-R: downstream data received.
AT U-C: not used.
Clock associated with simplex_rx (output).
Simplex data input to the AD6435.
AT U-R: not used.
duplex_clko
duplex_tx
There are two exceptions; the duplex streams can be “locked” with
a single clock or, in a “one down/one up” system typical for data
applications, the unused DPLL can be programmed to be a clock
source at the desired data rate for the tx channel.
duplex_clki
simplex_rx
T o avoid overflow/underflow of internal buffers, the clock rate
of the streams should be held roughly constant. As such, al-
though a degree of jitter or rate variation is supported, pure
burst-mode is not, and idle cell insertion (deletion) is necessary
and must be implemented by an external device.
simplex_clko
simplex_tx
AT U-C: downstream data to be sent.
Clock associated with simplex_tx (input).
simplex_clki
Alternatively, the buffering multiplex/demultiplex and bit-stuff/
rob operations may be bypassed (T ICL bypass operation).
T hese blocks are then powered down, reducing the AD6435’s
power consumption. T he interface presented is then a “raw”
stream of upstream and downstream data. As the elastic store
has been disabled, these have the relic of the ADSL line super-
frame structure, and will show an irregular clock (with a pause
for every 69th frame). This mode is compatible with the AD6442
DIA interface and is suited to packet (e.g., AT M) operation. It
results in a slight power saving.
PAYLOAD DATA IN
PAYLOAD DATA OUT
ELASTIC STORE
EOC
REMOVE
EOC INSERT
SYNC
FRAMER
CRC
FRAMER
AD6435
CRC
DETECT
RAM
ARBITRATION
NB: Although the AD6435 can implement the T 1.413 stan-
dard, and includes the required framing/interfacing (e.g.,
elastic store, bit-stuffing/robbing), it does not support the full
optional suite of seven bearer streams (ASx and LSx) and
associated multiplexing/demultiplexing as defined in T1.413.
Instead, simple synchronous data streams are provided. T hese
are essentially AS0 (simplex) and LS0 (duplex) but with vari-
able rate or rate adaptive (not merely fixed multiples of standard
PDH rates, as per Chapter 5 of T 1.413). Additionally, the “du-
plex” stream can be treated as two independent streams, one up
and one down. Indeed, in many applications, only one stream in
each direction is required; in this case, the downstream duplex
path is not used.
SCRAMBLER
UNSCRAMBLE
FEC
DECODE
FEC
ENCODE
INTERLEAVER
DE-INTERLEAVER
RAM
TONE
REORDER
TONE
SHUFFLE
CONSTELLATION
ENCODE
CONSTELLATION
DECODE
AD6436
INVERSE
FFT
FFT
Further T C-layer operations can be defined by the system for
their requirements (e.g., for V.35, AT M or 10BaseT ), and sim-
ply interfaced to the AD6435 serial ports.
DECIMATE
& TDQ
INTERPOLATE
INTERFACE TIMING
T he DT IR contains simplex (AS) and duplex (LS) channels
that interface with the Central Office (CO) and Remote T ermi-
nal (RT ). T he DT IR contains a transmit serial port in which the
DT IR transmits a bit stream to the DME and a receive serial
port in which DT IR receives a serial bit stream from the DME.
Since the DIA is being treated as a black box, the T ICL-DIA
interface will be defined here. T his interface is similar to the
DIA-DME transmit and receive interfaces. T he DT IR also
interfaces with a 32k × 8 Interleave RAM. T he DT IR also has a
DSP host port that allows a DSP to monitor the DT IR and
control the data through the device.
SERIAL DAC
(TO VCXO)
CONTROL
ADC
DAC
AD6437
FILTER
FILTER
PGA
RECEIVER
DRIVER
POTS
SPLITTER
HYBRID
AD816
DRIVER/RECEIVER
Figure 2. AD20m sp910 System Block Diagram
REV. 0
–7–
AD6435
and DUPLX_CLKI. T he serial clock rate is completely variable
between 8 kbps and 4.096 Mbps. T he interface operates identi-
cally at the CO and RT locations. T he input interface can ac-
cept a continuous stream of data at a fixed frequency within the
duplex rate. T he output interface on the other end transmits the
same continuous stream of data at the same fixed frequency.
T his frequency is established and programmed into the registers
by the DSP during reset.
CO /RT INTERFACE TIMING
Sim plex Ser ial P or t
T he simplex serial port consists of four pins, two outputs,
SIMPLX_RX and SIMPLX_CLKO, and two inputs, SIMPLX_
T X and SIMPLX_CLKI. T he serial clock rate is completely
variable between 8 kbps and 12.288 Mbps. T he interface
operates differently at the CO and RT locations.
DTIR XMT
RT RECEIVE
For the Duplex Rx channel, data is driven out of the AD6435
on the positive edge of the respective CLKO signal and should
be sampled by the external circuit on the negative edge.
SIMPLX_CLKO
SIMPLX_RX
For the Duplex T x channel, the data is sampled by the AD6435
on the positive edge of the respective CLKO signal and should
be driven by the external circuit on the negative edge.
VALID DATA
tSRX-S
tSRX-H
DTIR XMT
CO/RT RECEIVE
DTIR RECEIVE
CO XMT
SIMPLX_CLKI
DUPLX_CLKO
DUPLX_RX
SIMPLX_TX
VALID DATA
VALID DATA
tSTX-S
tSTX-H
tDRX-S
tDRX-H
CO/RT XMT
DTIR RECEIVE
Figure 3. Sim plex Serial Port
DUPLX_CLKI
Table II. TX Serial I/F Tim ing
D escription
P aram eter
Typ
DUPLX_TX
VALID DATA
tSRX-S
Setup T ime of SIMPLX_RX from
Falling Edge of SIMPLX_CLKO
Hold T ime of SIMPLX_RX from
Falling Edge of SIMPLX_CLKO
Setup T ime of SIMPLX_T X from
Rising Edge of SIMPLX_CLKI
Hold T ime of SIMPLX_T X from
Rising Edge of SIMPLX_CLKI
tDTX-S
tDTX-H
5 ns
5 ns
5 ns
5 ns
tSRX-H
tST X-S
tST X-H
Figure 4. Duplex Serial Port
Table III. TX Serial I/F Tim ing
D escription
P aram eter
Typ
tDRX-S
Setup T ime of DUPLX_RX from
Falling Edge of DUPLX_CLKO
Hold T ime of DUPLX_RX from
Falling Edge of DUPLX_CLKO
Setup T ime of DUPLX_T X from
Rising Edge of DUPLX_CLKI
Hold T ime of DUPLX_T X from
Rising Edge of DUPLX_CLKI
5 ns
5 ns
5 ns
5 ns
At the CO, the two input pins SIMPLX_TX and SIMPLX_CLKI
are used while the two output pins SIMPLX_RX and SIMPLX_
CLKO are not functionally connected. T he interface can oper-
ate at a continuous data stream into SIMPLX_RX at a fixed
frequency between 8 kbps and 12.288 Mbps. T he data rate is
set while the DT IR is in reset and does not change without
going into the reset state again.
tDRX-H
tDT X-S
tDT X-H
At the RT, the two output pins SIMPLX_RX and SIMPLX_
CLKO are used while the two input pins SIMPLX_T X and
SIMPLX_CLKI are not functionally connected. The interface can
operate at a continuous data stream out of SIMPLX_RX at a
fixed frequency between 8 kbps and 12.288 Mbps. T he data
rate is set while the DT IR is in reset and does not change with-
out going into the reset state again.
INTERLEAVE RAM INTERFACE
T he DT IR (DIA) Interfaces an external 32k × 8 Interleave
RAM. T he interleave RAM interface consists of M_A(14:0),
M_D(7:0), NM_WE, and NM_OE. When operating at 3.3 V
RAM must have access time less than 50 ns. For further infor-
mation concerning the operation of the RAM access, consult the
DIA specification.
For the Simplex Rx channel, data is driven out of the AD6435
on the positive edge of the respective CLKO signal and should
be sampled by the external circuit on the negative edge.
D ME INTERFACE TIMING
All signals transmitted by the DME to the DT IR are transmit-
ted on the rising edge and sampled on the falling edge except for
the T X_DREQ signal that is transmitted by the DME on the
falling edge and sampled by the DT IR on the rising edge. All
output signals from the DT IR to the DME are transmitted by
the DT IR on the rising edge and received by the DME on the
rising edge.
For the Simplex Tx channel, the data is sampled by the AD6435
on the positive edge of the respective CLKO signal and should
be driven by the external circuit on the negative edge.
D uplex Ser ial P or t
T he duplex serial port consists of four pins, two outputs,
DUPLX_RX and DUPLX_CLKO, and two inputs, DUPLX_T X
–8–
REV. 0
AD6435
P aram eter
D escription
Typ
Units
TX Ser ial I/F Tim ing
tT FRM-S
tT FRM-H
tT DREQ-S
tT DREQ-H
tT BS-S
tT BS-H
tT D_S
tT D_H
Setup T ime of T X_FRM from Falling Edge of T X_RX_SCLK
Hold T ime of T X_FRM from Falling Edge of T X_RX_SCLK
Setup T ime of T X_DREQ from Rising Edge of T X_RX_SCLK
Hold T ime of T X_DREQ from Rising Edge of T X_RX_SCLK
Setup T ime of T X_BS from Rising Edge of T X_RX_SCLK
Hold T ime of T X_BS from Rising Edge of T X_RX_SCLK
Setup T ime of T X_SDAT A from Rising Edge of T X_RX_SCLK
Hold T ime of T X_SDAT A from Rising Edge of T X_RX_SCLK
5
15
5
15
10
0
ns
ns
ns
ns
ns
ns
ns
ns
5
0
TX_RX_SCLK
TX_FRM
tTFRM-S tTFRM-H
TX_DREQ
tTDREQ-S tTDREQ-H
TX_BS
tTBS-S tTBS-H
TX_SDATA
VALID
tTD-S
DATA
tTD-H
Figure 5. TX Serial I/F Tim ing
P aram eter
D escription
Typ
Units
RX Ser ial I/F Tim ing
tRFRM-S
tRFRM-H
tRDREQ-S
tRDREQ-H
tRBS-S
tRBS-H
tRD-S
tRD-H
Setup T ime of RX_FRM from Falling Edge of T X_RX_SCLK
Hold T ime of RX_FRM from Falling Edge of T X_RX_SCLK
Setup T ime of RX_DREQ from Rising Edge of T X_RX_SCLK
Hold T ime of RX_DREQ from Rising Edge of T X_RX_SCLK
Setup T ime of RX_BS from Falling Edge of T X_RX_SCLK
Hold T ime of RX_BS from Falling Edge of T X_RX_SCLK
Setup T ime of RX_SDAT A from Falling Edge of T X_RX_SCLK
Hold T ime of RX_SDAT A from Falling Edge of T X_RX_SCLK
5
15
5
0
5
15
5
15
ns
ns
ns
ns
ns
ns
ns
ns
TX_RX_SCLK
RX_FRM
tRFRM-S tRFRM-H
RX_DREQ
tRDREQ-S tRDREQ-H
RX_BS
tRBS-S tRBS-H
RX_SDATA
VALID
tRD-S
DATA
tRD-H
Figure 6. RX Serial I/F Tim ing
–9–
REV. 0
AD6435
TX Ser ial P or t
T X_RX_SCLK:
Serial clock provided by DME.
T he T X serial interface between the DME and DT IR uses five
(5) signals:
RX_FRMRX_FRM: Frame strobe provided by DME.
RX_BS:
RX_SDAT A:
RX_DREQ:
Byte strobe provided by DME.
Serial data provided by DME.
Data request provided by DT IR.
T X_RX_SCLK:
T X_DREQ:
T X_FRM:
T X_BS:
T X_SDAT A:
Serial clock provided by DME.
Data request provided by DME.
Frame strobe provided by DME.
Byte strobe provided by DT IR.
Serial data provided by DT IR.
D SP P O RT
T he DSP port consists of a 14-bit address bus, A[13:0], a 16-bit
data bus, D[15:0], DSP_CLK and three bus control pins,
NRD, NWR, NCS.
RX Ser ial Inter face
T he RX serial interface between the DME and DT IR uses five
(5) signals:
P aram eter
Min
Max
Unit
Read O per ation
Timing Requirements:
tRDD
tAA
tRDH
NRD Low to Data Valid
A0–A13, NCS to Data Valid
Data Hold from NRD High
8
14
ns
ns
ns
0
Switching Characteristics:
tRP
NRD Pulsewidth
DSP_CLK High to NRD Low
A0–A13, NCS Setup before NRD Low
A0–A13, NCS Hold after NRD Deasserted
NRD High to NRD or NWR Low
12
3
2
5
12
ns
ns
ns
ns
ns
tCRD
tASR
tRDA
tRWR
16
NOTE:
DSP clock 28 MHz (35.7 ns)
DSP_CLK
A0–A13
NCS
NRD
tRDA
tASR
tCRD
tRP
tRWR
D
tRDD
tRDH
tAA
NWR
Figure 7. Read Operation
–10–
REV. 0
AD6435
P aram eter
Min
Max
Unit
Wr ite O per ation
Switching Characteristics:
tDW
tDH
tWP
tWDE
tASW
tDDR
tCWR
tAW
Data Setup before NWR High
Data Hold after NWR High
NWR Pulsewidth
NWR Low to Data Enabled
A0–A13, NCS Setup before NWR Low
Data Disable before NWR or NRD Low
DSP_CLK High to NWR Low
A0–A13, NCS, Setup before NWR Deasserted
A0–A13, NCS Hold after NWR Deasserted
NWR High to NRD or NWR Low
10
6
12
0
2
1
3
17
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
tWRA
tWWR
12
NOTE:
DSP clock 28 MHz (35.7 ns)
DSP_CLK
A0–A13
NCS
tWRA
NWR
tWWR
tASW
tWP
tAW
tDH
tDDR
tCWR
D
tDW
tWDE
NRD
Figure 8. Write Operation
REV. 0
–11–
AD6435
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
128-Lead P lastic Thin Q uad Flatpack
(ST-128)
0.063 (1.60)
0.630 (16.00) BSC
TYP
0.551 (14.00) BSC
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
128
1
103
102
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.787 0.866
(20.00) (22.00)
BSC
BSC
0.003 (0.08)
MAX
38
65
64
39
0.006 (0.15)
0.002 (0.05)
0.011 (0.27)
0.009 (0.22)
0.007 (0.17)
0.020 (0.50)
BSC
0.057 (1.45)
0.053 (1.40)
0.018 (1.35)
–12–
REV. 0
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