CXL5506M/P [ETC]
CMOS-CCD 1H Delay Line for PAL ; 对于PAL CMOS ， CCD 1H延时线\n
| 型号： | CXL5506M/P |
| 厂家： | 
ETC |
| 描述： | CMOS-CCD 1H Delay Line for PAL
|
| 文件： | 总9页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXL5506M/P
CMOS-CCD 1H Delay Line for PAL
For the availability of this product, please contact the sales office.
Description
CXL5506M
8 pin SOP (Plastic)
CXL5506P
8 pin DIP (Plastic)
The CXL5506M/P are CMOS-CCD delay line ICs
that provide 1H delay time for PAL signals including
the external low-pass filter.
Features
• Single 5V power supply
• Low power consumption 95mW (Typ.)
• Built-in peripheral circuits
Functions
• 1130-bit CCD register
• Clock driver
• Auto-bias circuit
• Input clamp circuit
• Sample-and-hold circuit
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
°C
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
PD
–10 to +60
–55 to +150 °C
Structure
CMOS-CCD
CXL5506M
CXL5506P
350
480
mW
mW
Recommended Operating Condition (Ta = 25°C)
Supply voltage 5 ± 5%
VDD
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.3 to 1.0
Vp-p
(0.5Vp-p typ.)
17.734475 MHz
• Input clock waveform Sine wave
• Clock frequency
fCLK
Input Signal Amplitude
VSIG 575mVp-p (Max.) (at internal clamp condition)
Blook Diagram and Pin Configuration (Top View)
8
7
6
5
Auto-bias circuit
Bias circuit
Timing circuit
Clock driver
Bias circuit (A)
Bias circuit (B)
CCD
(1130bit)
Output circuit
(S/H 1bit)
Clamp circuit
2
3
4
1
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E90632B7X-PS
CXL5506M/P
Pin Description
Pin No. Symbol
Description
Signal input
Impedance
I/O
I
> 10kΩ at no clamp
1
2
3
4
5
6
7
8
IN
VG2
OUT
VSS
CLK
VG1
VDD
AB
I
Gate bias 2 DC input
Signal output
40 to 500Ω
> 10kΩ
O
—
I
GND
Clock input
O
—
O
Gate bias 1 DC output
Power supply (5V)
Auto-bias DC output
600 to 200kΩ
Description of Pin 2 (VG2)
Control of input signal clamp condition
0V ........ Sync tip clamp condition
5V ........ Center bias condition
Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ).
In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is
200mVp-p.
Input waveform
Output waveform
Clamp
level
– 2 –
CXL5506M/P
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 17.734475MHz, VCLK = 500mVp-p, sine wave)
See "Electrical Characteristics Test Circuit"
SW condition
Item
Symbol
Test condition
—
Min. Typ. Max.
Unit Note
2
a
1
a
3
19
0
28
2
mA
dB
1
2
Supply current
10
–2
—
IDD
200kHz,
500mVp-p,
sine wave
Low frequency gain
a
b
a
GL
200kHz ←→ 4.43MHz,
150mVp-p,
sine wave
b
c
d
–1
3
0
dB
3
4
Frequency response
Differential gain
–2
0
b
a
b
c
fR
5-staircase wave
(See Note 4)
5
5
%
DG
5-staircase wave
(See Note 4)
3
degree
4
5
Differential phase
S/H pulse coupling
0
a
b
c
d
f
DP
CP
—
350 mVp-p
dB
—
No signal input
a
50% white
video signal
(See Note 6)
56
—
6
S/N ratio
52
a
d
e
SN
Notes
(1) This is the IC supply current value during clock and signal input.
(2) GL is the output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
OUT pin output voltage [mVp-p]
GL = 20 log
[dB]
500 [mVp-p]
(3) Indicates the dissipation at 4.43MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 4.43MHz sine wave is fed to same, calculation is made
according to the following formula.
OUT pin otuput voltage (4.43MHz) [mVp-p]
fR = 20 log
[dB]
OUT pin output voltage (200kHz) [mVp-p]
– 3 –
CXL5506M/P
(4) In figure below, differential gain (DG) and differential phase (DP) are tested with a vector scope when
the 5-staircase wave is fed.
150mV
350mV
500mV
150mV
1H 64µs
Input waveform
(5) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested.
Test value
(mVp-p)
(6) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in
BPF 100kHz to 5MHz, Sub Carrier Trap mode.
175mV
325mV
150mV
1H 64µs
Input waveform
Clock
4fsc (17.734475MHz) sine wave
0.3 to 1.0Vp-p
(0.5Vp-p typ.)
– 4 –
CXL5506M/P
– 5 –
CXL5506M/P
– 6 –
CXL5506M/P
Example of Representative Characteristics
Supply current vs. Ambient temperature
Low frequency gain vs. Ambient temperature
30
2
1
20
0
–1
–2
10
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temperature [°C]
Ambient temperature [°C]
Frequency response vs. Ambient temperature
Differential gain vs. Ambient temperature
0
10
8
–1
–2
–3
6
4
2
0
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temperature [°C]
Ambient temperature [°C]
Supply current vs. Supply voltage
Low frequency gain vs. Supply voltage
30
2
1
20
0
–1
10
4.75
–2
5
5.25
4.75
5
5.25
Supply voltage [V]
Supply voltage [V]
– 7 –
CXL5506M/P
Frequency response vs.Supply voltage
Differential gain vs. Supply voltage
0
10
8
–1
6
4
–2
–3
2
0
4.75
5
5.25
4.75
5
5.25
Supply voltage [V]
Supply voltage [V]
Frequency response
2
0
–2
–4
–6
10k
100k
1M
10M
Frequency [Hz]
– 8 –
CXL5506M/P
Package Outline
CXL5506M
Unit: mm
8PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
6.1– 0.1
8
5
0.15
+ 0.2
0.1– 0.05
1
4
+ 0.1
0.2 – 0.05
0.45 ± 0.1
1.27
0.24
M
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
SONY CODE
EIAJ CODE
SOP-8P-L01
SOP008-P-0300
42/COPPER ALLOY
0.1g
PACKAGE MASS
JEDEC CODE
CXL5506P
8PIN DIP (PLASTIC)
+ 0.4
9.4 – 0.1
5
8
1
0° to 15°
4
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
DIP-8P-01
EIAJ CODE
DIP008-P-0300
COPPER ALLOY
0.5g
PACKAGE MASS
JEDEC CODE
– 9 –
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