HMS88T6416 [ETC]
Turbo 80C52 Core Based High Security SmartcardController With 16K Bytes EEPROM; 涡轮80C52内核的高安全性SmartcardController用16K字节EEPROM
| 型号： | HMS88T6416 |
| 厂家： | 
ETC |
| 描述： | Turbo 80C52 Core Based High Security SmartcardController With 16K Bytes EEPROM |
| 文件： | 总2页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM S88T6416
HM S88T6416
Turbo 80C52 Core Based High Security Sm artcard Controller
W ith 16K Bytes EEPROM
General Features
• TurboCore : High Security 8-bit 80C52 com patible CPU
9 M ultiple source vectorized interrupt system with two priority levels
9 M ultiple source reset system
• High reliable EEPROM for data storage
9 16KB high reliability EEPROM
9 1 to 64 bytes per a page
9 64 bytes security area (OTP : One Tim e Program m able)
9 Bytewise EEPROM program m ing and read access
9 EEPROM endurance: 500,000 cycles at 25℃
9 EEPROM data retention: m in. 10 years
9 EEPROM m anagem ent library (EM L) with intelligent write algorithm
• 1M Hz to 6M Hz operating clock frequency range for program execution from ROM
• Integrated On-Chip M em ory
9 64KB User ROM : non-visible & scram ble ROM code
9 256B IRAM
9 2KB XRAM
• Integrated Peripherals
9 Interrupt m odule for I/O interface and peripherals
9 UART supporting ISO standard protocols T = 0 and T = 1
9 True random num ber generator in hardware
9 CRC m odule : 16 bit checksum according to ISO3309
• 2.7V to 5.5V extended operating voltage range
• Power saving IDLE m ode
• Low power SLEEP m ode
• Pad configuration according to ISO/IEC 7816: VDD, VSS, CLK, RST and I/O1
• Serial interface according to ISO/IEC 7816-3
• M eets GSM 11.11 and 11.12 Specifications
High Security Sm artcard IC
HM S88T6416
Security Features
• Data encryption according to T-DES standard
• ROM code not visible due to im plantation
• Low/High supply voltage detector
• Low/High clock frequency detector
• M etal shield detector
• Internal power-on-reset
• Unique chip identification num ber for each chip
• M em ory data / address encryption & scram bling
• M em ory segm entation
• Random waitstate generator
ROM
64KB
EEPROM
16KB
XRAM
2KB
Instruction Bus
INTERRUPT
External Bus
SECURITY
SENSORS
CPU
(TurboCore)
M EU
IRAM
SFR Bus
IO
RST
CLK
UART
TIM ER0/1
CRC
TDES
RNG
Block Diagram
High Security Sm artcard IC
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