ISP1280 [ETC]
Controller Miscellaneous - Datasheet Reference ; 控制器杂项 - 数据表参考\n
| 型号： | ISP1280 |
| 厂家： | 
ETC |
| 描述： | Controller Miscellaneous - Datasheet Reference
|
| 文件： | 总4页 (文件大小：29K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QLogic Corporation
ISP1280 Intelligent, Dual SCSI Processor
Data Sheet
■ No host intervention required to execute SCSI
Features
operations from start to finish
■ Simultaneous, multiple logical threads
■ JTAG boundary scan support
■ Compliance with ANSI X3T10/1142D SCSI
Parallel Interconnect-2 (SPI-2) draft
■ 64-bit PCI host bus interface, compliant with PCI
Local Bus Specification rev 2.1
■ Compliance with PCI Bus Power Management
Interface Specification Revision 1.0 (PC98)
■ Two concurrently operating wide, Ultra2 SCSI
channels
■ Up to 80 Mbytes/sec parallel SCSI transfer rates
■ Supports single-ended, low voltage differential
(LVD) SCSI and high voltage differential (HVD)
SCSI
Product Description
The ISP1280 adds dual channel, Ultra2 (Fast-40) SCSI
support to the expanding functionality of the ISP. The
product is a single-chip, highly integrated bus master,
dual-channel SCSI I/O processor for SCSI initiator and
target applications. This device interfaces the PCI bus to
two Ultra2 (Fast-40) SCSI buses and contains an onboard
RISC processor. The product is a fully autonomous device,
capable of managing multiple I/O operations and
■ SCSI initiator and target modes of operation
■ Onboard RISC processor to execute operations at
the I/O control-block level from the host memory
■ Supports PCI dual-address cycle (64-bit
addressing)
associated data transfers from start to finish without host
intervention. The ISP1280 provides power management
feature support in accordance with the PCI Bus Power
Management Interface Specification. The ISP1280 is
host-software compatible with the QLogic ISP1240 chip.
The ISP1280 block diagram is illustrated in figure 1.
ISP1280
PCI INTERFACE
HOST MEMORY
SCSI INTERFACE
DMA BUS 0
FIFO
512-BYTE
DATA FIFO
HOST SOFTWARE
DRIVER
ULTRA, WIDE
SCSI BUS 0
WCS AND
BUFFERS
SXP 0
64-BIT
PCI
BUS
IOCBS
SEQUENCERS
CTRL REGS
REQUEST
QUEUE
512-BYTE
DATA FIFO
DMA BUS 1
FIFO
128-BYTE
COMMAND FIFO
RISC I/O BUS
ULTRA, WIDE
SCSI BUS 1
WCS AND
BUFFERS
SXP 1
DMA
SEQUENCERS
CTRL REGS
CONTROL
RISC
RESPONSE
QUEUE
MAILBOX
REGISTERS
BOOT
CODE
REGISTER
FILE
CTRL/CONFIG
REGISTERS
MEMORY
INTERFACE
ALU
ADDRESS 16
DATA 16
EXTERNAL
CODE/DATA
MEMORY
FLASH
BIOS
NVRAM
Figure 1. ISP1280 Block Diagram
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ISP1280
1
QLogic Corporation
ISP Initiator and Target Firmware
The ISP1280 firmware implements a cooperative,
multitasking host adapter that provides the host system
with complete SCSI command and data transport
capabilities, thus freeing the host system from the demands
of the SCSI bus protocol. The firmware provides two
interfaces to the host system: the command interface and
the SCSI transport interface. The single-threaded
command interface facilitates debugging, configuration,
and error recovery, while the multithreaded SCSI transport
interface maximizes use of the SCSI and host buses. The
ISP1280 can switch between initiator and target modes.
Interfaces
The ISP1280 interfaces consist of the 64-bit PCI bus
interface, two SCSI interfaces, RISC interface, BIOS
PROM interface, and NVRAM interface. Pins that support
these interfaces and other chip operations are shown in
figure 3.
PCI Interface
The ISP1280 PCI interface supports the following:
■ 64-bit (address and data), intelligent bus master,
burst DMA host interface for fetching I/O control
blocks and data transfers
■ Supports PCI dual-address cycle (64-bit memory
addressing)
■ Backward compatible to 32-bit PCI
■ Triple-channel DMA controller
■ Two 512-byte data DMA FIFOs and a 128-byte
command DMA FIFO with threshold control
■ 16-bit slave mode for communication with host
■ Pipelined DMA registers for efficient scatter and
gather operations
■ 32-bitDMAtransfercounterforI/Otransferlengths
of up to four gigabytes
■ Support for subsystem ID
■ Support for flash BIOS PROM
■ Support for PCI cache commands
■ 3.3-V and 5.0-V tolerant PCI I/O buffers
Software Drivers
Windows 95/98 and Windows NT software drivers are
provided for the ISP1280. BIOS firmware is also available.
Subsystem Organization
To maximize I/O throughput and improve host and
SCSI bus utilization, the ISP1280 incorporates a
high-speed proprietary RISC processor; an intelligent
SCSIbuscontroller(SCSIexecutiveprocessor[SXP]);and
a host bus, dual-channel, first-party DMA controller. The
SCSI bus controller and the host bus DMA controller
operate independently and concurrently under the control
of the onboard RISC processor for maximum system
performance. The ISP1280 RISC interface requires
external program data memory.
The complete I/O subsystem solution including the
ISP1280 and associated supporting memory devices is
shown in figure 2.
The ISP1280 is designed to interface directly to the PCI
busandoperateasa64-bitDMAbusmaster. Thisoperation
is accomplished through a PCI bus interface unit (PBIU)
that contains an onboard DMA controller. The PBIU
generates and samples PCI control signals, generates host
memory addresses, and facilitates the transfer of data
between host memory and the onboard DMA FIFO. It also
allows the host to access the ISP1280 internal registers and
communicatewiththeonboardRISCprocessorthroughthe
PCI target mode operation.
SCSI
TARGETS
ISP1280
HOST
MEMORY
TARGET
TARGET
SCSI
16
SCSI
I/F
PCI
I/F
PCI
64
IOCB
TheISP1280onboardDMAcontrollerconsistsofthree
independentDMAchannelsthatinitiatetransactionsonthe
PCI bus and transfer data between the host memory and
DMA FIFO. The three DMA channels consist of one
command DMA channel and two data DMA channels. The
command DMA channel is used mainly by the RISC
processor for small transfers such as fetching commands
from and writing status information to the host memory
over the PCI bus. The data DMA channels transfer data
between the two SCSI buses and the PCI bus.
SCSI
P
C
I
TARGETS
DATA
TARGET
TARGET
B
U
S
SCSI
16
SCSI
I/F
RISC
CODE/DATA
MEMORY
The PBIU internally arbitrates between the data DMA
channels and the command DMA channel and alternately
services them. Each DMA channel has a set of DMA
registers that are programmed for transfers by the RISC
processor.
Figure 2. I/O Subsystem Design Using the ISP1280
2
ISP1280
83280-580-00 B
QLogic Corporation
ISP1280
ACK0-1/ACK0-1
ATN0-1/ATN0-1
FLASHCS
4
4
2
FLASH BIOS PROM
INTERFACE
SCSI BUS 0 AND 1
INTERFACE
FLASHOE
FLASHWR
PDATA7-0
4
BSY0-1/BSY0-1
CD0-1/CD0-1
8
4
4
DIFFS0/DIFFS1
11
IO0-1/IO0-1
MSG0-1/MSG0-1
REQ0-1/REQ0-1
4
ECS3-0
IF
4
4
32
4
RISC
INTERFACE
RST0-1/RST0-1
4
32
4
IOCS
SD0[15-0]/SD0[15-0]
RADDR15-0
RDATA15-0
16
SD1[15-0]/SD1[15-0]
SDP0[1-0]/SDP0[1-0]
16
RDPAR
RISCSTB
ROE
SDP1[1-0]/SDP1[1-0]
SEL0-1/SEL0-1
4
110
TRIG
WE
NVCLK
NVCS
43
NVRAM
INTERFACE
NVDATI
NVDATO
ACK64
AD63-0
BCLK
PCI BUS
INTERFACE
64
4
BGNT
BREQ
BIAS0_RES/BIAS1_RES
2
MISCELLANEOUS
BSYLED0-1
CLK
2
CBE7-0
DEVSEL
FRAME
IDSEL
8
CLKOUT
CMDCH
DATCH0/DATCH1
2
INTA
IRDY
GPIO3-0
IDENB
4
M66EN
PAR
30
NC (NO CONNECT)
PLLCNT
PAR64
PERR
PLLFILTER
PLLTD
REQ64
POD
RESET
SERR
TCK
TDI
STOP
TRDY
TDO
TEST5
TEST4-0
TMS
90
5
VDD4
VDD
12
28
POWER
AND GROUND
TRST
TSTOUT
60
VDDS5
4
VDDA
VDDSCSI
18
92
VSS
VSSA
VSSSCSI
18
174
492
Figure 3. ISP1280 Functional Signal Grouping
■ Programmable SCSI processor
SCSI Executive Processor
❒ Specialized instruction set with 16-bit
microword
❒ 384x16 internal RAM control store
The ISP1280 SXP supports the following:
■ Ultra and Ultra2 (Fast-40) SCSI synchronous data
transfer rates up to 80 Mbytes/sec
■ Asynchronous SCSI data transfer rates up to
12 Mbytes/sec
■ 32-bit, configurable SCSI transfer counter
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ISP1280
3
QLogic Corporation
■ Command, status, message in, and message out
buffers
■ Device information storage area
■ On-chip, LVD SCSI transceivers
■ Programmable active negation
RISC Processor
The ISP1280 RISC processor supports the following:
■ Execution of multiple I/O control blocks from the
host memory
■ Reduced host intervention and interrupt overhead
■ One interrupt or less per I/O operation
The SXP provides an autonomous, intelligent SCSI
interface capable of handling complete SCSI operations.
The SXP interrupts the RISC processor only to handle
higher level functions such as threaded operations or error
handling.
The onboard RISC processor enables the ISP1280 to
handlecompleteI/Otransactionswithnointerventionfrom
the host. The ISP1280 RISC processor controls the chip
interfaces; executes simultaneous, multiple input/output
control blocks (IOCB); and maintains the required thread
information for each transfer.
Packaging
The ISP1280 is available in a 492-pin plastic ballgrid
array (PBGA) package.
Windows NT and Windows 95 are trademarks or registered trademarks of Microsoft Corp.
All other brand and product names are trademarks or registered trademarks of their respective holders.
Specifications are subject to change without notice.
QLogic is a trademark of QLogic Corporation.
©October 21, 1998 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200
4
ISP1280
83280-580-00 B
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