ML610Q359 [ETC]
8-bit Microcontroller with Voice Output Function;
| 型号： | ML610Q359 |
| 厂家： | 
ETC |
| 描述： | 8-bit Microcontroller with Voice Output Function 微控制器 |
| 文件： | 总30页 (文件大小：782K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL610Q359-01
Issue Date: Jul 31, 2015
ML610Q359/ML610Q360
8-bit Microcontroller with Voice Output Function
GENERAL DESCRIPTION
Equipped with a 8-bit CPU nX-U8/100, the ML610Q359 is a high-performance 8-bit CMOS microcontroller that integrates a
wide variety of peripherals such as, 12-bit A/D converter, timer, synchronous serial port, UART, and voice output function.
The nX-U8/100 CPU is capable of executing instructions efficiently on a one-instruction-per-clock-pulse basis through parallel
processing by the 3-stage pipelined architecture.
In addition, it has an on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the
board.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system:
16-bit instructions
− Instruction set:Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations,
bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 µs (at 32.768kHz system clock)
Approx 0.125 µs (at 8MHz system clock)＠DVDD = 2.2 to 3.6V
Approx 0.250 µs (at 4MHz system clock)＠DVDD = 2.0 to 3.6V
• Internal memory
− Has 160-Kbyte flash ROM(80K × 16-bit) built in. (544 byte of test domain that it cannot be used is included)
− Has 3-Kbyte flash ROM built in. (area in which self rewriting is possible.512Byte×6)
− Has 2-Kbyte RAM (2048 × 8 bits) built in.
− Has 16-Mbit P2ROM built in. (only ML610Q360)
• Interrupt controller
− 2 non-maskable interrupt sources (Internal source: 1, External source: 1)
− 25 maskable interrupt sources (Internal source: 19, External source: 6)
• Time base counter
− Low-speed time base counter × 1 channel
− High-speed time base counter × 1 channel
• Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 8ch (16-bit configuration available)
1/30
FEDL610Q359-01
ML610Q359/ML610Q360
• Voice output function
− Voice synthesis method: 4-bit ADPCM2 / non-linear PCM / straight 8-bit PCM / straight 16-bit PCM
− Sampling frequency: 8/16/32 kHz; 10.7/21.3 kHz; 6.4/12.8/25.6 kHz
• D/A converter
− 12-bit D/A converter
• Speaker amplifier output power
− 0.5W(at 3.0V)
− Thermal detection circuit
− Disconnection detection circuit
• Synchronous serial port
− 2ch
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− Half-duplex × 2ch or half-duplex × 1ch + full-duplex × 1ch
− TXD / RXD
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• Successive approximation type A/D converter
− 12-bit A/D converter
− Input: 4ch (ch0-2:External input
ch3: A regulator output (VDDR) or a temperature sensor output (TEMPO)
− Conversion time: 20 µs per channel at 8MHz AVDD≧2.5V
− Conversion time: 28 µs per channel at 8MHz AVDD≧2.2V
• Temperature sensor
− Measuring range : −40°C to +85°C
• Regulator output (VDDR
)
− 1.5V±50mV(at −40°C to +85°C and when a VDDR pin is no-load)
− 1.5V / 0V / HiZ selectable
• General-purpose ports
− Non-maskable interrupt input port × 1ch
− Input-only port × 7ch
− Output-only port × 3ch (including secondary functions)
− Input/output × 29ch (including secondary functions)
• Supply voltage supervisor circuit
− Judgment accuracy: ±1.5% (Typ.)
− Judgment Voltage:
A binary to selection is possible
− This function can be used as supply voltage supervisor reset.
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FEDL610Q359-01
ML610Q359/ML610Q360
• Reset
− Reset through the RESET_N pin
− Power-on reset generation when powered on
− Reset by the watchdog timer (WDT) overflow
− Reset when oscillation stop of the low-speed clock is detected
− Voltage level supervisor reset
• Clock
− Low-speed clock (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz)
− High-speed clock
Built-in oscillation (8.192MHz), external clock
• Power management
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the
oscillation clock)
− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock stop)
• Shipment
− 64-pin TQFP
ML610Q359-xxxTB (blank product: ML610Q359-NNNTB)
ML610Q360-xxxTB (blank product: ML610Q360-NNNTB)
xxx: ROM code number
• Guaranteed operating range
− Operating temperature: −40°C to 85°C(for ML610Q359)
: −10°C to 65°C(P2ROM movment of ML610Q360)
− Operating voltage: DVDD = 2.0V to 3.6V, SPVDD = 2.2V to 3.6V, AVDD = 2.2V to 3.6V
3/30
FEDL610Q359-01
ML610Q359/ML610Q360
BLOCK DIAGRAM
Block Diagram of ML610Q359
CPU (nX-U8/100)
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
EA
Timing
Controller
ALU
SP
Program
Memory
（Flash）
BUS
Controller
Instruction
Decoder
Instruction
Register
On-Chip
ICE
160Kbyte
DVDD
DVSS
INT
2
Data-bus
SCK0*
SIN0*1
SOUT0*
SSIO
RESET_N
RESET &
TEST
TEST0
RAM
2048byte
SCK1*
SIN1*
SOUT1*
TEST1_N
XT0
XT1
INT
3
OSC
Interrupt
Controller
RXD0*,
RXD1*
RXD2*
UART
LSCLK*
OUTCLK*
INT
4
TXD0*
TXD1*
TXD2*
TBC
VDDL
VDDX
POWER
INT
8
INT
7
AVDD
AVSS
8bit Timer
INT
1
×8
NMI
INT
P00 to P05
P10
12bit-ADC
VDDR
AIN0 to AIN2
GPIO
WDT
P20 to P22
AVDD
AVSS
P30 to P37
P40 to P47
P50 to P57 *1
P60 to P63
Temperature
sensor
VDDR
INT
1
SVS
SG
AOUT
VOICECNT
SPVDD
SPVSS
SPEAKER
AMP
SG
SPIN
SPP
SPM
* : Secondary or tertiary or fourthly function
*1: It is the point with the difference in ML610Q359 and ML610Q360
Figure 1 Block Diagram of ML610Q359
4/30
FEDL610Q359-01
ML610Q359/ML610Q360
Block Diagram of ML610Q360
CPU (nX-U8/100)
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
EA
Timing
Controller
ALU
SP
Program
Memory
（Flash）
BUS
Controller
Instruction
Decoder
Instruction
Register
On-Chip
ICE
160Kbyte
DVDD
DVSS
INT
2
Data-bus
SCK0*
SIN0*
SOUT0*
SSIO
RESET_N
TEST0
RESET &
TEST
RAM
TEST1_N
2048byte
XT0
XT1
OSC
INT
3
Interrupt
Controller
LSCLK*
OUTCLK*
RXD0*,
RXD1*
RXD2*
UART
INT
4
TXD0*
TXD1*
TXD2*
TBC
VDDL
VDDX
POWER
INT
8
INT
7
AVDD
AVSS
8bit Timer
INT
1
NMI
×8
P00 to P05
P10
P20 to P22
INT
12bit-ADC
VDDR
GPIO
AIN0 to AIN２
WDT
P30 to P37
P40 to P47
AVDD
AVSS
P50 to P53 *１
TESTO3
Temperature
sensor
VDDR
to TESTO6 *1
P60 to P63
INT
1
DVDD
DVSS
SVS
SG
AOUT
VOICECNT
*1 PVPP
PSO
PSCK
PSI
* *1 P54(SIN1)
* *1 P55(SCK1)
* *1 P56(SOUT1)
*1 P57
PORT
SPVDD
SPVSS
*1 16Mbit
P2ROM
SPEAKER
AMP
PCSB
SG
SPIN
SPP
SPM
* : Secondary or tertiary or fourthly function
1
:
It is the point with the difference in ML610Q359 and ML610Q360
*
Figure 2 Block Diagram of ML610Q360
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FEDL610Q359-01
ML610Q359/ML610Q360
PIN CONFIGURATION
ML610Q359 TQFP package product
P62
P63
NMI
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AVSS
AVDD
AIN2
AIN1
AIN0
VDDR
P37
P36
P35
P34
P33
P32
P31
P30
P05
P04
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P20
P21
P22
DVSS
P00
P01
P02
P03
SG
AOUT
SPIN
SPVDD
SPVSS
*: It is the point with the difference in ML610Q359 and ML610Q360
(NC): No Connection
Figure 3 Pin Configuration of ML610Q359 Package Product
6/30
FEDL610Q359-01
ML610Q359/ML610Q360
ML610Q360 TQFP package product
P62
P63
NMI
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
AVSS
AVDD
AIN2
AIN1
AIN0
VDDR
P37
P36
P35
P34
P33
P32
P31
P30
P05
P04
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P20
P21
P22
DVSS
P00
P01
P02
P03
SG
AOUT
SPIN
SPVDD
SPVSS
*: It is the point with the difference in ML610Q359 and ML610Q360
Figure 4 Pin Configuration of ML610Q360 Package Product
7/30
FEDL610Q359-01
ML610Q359/ML610Q360
LIST OF PINS
Pin No
Primary function
Secondary function
Tertiary function
Q359
13,55
12
Q360
13,55
12
Pin name
DVSS
DVDD
I/O
Description
Pin name
I/O
Description
Pin name
I/O
Description
Negative power supply pin
Positive power supply pin
Power supply for internal
logic (internally generated)
Power supply pin for
oscillation (internally
generated)
Reference voltage
output of 1.5V
Negative power supply
pin for built-in speaker
amplifier
11
14
27
64
11
14
27
64
VDDL
VDDX
VDDR
SPVSS
Positive power supply
pin for built-in speaker
amplifier
Negative power supply pin
for
successive-approximation
type ADC/OP-amp
Positive power supply pin
for
successive-approximation
type ADC/OP-amp
High voltage power supply
pin of data to building
P2ROM
63
32
63
32
SPVDD
AVSS
31
31
8
AVDD
PVPP
3
4
39
5
3
4
39
5
TEST0
TEST1_N
TESTO2
RESET_N
I/O Input/output pin for testing
I
I
Input pin for testing
Output pin for testing
Reset input pin
Low-speed clock oscillation
pin
16
16
XT0
I
Low-speed clock oscillation
pin
LINE output
Analog input to the built-in
speaker amplifier
15
61
62
15
61
62
XT1
AOUT
SPIN
O
O
I
Reference power supply
pin of the built-in speaker
amplifier
60
60
SG
O
Positive output pin of the
built-in speaker amplifier
Negative output pin of the
built-in speaker amplifier
Successive-approximation
type ADC input
Successive-approximation
type ADC input
Successive-approximation
type ADC input
2
2
SPP
SPM
AIN0
AIN1
AIN2
O
O
I
1
1
28
29
30
28
29
30
I
I
8/30
FEDL610Q359-01
ML610Q359/ML610Q360
Pin No
Primary function
Secondary function
Tertiary function
I/O
Fourthly function
Pin
name
Pin
Pin
name
Q359
Q360
Pin name
I/O
Description
I/O
Description
Description
I/O
Description
name
Input port,
non-maskable
interrupt
51
51
NMI
I
Input port /
External
Input port /
External
56
57
56
57
P00/EXI0
P01/EXI1
I
I
Input port /
External
P02/EXI2
/ RXD0
/ RXD2
interrupt /
UART0 data
input /
58
58
I
UART2 data
input
Input port /
External
interrupt /
UART1 data
input
Input port /
External
interrupt /
Timer0,2
external clock
input
P03/EXI3
/ RXD1
59
17
59
17
I
I
P04/EXI4/
T02P0CK
Input port /
External
P05/EXI5/
T13P0CK
interrupt /
Timer1,3
external clock
input
18
18
I
High-speed
oscillation
Low-speed
clock output
high-speed
clock output
48
52
53
54
19
20
21
22
23
24
25
48
52
53
54
19
20
21
22
23
24
25
P10
I
Input port
OSC0
I
P20/
LED0
P21/
LED1
P22/
Output port /
LED drive
Output port /
LED drive
Output port /
LED drive
Input/output
port
Input/output
port
Input/output
port
Input/output
port
Input/output
port
Input/output
port
Input/output
port
O
LSCLK
O
O
OUTCLK
O
O
LED2
P30
P31
P32
P33
P34
P35
P36
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9/30
FEDL610Q359-01
ML610Q359/ML610Q360
Pin No
Primary function
Secondary function
Tertiary function
Fourthly function
Pin
name
Pin
Pin
name
Pin
name
Q359
Q360
35
I/O
Description
I/O
Description
I/O
Description
I/O
Description
name
Input/output
port
SSIO0 data
input
35
36
P40
P41
I/O
SIN0
I
SSIO0
Input/output
port
synchronous
clock
36
I/O
SCK0
I/O
input/output
SSIO0 data
output
Input/output
port
Input/output
port
Input/output
port
UART0 data
input
UART0 data
output
UART2 data
input
UART2 data
output
37
38
40
37
38
40
P42
P43
P44
I/O
I/O
I/O
RXD0
TXD0
I
SOUT0
O
I
RXD2
TXD2
I
O
O
SSIO0 data
input
SIN0
Input/output
port
SSIO0
synchronous
clock
41
41
P45
I/O
SCK0
I/O
input/output
SSIO0 data
output
Input/output
port
Input/output
port
Input/output
port
42
43
44
42
43
44
P46
P47
P50
I/O
I/O
I/O
SOUT0
O
I
SSIO1 data
input
SIN1
SSIO1
Input/output
port
synchronous
clock
input/output
SSIO1 data
output
45
45
P51
I/O
SCK1
I/O
Input/output
port
Input/output
port
UART1 data
input
UART1 data
output
46
47
46
47
P52
P53
I/O
I/O
RXD1
TXD1
I
SOUT1
O
UART2 data
output
O
TXD2
O
P54/
TEST
O3
Input/output
port
SSIO1 data
input
6
I/O
I/O
SIN1
I
SSIO1
synchronous
clock
P55/
TEST
O4
Input/output
port
33
SCK1
I/O
input/output
P56/
TEST
O5
P57/
TEST
O6
Input/output
port
SSIO1 data
output
34
7
I/O
I/O
SOUT1
O
Input/output
port
Input/output
port
Input/output
port
Input/output
port
Input/output
port
9
9
P60
P61
P62
P63
I/O
I/O
I/O
I/O
10
49
50
10
49
50
Note:
The function which has not been chosen is lost when it is chosen any of a secondary function, the Tertiary function, and the
fourthly function they are. However, when using it as an input, it is possible to read input data with a port-n data register.
10/30
FEDL610Q359-01
ML610Q359/ML610Q360
Complement: It is only ML610Q360. ML610Q359 does not correspond.
P54-P57 are connected with built-in P2ROM inside the chip, and each function exists. An external terminator name is set to
TESTO3-TESTO6. Please make the external terminator open. The content of contact with P2ROM is shown below.
The terminator of built-in P2ROM
PSO
Explanation
serial data output
It connects with P54/SIN1(tertiary functional use) inside.
serial clock input
It connects with P55/SCK1(tertiary functional use) inside.
serial data input
PSCK
PSI
It connects with P56/SOUT1(tertiary functional use) inside.
chip select input
It connects with P57(primary functional use) inside.
PCSB
11/30
FEDL610Q359-01
ML610Q359/ML610Q360
PIN DESCRIPTION
Pin name
I/O
Description
Primary/
Logic
Secondary
Power supply
DVSS
Negative power supply pin
Positive power supply pin
—
—
—
—
—
—
—
DVDD
Positive power supply pin for internal logic (internally generated)
VDDL
—
—
—
—
—
—
Connect capacitors (CL) (see Measuring Circuit 1) between this pin and
DVSS
.
Power supply pin for oscillation (internally generated).
Capacitors CX(see measuring circuit 1) are connected between this pin and
VDDX
—
—
DVSS
.
Reference voltage output.
Capacitors CR(see measuring circuit 1) are connected between this pin and
VDDR
DVSS
.
Negative power supply pin for built-in speaker amplifier
SPVSS
SPVDD
AVSS
—
—
—
—
—
—
—
—
—
—
—
—
Positive power supply pin for built-in speaker amplifier
Negative power supply pin for successive-approximation type ADC/op-amp
Positive power supply pin for successive-approximation type ADC/op-amp
AVDD
High voltage power supply pin of the data write to building P2ROM into.
Besides, fix at the VSS level.
PVPP
—
—
Test
Input/output pin for testing. Has a pull-down resistor built in.
Input pin for testing. Has a pull-up resistor built in.
Output pin for testing
TEST0
I/O
I
Positive
Negative
—
—
—
—
TEST1_N
TESTO2
—
System
Reset input pin. When this pin is set to a “L” level, the device is placed in
system reset mode and the internal circuit is initialized. If after that this pin
is set to a “H” level, program execution starts. This pin has a pull-up
resistor built in.
RESET_N
I
—
Negative
XT0
I
—
—
Positive
XT1
O
I
Negative
OSC0
LSCLK
Secondary Positive
Low-speed clock output. This function is allocated to the secondary function
of the P20 pin.
O
—
Secondary
High-speed clock output. This function is allocated to the secondary
function of the P21 pin.
OUTCLK
O
—
Secondary
General-purpose input port
P00 to P05
P10
I
I
General-purpose input ports.
Primary
Primary
Positive
Positive
General-purpose input/output ports.
Provided with a secondary function for each port. Cannot be used as ports
if their secondary functions are used.
12/30
FEDL610Q359-01
ML610Q359/ML610Q360
Primary/
Secondary/
Logic
Pin name
I/O
Description
Tertiary/
Fourthly
General-output input port
General-purpose output ports.
P20 to P22
O
Primary
Primary
Positive
Positive
Provided with a secondary function for each port. Cannot be used as ports
if their secondary functions are used.
General-purpose input/output port
General-purpose input/output ports.
P30 to P37
P40 to P47
P50 to P57
P60 to P63
UART
I/O
Provided with a secondary function for each port. Cannot be used as ports
if their secondary functions are used.
UART0 data output pin. Allocated to the secondary function of the P43 pin.
TXD0
O
I
Secondary Positive
UART0 data input pin. Allocated to the primary function of the P02 pin and
the secondary function of the P42 pin.
RXD0
Secondary
Positive
UART1 data output pin. Allocated to the secondary function of the P53 pin.
TXD1
RXD1
O
I
Secondary
Secondary
Positive
Positive
UART1 data input pin. Allocated to the primary function of the P03 pin and
the secondary function of the P52 pin.
UART0 data output pin. Allocated to the fourthly function of the P43 pin and
the fourthly function of the P53 pin.
TXD2
RXD2
O
I
Fourthly
Fourthly
Positive
Positive
UART0 data input pin. Allocated to the primary function of the P02 pin and
the fourthly function of the P42 pin.
Synchronous serial (SSIO)
Synchronous serial data input pin. Allocated to the tertiary function of the
P40 pin and the tertiary function of the P44 pin.
SIN0
I
I/O
O
Tertiary
Tertiary
Tertiary
Tertiary
Tertiary
Tertiary
Positive
—
Synchronous serial clock input/output pin. Allocated to the tertiary function
of the P41 pin and the tertiary function of the P45 pin.
SCK0
SOUT0
SIN1
Synchronous serial data output pin. Allocated to the tertiary function of the
P42 pin and the tertiary function of the P46 pin.
Positive
Positive
—
Synchronous serial data input pin. Allocated to the tertiary function of the
P50 pin and the tertiary function of the P54 pin .
I
Synchronous serial clock input/output pin. Allocated to the tertiary function
of the P51 pin and the tertiary function of the P55 pin.
SCK1
SOUT1
I/O
O
Synchronous serial data output pin. Allocated to the tertiary function of the
P52 pin and the tertiary function of the P56 pin.
Positive
External interrupt
NMI
External non-maskable interrupt input pin. The interrupt occurs on both the
rising and falling edges.
Positive/
Negative
I
I
Primary
Primary
External maskable interrupt input pins. It is possible, for each bit, to specify
whether the interrupt is enabled and select the interrupt edge by software.
Allocated to the primary function of the P00–P05 pins.
EXI0–EXI5
Positive/
Negative
13/30
FEDL610Q359-01
ML610Q359/ML610Q360
Primary/
Secondary/
Logic
Pin name
I/O
O
Description
Tertiary/
Fourthly
LED drive
LED0–LED2
Pins for LED driving. Allocated to the primary function of the P20 to P22
pins.
Positive/
Primary
Negative
Voice output function
LINE output pin.
AOUT
O
—
—
The case of built-in speaker amplifier use, connect capacitors (CAOSP
)
between this pin and the SPIN pin.
Analog input pin of the internal speaker amplifier.
Reference voltage output pin of the internal speaker amplifier.
Positive output pin of the internal speaker amplifier.
Negative output pin of the internal speaker amplifier.
SPIN
SG
I
—
—
—
—
—
—
—
—
O
O
O
SPP
SPM
Successive-approximation type A/D converter
Analog inputs to Ch0–Ch2 of the successive-approximation type A/D
converter.
AIN0–AIN2
I
—
—
14/30
FEDL610Q359-01
ML610Q359/ML610Q360
TERMINATION OF UNUSED PINS
How to Terminate Unused Pins
Pin
RESET_N
TEST0
Recommended pin termination
Open
Open
TEST1_N
TESTO2
AVDD
Open
Open
Connect to DVDD
AVSS
Connect to DVSS
AIN0 to AIN2
SPVDD
Open
Connect to DVDD
SPVSS
Connect to DVSS
PVPP
Open
AOUT
Open
SPIN
Open
SG
Open
SPP
Open
SPM
Open
P00 to P05
P10
Connect to DVDD or DVSS
Connect to DVDD or DVSS
P20 to P22
P30 to P37
P40 to P47
P50 to P57
TESTO3 to TESTO6
P60 to P63
VDDR
Open
Open
Open
Open
Open
Open
Open
Note:
For unused input ports or unused input/output ports, if the corresponding pins are configured as high-impedance inputs and left
open, the supply current may become excessively large. Therefore, it is recommended to configure those pins as either inputs
with a pull-down resistor/pull-up resistor or outputs.
15/30
FEDL610Q359-01
ML610Q359/ML610Q360
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(DVSS = AVSS = SPVSS = 0V)
Parameter
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
Power supply voltage 4
Power supply voltage 5
Power supply voltage 6
Power supply voltage 7
Input voltage
Symbol
Condition
Ta=25°C
Rating
−0.3 to +7.0
−0.3 to +7.0
−0.3 to +7.0
−0.3 to +3.6
−0.3 to +3.6
−0.3 to +3.6
−0.3 to +9.5
−0.3 to DVDD+0.3
−0.3 to DVDD+0.3
−12 to +11
−12 to +60
472
Unit
V
DVDD
AVDD
SPVDD
VDDL
Ta=25°C
V
Ta=25°C
V
Ta=25°C
V
VDDX
Ta=25°C
V
VDDR
Ta=25°C
V
TESTO2
VIN
Ta=25°C
V
Ta=25°C
V
Output voltage
VOUT
Ta=25°C
V
Output current 1
IOUT1
Port 3, 4, 5, 6 Ta=25°C
Port 2, Ta=25°C
ML610Q359 Ta=25°C
ML610Q360
―
mA
mA
mW
mW
°C
Output current 2
IOUT2
Power dissipation
PD
562
Storage temperature
TSTG
−55 to +150
Recommended Operating Conditions
(DVSS = AVSS = SPVSS = 0V)
Parameter
Symbol
TOP
Condition
Range
Unit
Operating temperature
―
―
―
−40 to +85
2.0 to 3.6
2.2 to 3.6
°C
DVDD
SPVDD
AVDD
Operating voltage
V
―
2.2 to 3.6
3.8k to 8.4M
3.8k to 4.2M
DVDD =2.2V to 3.6V
DVDD =2.0V to 3.6V
Operating frequency (CPU)
fOP
Hz
Hz
Low speed clock oscillation
frequency
fXTL
―
32.768k
Low speed clock oscillation
Capacitor externally connected to
Low speed clock oscillation pin
CDL
CGL
14
14
MC-146 (EPSON TOYOCOM)
pF
Capacitor externally connected to
VDDL pin
Capacitor externally connected to
VDDX pin
Capacitor externally connected to
VDDR pin
CL
CX
CR
―
―
―
10±30%
0.1±30%
1±30%
µF
µF
µF
Capacitor externally connected to
AOUT pin – SPIN pin
CAOSP
CSG
―
―
0.022±30%
0.1±30%
µF
µF
Capacitor externally connected to
SG pin
16/30
FEDL610Q359-01
ML610Q359/ML610Q360
Flash Memory Operating Conditions
(DVSS = AVSS = SPVSS = 0V)
Parameter
Operating temperature
Operating voltage
Symbol
TOP
DVDD
CEPD
CEPP
YDR
Condition
At write/erase
At write/erase
Data area(1024B)
Program area
―
Range
-20 to +75
2.2 to 3.6
6000
Unit
°C
V
Maximum rewrite count
Data retention period
times
years
100
10
DC Characteristics (1 of 5)
(DVDD= AVDD=SPVDD= 2.0 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
ms
s
High-speed oscillation start
time
Low-speed crystal oscillation
start time
TXTH
―
―
1
3
2
TXTL
―
―
―
typ
-2.5%
100
typ
+2.5%
―
High-speed oscillator frequency
fHPLL
PRST
LSCLK=32.768kHz
8.192M
―
Hz
1
Reset pulse width
Reset noise rejection pulse
width
Time from power-on reset to
power-up
―
―
µs
PNRST
―
―
―
0.3
10
TPOR
―
―
ms
Reset
VIL1
VIL1
PRST
RESET_N
Reset by RESET_N pin
0.9×VDD
DVDD
0.1×VDD
TPOR
Power-on reset
17/30
FEDL610Q359-01
ML610Q359/ML610Q360
DC Characteristics (2 of 5)
(DVDD=AVDD=SPVDD= 2.3 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter
Symbol
Condition
At 10kΩ load
for DVSS
Min.
Typ.
Max.
Unit
Measuring circuit
LINE amplifier output
voltage range
VAD
SPVDD×1/6
SPVDD×5/6
V
0.95 ×
SPVDD/2
57
1.05 ×
SPVDD/2
135
SG output voltage
VSG
RSG
RLSP
―
―
―
SPVDD/2
96
V
kΩ
Ω
SG output resistance
SPM, SPP output load
resistance
8
―
―
SPVDD = 3.0V,
f = 1kHz,
RSPO = 8Ω,
THD ≥ 17%
At SPIN Input
1
Speaker amplifier output
power
PSPO1
—
0.5
—
—
W
SPVDD=3.0V,
SPIN – SPM,
Gain = +6dB
Output offset voltage
between SPM and SPP with
no signal present
VOF
−30
+30
mV
With a load of 8Ω
18/30
FEDL610Q359-01
ML610Q359/ML610Q360
DC Characteristics (3 of 5)
(DVDD=AVDD=SPVDD=2.0 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Meas
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
uring
circuit
CPU: In STOP state.
Low-speed/high-speed
oscillation: stopped
Ta ≦ +50°C
Ta ≦ +85°C
―
―
0.5
0.5
2.5
8
Supply current 1
IDD1
µA
CPU: In HALT state (LTBC,
WDT: Operating*2)
High-speed oscillation:Stopped
CPU: Running at 32.768 kHz*1
High-speed oscillation: Stopped
CPU: Running at 8.192MHz
High-speed
Ta ≦ +50°C
Ta ≦ +85°C
―
―
―
1.7
1.7
16
3.5
10
25
Supply current 2
Supply current 3
Supply current 4
IDD2
IDD3
IDD4
1
DVDD =
SPVDD = 3.0V
―
4.5
10
mA
oscillation:Stopped
*1: Case when the CPU operating rate is 100% (with no HALT state)
*2 : Significant bits of BLKCON0 to BLKCON4 registers are all “1”.
Supply-voltage supervisor circuit
(DVDD=AVDD=SPVDD=2.0 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Meas
Parameter
Symbol
VSVS1
Condition
Min.
Typ.
Max.
Unit
uring
circuit
DVDD falling
DVDD rising
DVDD falling
DVDD rising
Typ.
Typ.
+1.5%
Typ.
2.05
2.13
2.25
2.33
Ta = 25°C
Ta = 25°C
-1.5%
VLS judging voltage
V
Typ.
-1.5%
1
VSVS2
ISVS
+1.5%
VLS self-consumption
current
―
―
10
―
µA
Temperature sensor
(DVDD=AVDD=SPVDD=2.0 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Meas
Parameter
Symbol
VTEMPO
Condition
Min.
Typ.
Max.
Unit
uring
circuit
0.95
―
1.3
-3.9
-4.1
1.6
―
TEMPO output voltage
Ta = 25°C
V
1
Ta=-40℃ to +25℃
Ta=+25℃ to +85℃
TEMPO temperature
inclination
mV/℃
⊿
TEMPO
―
―
Regulator output
(DVDD=AVDD=SPVDD=2.0 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Meas
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
uring
circuit
VDDR output voltage
No load
V
1
VDDR
1.45
1.5
1.55
DC Characteristics (4 of 5)
(DVDD=AVDD=SPVDD=2.0 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
19/30
FEDL610Q359-01
ML610Q359/ML610Q360
Output voltage 1
(P20 to P22)
(P30 to P37)
(P40 to P47)
(P50 to P57)
DVDD
−0.5
VOH1
VOL1
IOH1 = −0.5mA
―
―
―
V
2
3
0.5
IOL1 = +0.5mA
―
(P60 to P63)
Output voltage 2
(P20 to P22)
When LED drive
mode is selected
IOL2=+20mA
DVDD≧2.5V
VOL2
IOOH
―
―
―
―
0.5
1
出力リーク
(P20 to P22)
(P30 to P37)
(P40 to P47)
(P50 to P57)
(P60 to P63)
Input current 1
(RESET_N)
(TEST1_N)
VOH = DVDD
(in high-impedance state)
µA
VOL = DVSS
(in high-impedance state)
IOOL
IIH1
−1
―
―
―
VIH1 = DVDD
0
−1
IIL1
IIH2
IIL2
VIL1 = DVSS
−1500
2
−300
30
−20
250
−2
Input current 2
VIH2 = DVDD (when pulled down)
VIL2 = DVSS (when pulled up)
(NMI)
(P00 to P05)
(P10)
(P30 to P37)
(P40 to P47)
(P50 to P57)
−250
−30
VIH2 = DVDD
(in high-impedance state)
µA
4
IIH2Z
IIL2Z
―
―
―
1
VIL2 = DVSS
(in high-impedance state)
-1
―
(P60 to P63)
IIH3
IIL3
VIH3=DVDD
VIL3=DVSS
20
-1
300
1500
Input current 3
(TEST0)
―
―
20/30
FEDL610Q359-01
ML610Q359/ML610Q360
DC Characteristics (5 of 5)
(DVDD=AVDD=SPVDD=2.0 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Measuring
circuit
Parameter
Symbol
VIH1
Condition
Min.
Typ.
Max.
Unit
Input voltage 1
(RESET_N)
(TEST0)
0.7×
DVDD
―
―
DVDD
(TEST1_N)
(NMI)
(P00 to P05)
(P10)
(P30 to P37)
(P40 to P47)
(P50 to P57)
0.3×
DVDD
VIL1
∆VT
CIN
―
0
―
―
―
(P60 to P63)
Hysteresis width
(RESET_N)
(TEST0)
(TEST1_N)
(NMI)
(P00 to P05)
(P10)
(P30 to P37)
(P40 to P47)
(P50 to P57)
V
5
0.05×
DVDD
0.4×
DVDD
―
(P60 to P63)
Input pin capacitance
(NMI)
(P00 to P05)
(P10)
(P30 to P37)
(P40 to P47)
(P50 to P57)
f = 10kHz
Vrms = 50mV
Ta = 25°C
―
10
pF
―
(P60 to P63)
Hysteresis Width
∆VT
VDD
Input signal
VSS
VDDL
VSS
Internal signal
21/30
FEDL610Q359-01
ML610Q359/ML610Q360
Measuring Circuits
Measuring circuit 1
CGL
CDL
XT0
XT1
32.768kHz
crystal
DVDD AVDD SPVDD
VDDX VDDR SG VSS AVSSSPVSS
VDDL
CV
：10μF
A
CL
CX
：10μF
：0.1μF
：1μF
CV
CL CX CR
CSG
CR
CSG
CGL
CDL
：0.1μF
：14pF
：14pF
CPTiming
Measuring circuit 2
(*2)
VIH
(*1)
V
VIL
DVDD VDDL VDDX
AVDD SPVDDDVSS AVSS SPVSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
22/30
FEDL610Q359-01
ML610Q359/ML610Q360
Measuring circuit 3
(*2)
VIH
(*1)
A
VIL
DVDD VDDL VDDX
AVDDSPVDD DVSS AVSS SPVSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
Measuring circuit 4
(*3)
A
DVDD VDDL VDDX
AVDDSPVDD
SPVSS
DVSS AVSS
*3: Measured at the specified input pins.
Measuring circuit 5
VIH
(*1)
VIL
VDDX
DVDD VDDL
AVDDSPVDD
SPVSS
DVSS AVSS
*1: Input logic circuit to determine the specified measuring conditions.
23/30
FEDL610Q359-01
ML610Q359/ML610Q360
AC Characteristics (External Interrupt)
(DVDD=AVDD=SPVDD=2.0 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter
External interrupt disable
period
Symbol
Condition
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
Min.
2.5×
sysclk
Typ.
Max.
3.5×
sysclk
Unit
TNUL
―
µs
P00–P05
(Rising-edge interrupt)
tNUL
tNUL
tNUL
P00–P05
(Falling-edge interrupt)
NMI, P00–P05
(Both-edge interrupt)
24/30
FEDL610Q359-01
ML610Q359/ML610Q360
AC Characteristics (Synchronous Serial Port)
(DVDD=AVDD=SPVDD=2.0 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C, unless otherwise specified)
Parameter
Symbol
Condition
Min.
10
Typ.
―
Max.
―
Unit
µs
ns
High-speed oscillation stopped
During high-speed oscillation
SCK input cycle
(slave mode)
tSCYC
500
―
―
SCK output cycle
(master mode)
tSCYC
tSW
―
―
SCK(*1)
―
s
High-speed oscillation stopped
During high-speed oscillation
4
―
―
SCK(*1)
―
―
SCK(*1)
µs
SCK input pulse width
(slave mode)
200
SCK(*1)
×0.4
ns
SCK output pulse width
(master mode)
SOUT output delay time
(slave mode)
SOUT output delay time
(master mode)
―
―
―
s
tSW
tSD
tSD
×0.5
×0.6
―
―
180
ns
ns
―
―
80
SIN input setup time
(slave mode)
SIN input hold time
―
―
50
50
―
―
―
―
ns
ns
tSS
tSH
*1: Clock period selected by S0CK3–0 of the serial port 0 mode register (SIO0MOD1)
tSCYC
tSW
tSW
SCK0*
SOUT0
SIN0*
tSD
tSD
tSS
tSH
*: Indicates the tertiary function of the corresponding port.
25/30
FEDL610Q359-01
ML610Q359/ML610Q360
Electrical Characteristics of Successive Approximation Type A/D Converter
(DVDD=SPVDD=2.0 to 3.6V, AVDD=2.2 to 3.6V, DVSS=AVSS=SPVSS=0V, Ta=−40 to +85°C,
unless otherwise specified)
Parameter
Resolution
Symbol
n
Condition
Min.
―
Typ.
―
Max.
12
Unit
bit
―
2.7V≦VREF≦3.6V
2.2V≦VREF≦2.7V
2.7V≦VREF≦3.6V
2.2V≦VREF≦2.7V
−4
−6
−3
−5
−6
−6
―
―
―
―
―
―
―
―
+4
+6
+3
+5
+6
+6
5k
Integral non-linearity error
IDL
Differential non-linearity error
DNL
LSB
Zero-scale error
Full-scale error
Input impedance
VOFF
FSE
ZI
―
―
―
Ω
SACK=0 (HSCLK=3M to 4.2MHz)
2.2≦AVDD
―
―
224
160
―
―
Conversion time
tCONV
φ/CH
SACK=1 (HSCLK=3M to 8.4MHz)
2.5≦AVDD
φ: Period of high-speed clock (HSCLK)
AVDD
DVDD
VDDL
1μF
10μF
VDDX
A
0.1μF
RI≦5kΩ
AIN0
to
-
1μF
DVSS
+
AIN2
Analog input
Reference voltage
AVSS
0.47μF
26/30
FEDL610Q359-01
ML610Q359/ML610Q360
Power-on/Shutdown Sequence
When the power rise time is 10 ms or less
Upon shutdown
Upon power-on
0V
DVDD
When the power rise time is more than 10 ms
Upon shutdown
Upon power-on
90%
10 ms (min.)
DVDD
0V
0V
VIL
RESET_N
When DVDD becomes less than 2.0V, please set DVDD to 0V, and repeat a Power-on Sequence.
Please supply voltage to AVDD simultaneous with DVDD or After DVDD rises.
27/30
FEDL610Q359-01
ML610Q359/ML610Q360
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact ROHM's responsible sales person for the product name, package name, pin
number, package code and desired mounting conditions (reflow method, temperature and times).
The heat resistance (example) of this LSI is shown below. Heat resistance (θJa) changes with the size and the number of layers
of a substrate.
Example 1
（EIA/JESD51）
W/L/t=
Condition
PCB
Example 2
W/L/t=
50 / 50 / 1.6（mm）
76.2 / 114.5 / 1.6（mm）
PCB Layer
Cu thickness
2Layers
40(um)
2Layers
30(um)
Cu density
60% / 60% (Two-Sided)
Calm（0m/sec）
41.3[℃/W]
80% / 60% (Two-Sided)
Calm（0m/sec）
46.1[℃/W]
Air cooling conditions
Heat resistance（θJa）
Power consumption of Chip PMax
at OutputPower 0.5W (3.6V)
0.472[W] (ML610Q359)
0.562[W] (ML610Q360)
TjMax of this LSI is 125℃. TjMax is expressed with the following formulas.
TjMax = TaMax + θJa × PMax
28/30
FEDL610Q359-01
ML610Q359/ML610Q360
REVISION HISTORY
Page
Previous
Edition
Document No.
Date
Description
Current
Edition
FEDL610Q359-01
Jul 31, 2015
–
–
Final edition 1
29/30
FEDL610Q359-01
ML610Q359/ML610Q360
Notes
1) The information contained herein is subject to change without notice.
2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can
break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,
please take safety measures such as complying with the derating characteristics, implementing redundant and fire
prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for
any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.
3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate
the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing
circuits for mass production.
4) The technical information specified herein is intended only to show the typical functions of the Products and examples of
application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property
rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document;
therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by
third parties, arising out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,
gaming/entertainment sets) as well as the applications indicated in this document.
6) The Products specified in this document are not designed to be radiation tolerant.
7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and
consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary
communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and
power transmission systems.
8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power
control systems, and submarine repeaters.
9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the
recommended usage conditions and specifications contained herein.
10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.
However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have
no responsibility for any damages arising from any inaccuracy or misprint of such information.
11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no
responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.
12) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US
Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.
13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.
Copyright 2015 LAPIS Semiconductor Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,
Yokohama 222-8575, Japan
http://www.lapis-semi.com/en/
30/30
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