NJW1321 [ETC]
WIDE BAND VIDEO SWITCH WITH I2C BUS; 采用I2C总线宽频带视频开关
| 型号： | NJW1321 |
| 厂家： | 
ETC |
| 描述： | WIDE BAND VIDEO SWITCH WITH I2C BUS |
| 文件： | 总12页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NJW1321
WIDE BAND VIDEO SWITCH WITH I2C BUS
■ GENERAL DESCRIPTION
■ PACKAGE OUTLINE
The NJW1321 is a Wide Band Video Switch with I2C BUS.
The NJW1321 includes switch of 4-input 2-output and 6dB
amplifier. It is suitable for RGB or Y, Pb, and Pr signal because
frequency range is 100MHz.
The NJW1321 includes external logic control terminals and
external logic discernment terminals.
NJW1321FP1
The NJW1321 is suitable for PTV, DTV, PDP and other high quality
AV systems.
■ FEATURES
■ Operating Voltage
+9.0V
■ I2C BUS Interface
■ 4-input 2-output 3-Circuits
■ Wide frequency range
0dB at 100MHz typ.
-3dB at 300MHz typ.
■ Internal 6dB amplifier (Selectable Bypass or 6dB)
■ External logic discernment terminal
■ External logic control terminal
■ Selectable slave address
■ Power Save Circuit
■ Bi-CMOS Technology
■ Package Outline
QFP48
■ BLOCK DIAGRAM
Y/R IN1
Y/R IN2
Y/R IN3
Y/R IN4
6dB
6dB
Y/R OUT1
Y/R OUT2
Pb/G IN1
6dB
6dB
Pb/G OUT1
Pb/G OUT2
Pb/G IN2
Pb/G IN3
Pb/G IN4
Pr/B IN1
6dB
6dB
Pr/B OUT1
Pr/B OUT2
Pr/B IN2
Pr/B IN3
Pr/B IN4
PORT 0
PORT 1
PORT 2
ADDRESS
SDA
SCL
I2C BUS
AUX 0
AUX 1
AUX 2
AUX 3
DGND
PORT 3
V+
GND
BIAS
VREF
Ver.3
- 1 -
NJW1321
■PIN CONFIGURATION
38
25
39
48
GND
Pr IN4
V+
Y IN3
GND
Pb IN3
V+
Pr IN3
GND
Y IN2
24
15
Pb OUT2
PORT0
PORT1
Pr OUT2
V+
VREF
DGND
GND
SDA
SCL
1
14
1. V+
13. PORT2
14. ADR
25. AUX0
26. AUX1
27. Y OUT2
28. AUX2
29. AUX3
30. Pr OUT1
31. GND
37. V+
2. Pb IN2
3. GND
4. Pr IN2
5. GND
6. Y IN1
7. V+
38. Pb IN4
39. GND
40. Pr IN4
41. V+
15. SCL
16. SDA
17. GND
18. DGND
19. VREG
20. V+
42. Y IN3
43. GND
44. Pb IN3
45. V+
8. Pb IN1
9. V+
32. Pb OUT1
33. GND
21. Pr OUT2
22. PORT1
23. PORT 0
24. Pb OUT2
10. Pr IN1
11. GND
34. Y OUT1
35. V+
46. Pr IN3
47. GND
48. Y IN2
12. PORT3
36. Y IN4
- 2 -
NJW1321
■ ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
V+
PD
12.0
V
mW
°C
Power Dissipation
1875(note)
-40 to +75
-40 to +150
Topr
Tstg
Operating Temperature Range
Storage Temperature Range
°C
(Note) At on a board of EIA/JEDEC specification. (76.2 × 114.3 × 1.6mm Two layers, FR-4)
■ RECOMMENDED OPEARATING CONDITION (Ta=25°C)
PARAMETER
Operating Voltage
SYMBOL
Vopr
TEST CONDITION
MIN.
8.5
TYP. MAX. UNIT
9.0
9.5
V
■ ELECTRICAL CHARACTERISTICS (V+=9.0V, RL=10KΩ, Ta=25°C)
■VIDEO
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP. MAX. UNIT
Operating Current
Maximum Output Voltage
-
85
2.5
100
-
Icc
Vom
No signal
mA
Vp-p
f=100kHz, THD=1%
2.0
6dB Mode
Voltage Gain 1
Gv1
Gv2
Gf1
Gf2
Gf3
Gf4
6.0
6.4
0.0
0
6.8
dB
dB
dB
dB
dB
dB
Vin=100kHz, 1.0Vp-p Sin signal
Bypass Mode
Voltage Gain 2
-0.5
0.5
Vin=100kHz, 1.0Vp-p Sin signal
6dB Mode
Frequency
-
-
-
-
-
-
-
-
Characteristic 1
Frequency
Vin=100MHz / 100kHz, 1.0Vp-p Sin signal
Bypass Mode
0
Characteristic 2
Frequency
Vin=100MHz / 100kHz, 1.0Vp-p Sin signal
6dB Mode
-3.0
-3.0
Characteristic 3
Frequency
Vin=300MHz / 100kHz, 1.0Vp-p Sin signal
Bypass Mode
Characteristic 4
Vin=300MHz / 100kHz, 1.0Vp-p Sin signal
Cross talk 1
Cross talk 2
Differential Gain
Differential Phase
S/N
CTB1
CTB2
DG
DP
SNv
Vin=4.43MHz,1.0Vp-p Sin signal
Vin=50MHz,1.0Vp-p Sin signal
Vin=1.0Vp-p 10step Video signal
Vin=1.0Vp-p 10step Video signal
Vin=1.0Vp-p,100% White Video Signal
-
-
-
-
-
-60
-40
0.3
0.3
65
-50
dB
dB
%
deg
dB
-
-
-
-
■PORT, AUX
PARAMETER
SYMBOL
VPTH
TEST CONDITION
MIN.
3.5
TYP. MAX. UNIT
PORT Input Voltage H
-
5.5
V
PORT Input Voltage M
PORY Input Voltage L
VPTM
VPTL
1.4
0
-
-
2.4
0.8
V
V
AUX Output Voltage H
AUX Output Voltage M
AUX Output Voltage L
ADR Input Voltage H
ADR Input Voltage L
VAUXH
VAUXM
VAUXL
VADRH
VADRL
3.5
1.4
0
3.5
0
-
-
-
-
-
5.5
2.4
0.8
5.0
1.0
V
V
V
V
V
- 3 -
NJW1321
■ I2C BUS BLOCK CHARACTERISTICS (SDA,SCL)
PARAMETER
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
SYMBOL
VIH
MIN.
3.0
0
-
-
0
-3.0
-
4.7
4.0
4.7
4.0
4.0
0.0
250
-
TYP.
MAX.
UNIT
V
V
µA
µA
V
mA
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.0
1.5
10
10
0.4
-
100
-
-
VIL
IIH
IIL
VOL
IOL
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
Low Level Output Voltage (3mA at SDA pin)
Maximum Output Current
Maximum Clock Frequency
Data Change Minimum Waiting Time
Data Transfer Start Minimum Waiting Time
Low Level Clock Pulse Width
High Level Clock Pulse Width
Minimum Start Preparation Waiting Time
Minimum Data Hold Time
Minimum Data Preparation Time
Rise Time
Fall Time
-
-
-
3.45
-
1.0
300
-
tF
tSU:STO
-
Minimum Stop Preparation Waiting Time
4.0
I2C BUS Load Condition:
Pull up resistance 4kΩ (Connected to +5V)
Load capacitance 200pF (Connected to GND)
SDA
SCL
tBUF
tR
tF
tHD:STA
tSU:STA
tSU:STO
tHD:STA tLOW
tHD:DAT
tHIGH
tSU:DAT
Sr
P
S
- 4 -
NJW1321
■EQUIVALENT CIRCUIT
PIN No.
NAME
FUNCTION
INSIDE EQUIVALENT CIRCUIT
VOLTAGE
V+
V+
V+
6
Y IN1
Pb IN1
Pr IN1
Y IN2
8
10
48
2
Pb IN2
Pr IN2
Y IN3
4
Y,Pb,Pr Input
RGB Input
150kΩ
100Ω
4.4V
42
44
46
36
38
40
Pb IN3
Pr IN3
Y IN4
Pb IN4
Pr IN4
V+
V+
34
32
30
27
24
21
Y OUT1
Pb OUT1
Pr OUT1
Y OUT2
Y,Pb,Pr Output
RGB Output
3.0V
Pb OUT2
Pr OUT2
50Ω
V+
V+
23
22
13
12
PORT0
PORT1
PORT2
PORT3
Logic input terminal
-
66Ω
100kΩ
V+
V+
V+
1kΩ
25
26
28
29
AUX0
AUX1
AUX2
AUX3
0V
Auxiliary 3 values voltage
output terminal
66Ω
1.9V
5.0V
- 5 -
NJW1321
PIN No.
NAME
FUNCTION
INSIDE EQUIVALENT CIRCUIT
VOLTAGE
V+
V+
VREF
Slave address
setting terminal
14
ADR
-
66Ω
15
16
SCL
SDA
I2C clock terminal
I2C data terminal
-
4kΩ
V+
V+
V+
66Ω
Reference voltage
terminal
19
VREF
4.8V
48kΩ
1
7
9
20
35
37
41
45
V+
Supply voltage terminal
-
3
5
11
17
31
33
39
43
47
GND
Ground terminal
Ground terminal
-
-
18
DGND
- 6 -
NJW1321
■ DEFINITION OF I2C REGISTER
♦ I2C BUS FORMAT
MSB
LSB
MSB
LSB
MSB
LSB
Slave Address
S
1bit
A
1bit
Data
8bit
A
1bit
Data
8bit
A
P
8bit
1bit 1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
♦ SLAVE ADDRESS
R/W: Set the Write Mode or Read Mode.
ADR : Set the Slave Address by “ADR” terminal.
Slave Address
Hex
MSB
LSB
-
-
-
1
0
0
0
0
0
ADR
R/W
■ R/W = 0 : Write Mode, ADR = 0/1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
0
94(h)
96(h)
-
■ R/W = 1 : Read Mode, ADR = 0/1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
1
1
95(h)
97(h)
♦ CONTROL REGISTER TABLE
< Write Mode >
BIT
No.
D4
D3
D3
D2
D2
D1
OUT2
D0
D0
D7
D6
D5
Data1
Data2
PS1
PS2
OUT1
AUX0
AUX1
AUX2
AUX3
< Read Mode >
BIT
BIT
No.
D4
D1
D7
D6
D5
Data
PORT0
PORT1
PORT2
PORT3
♦ CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
No.
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
D7
0
0
D6
0
0
D5
0
0
Data1
Data2
- 7 -
NJW1321
!INSTRUCTION CODE
♦ POWER SAVE, OUTPUT SETTING
BIT
No.
D4
D3
D2
D1
D0
D7
D6
D5
Data1
PS1
PS2
OUT1
OUT2
•PS1, PS2: Power Save Setting
Power Save D7
D6
0
1
0
1
OUT1 ON
OUT2 ON
OUT2 OFF
OUT2 ON
0
0
1
1
OUT1 ON
OUT1 OFF
OUT1 OFF OUT2 OFF
ON: Power Save OFF, OFF: Power Save ON (Mute)
•OUT1: Output 1 Setting
D4
0
1
0
1
Output 1
PbIN1
PbIN2
PbIN3
PbIN4
D5
0
0
1
1
Gain
6dB
0dB
D3
0
1
YIN1
YIN2
YIN3
YIN4
PrIN1
PrIN2
PrIN3
PrIN4
•OUT2: Output 2 Setting
D1
0
1
0
1
Gain
6dB
0dB
D0
0
1
Output 2
D2
0
0
1
1
YIN1
YIN2
YIN3
YIN4
PbIN1
PbIN2
PbIN3
PbIN4
PrIN1
PrIN2
PrIN3
PrIN4
- 8 -
NJW1321
♦ AUX: AUXILIARY SETTING
BIT
No.
D4
D3
D2
D1
D0
D7
D6
D5
Data2
AUX0
D7
0
0
1
AUX1
AUX2
AUX3
AUX0
D6
0
1
L
M
H
1
AUX1
D5
0
0
D4
0
1
L
M
H
1
1
AUX2
D3
0
0
D2
0
1
L
M
H
1
1
AUX3
D1
0
0
D0
0
1
L
M
H
1
1
♦ PORT: PORT SETTING
BIT
No.
D7
D4
D3
D2
D1
D0
D6
D5
Data
PORT0
PORT1
PORT2
PORT3
PORT0
OPEN
D7
0
D6
0
L
M
H
0
0
1
0
1
1
PORT1
OPEN
D5
0
D4
0
L
M
H
0
0
1
0
1
1
PORT2
OPEN
D3
0
D2
0
L
M
H
0
0
1
0
1
1
PORT3
OPEN
D1
0
D0
0
L
M
H
0
0
1
0
1
1
- 9 -
NJW1321
■TEST CIRCUIT
Pb IN4
Y IN4
Pb OUT1
Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 AUX0
Y OUT1
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
10kΩ
50Ω/75Ω
50Ω/75Ω
+
+
+
+
+
+
0.1uF
0.1uF
0.1uF
0.1uF
1uF
10uF
10uF
10uF
10uF
1uF
0.1uF
0.1uF
38
39
37
36
35
34
33
32
31
30
29
28
27
26
25
24
+
10uF
0.1uF
PORT0
Pb OUT2
10kΩ
Pr IN4
1uF
+
40
41
42
43
44
45
46
47
48
23
22
21
20
19
18
17
16
15
0.1uF
50Ω/75Ω
PORT1
10uF
Y IN3
1uF
+
+
Pr OUT2
0.1uF
10kΩ
0.1uF
50Ω/75Ω
NJW1321
Pb IN3
1uF
+
+
1uF
0.1uF
50Ω/75Ω
Pr IN3
1uF
+
0.1uF
50Ω/75Ω
SDA
SCL
Y IN2
1uF
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.1uF
50Ω/75Ω
+
+
+
+
+
1uF
0.1uF
1uF
0.1uF
1uF
1uF
1uF
0.1uF
0.1uF
0.1uF
PORT3 PORT2 ADR
Pb IN2
50Ω/75Ω
Pr IN2
50Ω/75Ω
Y IN1
50Ω/75Ω
Pb IN1
50Ω/75Ω
Pr IN1
50Ω/75Ω
V+
+
100uF 0.1uF
- 10 -
NJW1321
■APPLICATION CIRCUIT
Pb IN4
Y IN4
Pb OUT1
Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 AUX0
Y OUT1
75Ω
75Ω
10kΩ
10kΩ
10kΩ
10kΩ
+
+
+
+
+
+
0.1uF
0.1uF
0.1uF
0.1uF
1uF
10uF
10uF
10uF
10uF
1uF
0.1uF
0.1uF
38
39
37
36
35
34
33
32
31
30
29
28
27
26
25
24
+
10uF
0.1uF
PORT0
Pb OUT2
Pr IN4
1uF
+
40
41
42
43
44
45
46
47
48
23
22
21
20
19
18
17
16
15
75Ω
0.1uF
PORT1
10uF
Y IN3
1uF
+
+
Pr OUT2
0.1uF
75Ω
0.1uF
NJW1321
Pb IN3
1uF
+
+
1uF
75Ω
0.1uF
Pr IN3
1uF
+
75Ω
0.1uF
SDA
SCL
Y IN2
1uF
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
75Ω
0.1uF
+
+
+
+
+
1uF
0.1uF
1uF
0.1uF
1uF
1uF
1uF
0.1uF
75Ω
0.1uF
75Ω
0.1uF
75Ω
PORT3 PORT2 ADR
75Ω
75Ω
Pb IN2
Pr IN2
Y IN1
Pb IN1
Pr IN1
V+
+
100uF 0.1uF
- 11 -
NJW1321
■TYPICAL CHARACTERISTICS
Voltege Gain vs. Frequency
10
0
-10
-20
-30
-40
0dB
6dB
106
107
108
Frequency[Hz]
■NOTE
Please all connect V+ terminal and GND terminal.
When the power supply voltage is not impressing, please do not impress voltage to the ADR terminal.
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
- 12 -
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