NT6868CH [ETC]
Keyboard Controller; 键盘控制器
| 型号： | NT6868CH |
| 厂家： | 
ETC |
| 描述： | Keyboard Controller |
| 文件： | 总15页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NT6868C
Keyboard Controller
Features
n Built-in 6502 8-bit CPU
n 2 MHz CPU operation frequency
n 4K bytes of ROM
n Mask optional for built-in RC oscillator with an
external resistor or external ceramic resonator
applied
n 128 bytes of SRAM
n One 8-bit programmable base timer with 1 - 256 msec
interval
n Mask optional for DATA/CLK driving capability
n Watch-dog timer
n Built-in power-on reset
n 29 programmable bi-directional I/O pins
n 3 LED direct sink pins with internal serial resistors
n Built-in low voltage reset
n CMOS technology for low power consumption
n Available in 40 pin DIP package and 40 pad CHIP
FORM
General Description
NT6868C is a single chip micro-controller for keyboard
applications. It incorporates a 6502 8-bit CPU core, 4K
bytes of ROM and 128 bytes of RAM used as working
RAM and stack area. It also includes 29 programmable
bi-directional I/O pins and one 8-bit pre-loadable base
timer.
Additionally, it includes a built-in low voltage reset, a
4MHz RC oscillator that only requires an externally
applied or a 4MHz ceramic resonator, and a watch-dog
timer that has a resistor preventing system standstill.
Pin Configuration
Pad Configuration
P
1
7
P
1
6
P
1
5
P
1
4
P
1
3
P
1
2
P
1
1
P
1
0
P
0
7
P
0
6
GND
NC
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OSCI
26
25
24
23
22
21
20
19
18
17
16
P05
2
R/OSCO
DATA
CLK
P30
3
V
DD
15
14
P04
P03
4
LED2
LED1
LED0
P27
P20
27
5
P21
P22
28
29
13
12
P02
P01
P31
6
P32
7
P33
8
P26
P23
P24
30
31
11
10
P00
P34
9
P25
NT6868CH
RESET
P00
10
11
12
13
14
15
16
17
18
19
20
P24
P23
P22
P21
RESET
P25
P26
32
33
9
8
P34
P33
P01
P02
P03
P20
P17
P16
P27
34
35
7
P32
P04
LED0
P05
P06
P07
P10
P15
P14
P13
P12
37
38
39
40
1
LED1
36
P31
2
3
4
5
6
O
S
C
I
G
N
D
N
C
D
A
T
A
L
E
D
2
V
D
D
R
/
O
S
C
O
C
L
K
P
3
0
P11
1
V2.0
NT6868C
Block Diagram
CLK
4K BYTES
ROM
TIMING GENERATOR
(RC OSC/Ceramic Resonator: 4MHz)
DATA
LED0
LED1
LED2
128 BYTES
SRAM + STACK
6502
CPU
I/O PORTS
P00 - P07
P10 - P17
WATCH DOG
TIMER
INT. CONTROLLER
P20 - P27
P30 - P34
RESET
VDD
POWER-ON RESET/
LOW VOLTAGE RESET
BASE TIMER
GND
Pin and Pad Descriptions
Pin No.
Pad No.
Designation
GND
I/O
P
Description
1
2
3
4
1
2
3
4
Ground pin
NC
-
No connection, recommended to connect VDD or floating
I/O, 10KW pull-up resistor for communication
I/O, 10KW pull-up resistor for communication
Bi-directional I/O pins
DATA
CLK
I/O
I/O
I/O
5 - 9,
11 - 34
5 - 9,
11 - 34
P30 - P34,
P00 - P27
10
10
I
RESET
RESET signal input pin with internal pull-up resistor; Active low
LED direct sink pins
35 - 37
35 - 37
LED0 -
LED2
O
38
39
38
39
P
I
Power supply
VDD
R/OSCO
47KW resistor connected for RC OSC or 4MHz ceramic resonator
connection
40
40
OSCI
-
No connection for RC OSC connection; for 4MHz ceramic resonator
* Under the constraint of the maximum frequency variation, (DF/F)max, £ ±1%, code 3, 7 (ceramic resonator option) must
be selected while pins 39 and 40 are connected to a ceramic resonator. If (DF/F)max, £ ±10%, code 1, 5 (RC OSC option),
then it is recommended to be selected. Also, connect pin 39 a 47KW resistor with, £ ±1% accuracy to VDD while pin 40 is
floating.
2
NT6868C
Functional Description
6502 CPU
6502 is an 8-bit CPU. Please refer to 6502 data sheet for more details.
7
7
7
0
0
0
0
0
ACCUMULATOR A
INDEX REGISTER X
INDEX REGISTER Y
0000
009F
SRAM
STACK PTR
UNUSED
00C0
00CF
SYSTEM REGISTERS
15
UNUSED
PROGRAM COUNTER PC
7
EC00
S
STACK POINTER SP
STATUS REGISTER P
7
0
USER ROM
S
V
B
D
I
Z
C
FFFA
FFFB
FFFC
FFFD
FFFE
FFFF
NMI-L
NMI-H
RST-L
RST-H
IRQ-L
IRQ-H
CARRY
NMI VECTOR
ZERO
INTERRUPT MASK
DECIMAL MODE
BREAK
OVERFOLW
SIGN
IRQ VECTOR
Figure 1. 6502 CPU Registers and Status Flags
Figure 2. NT6868C Memory Map
3
NT6868C
System Reserved Registers
Address Register
Bit7
BT7
-
Bit6
BT6
-
Bit5
BT5
-
Bit4
BT4
-
Bit3
BT3
-
Bit2
BT2
-
Bit1
BT1
-
Bit0
R/W
W
$00C0
$00C1
BT
BT0
TCON
W
ENBT
$00C2
$00C3
$00C4
$00C5
$00C6
$00C7
$00C8
$00C9
$00CA
$00CB
$00CC
$00CD
$00CE
$00CF
CLRIRQX
PORT0
PORT1
PORT2
PORT3
CLK
-
-
-
-
-
-
-
CLRIRQTMR
W
RW
RW
RW
RW
RW
RW
W
PD07
PD06
PD05
PD04
PD03
PD02
PD01
PD00
PD10
PD20
PD30
CLK
DATA
LED0
1
PD17
PD16
PD15
PD14
PD13
PD12
PD11
PD27
PD26
PD25
PD24
PD23
PD22
PD21
-
-
-
-
-
-
PD34
PD33
PD32
PD31
-
-
-
-
DATA
LED
-
-
-
-
-
-
-
-
-
-
-
-
LED2
LED1
CLRWDT
X
0
X
X
X
X
X
1
X
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
X
0
X
X
X
X
X
1
0
W
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
- : no effect
X : access not allowed
4K X 8 ROM
Power-On Reset
The built-in ROM program code, executed by the 6502
CPU, has a capacity of 4K X 8 bits and is addressed
from F000H to FFFFH.
The built-in power-on reset circuit can generate a 150ms
pulse to reset the entire chip. The beginning of the
150ms pulse occurs at 60% of VDD when powered on.
128 X 8 SRAM
The built-in SRAM is used for general purpose data
memory and for the stack area. SRAM is addressed from
0000H to 007FH. The user can allocate stack area in the
SRAM by setting the stack pointer register (S). Since
6502C’ s default stack pointer is 01FFH, it must be
mapped to 007FH. Mapping from 01XX to 00XX is done
internally by setting the S register to 7FH via software
programming.
power
VDD
60%
The start of 150ms pulse
t
For example :
LDX
TXS
#$7F
4
NT6868C
Timing Generation
This block generates the system timing and control
signal supplied to the CPU and on-chip peripherals.
There are two types of system clock sources: a built-in
RC oscillator or an external ceramic resonator. Both of
them are mask optional and generate a 4MHz system
clock. They also generate 2MHz for the CPU, and 1 MHz
for the base timer. The following shows the relationship
of code type number with oscillation type.
The following table provides the relationship between
the external resistor and the RC OSC frequency. (This is
for reference only)
External Resistor (K
W
)
RC OSC Frequency (MHz)
39
43
47
56
4.7
4.44
4
Oscillator
RC OSC
Code Number
3.68
1, 5
3, 7
External Resistor
Base Timer
The base timer is an 8-bit counter with a 1MHz clock source. The base timer can be enabled/disabled by the CPU. After a
reset, the base timer is disabled and cleared. The base timer can be preset by writing BT7 - BT0 to the BT register at any
time. When enabled, the base timer starts counting from the preset value. When the value reaches FFH, it generates a
timer interrupt only if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap
around and begin counting at 00H. The timer interval can be programmed from 1 - 256 msec. The base timer can be
enabled by writing a '0' to ' ENBT' in the TCON (Timer Control) register. The ENBT is a level trigger.
Base timer structure:
8-Bit timer
TMRINT
1ms
BT7
BT6
BT5
BT4
BT2
BT2
BT1
BT0
BT Pre-loaded Data:
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00C0
BT
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
(W)
Timer Control Register:
$00C1
TCON
-
-
-
-
-
-
-
(W)
ENBT
INT. Controller
When a BASE TIMER overflow occurs, it will set the IRQTMR flag. The IRQTMR flag cannot be directly accessed by the
software. Once set by an interrupt source, it remains HIGH unless cleared by writing '1' to the corresponding bit in
CLRIRQX ($00C2H). This register is cleared to '0' on initialization by a system reset.
When an interrupt occurs, the CPU will jump to $FFFEH & $FFFFH to execute the interrupt service routine. When a BASE
TIMER interrupt occurs and enters the interrupt service routine, the IRQTMR flag must be cleared by the software.
Interrupt Control Register:
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00C2
CLRIRQX
-
-
-
-
-
-
-
CLRIRQTMR
(W)
5
NT6868C
I/O Ports
The NT6868C has 31 pins dedicated to input and output. These pins are grouped into 6 ports as follows:
PORT 0 (P00 - P07):
Port 0 is an 8-bit bi-directional CMOS I/O port that is internally pulled HIGH by PMOS. Each pin of port 0 can be bit
programmed as an input or output pin under the software control. When programmed as output, data is latched to the port
data register and output to the pin. Port 0 pins with ''1'' written to them are pulled HIGH by the internal PMOS pull-ups, and
are used as input in that state. These input signals can then be read. The port output will be HIGH after reset.
PORT 1 ( P10 - P17 ) : These functions are the same as PORT 0.
PORT 2 ( P20 - P27)
: These functions s are the same as PORT 0.
PORT 3 ( P30 - P34) : These functions are the same as PORT 0.
CLK & DATA
: These two pins have the same structure as I/O ports.
PORT Registers:
Addr.
$00C3
$00C4
$00C5
$00C6
$00C7
$00C8
Bit
7
6
5
4
3
2
1
0
R/W
(RW)
(RW)
(RW)
(RW)
(RW)
(RW)
PORT0
PORT1
PORT2
PORT3
CLK
PD07
PD06
PD05
PD04
PD14
PD24
PD34
-
PD03
PD13
PD23
PD33
-
PD02
PD12
PD22
PD32
-
PD01
PD11
PD21
PD31
-
PD00
PD10
PD20
PD30
CLK
PD17
PD16
PD15
PD27
PD26
PD25
-
-
-
-
-
-
-
-
-
DATA
-
-
-
-
DATA
VDD
Latch
WREN
Weak PMOS
L
IO
Q
DB
D
SD
RST
RDENB
IO Port Structure
6
NT6868C
LED Port
There are 3 LED direct sink pins which require no external serial resistors. The address is mapped to address $00C9.
Addr.
Bit
7
6
5
4
3
2
1
0
R/W
$00C9
LED
-
-
-
-
-
LED2
LED1
LED0
(W)
VDD
LED [ 0 ]
WREN
WREN
L
L
LED [ 1:2 ]
Q
Q
DB
DB
D
D
SD
SD
RST
RST
LED0 Port Structure
LED1, LED2 Port Structures
Watch-Dog Timer
NT6868C implements a watch-dog timer, which protects programs against system standstill. The clock of the watch-dog
timer is derived from the on-chip RC oscillator. The watch-dog timer interval is about 0.175 of a second. The timer must
be cleared within every 0.175 second during normal operation; otherwise, it will overflow and cause a system reset. The
watch-dog timer is cleared and enabled after a system reset. It cannot be disabled by the software. The user can clear the
watch-dog timer by writing #55H to CLRWDT ($00CAH) register.
For example:
LDA
STA
#$55
$00CA
Addr.
$00CA
Bit
7
6
5
4
3
2
1
0
R/W
CLRWDT
0
1
0
1
0
1
0
1
(W)
Low Voltage Reset (LVR) Circuit
The NT6868C will check on the voltage level of the power supply. When the voltage level of power supply is below a
threshold of 3.0V (Typical), the LVRC will issue a reset output to the chip until the power voltage level is above a threshold
voltage of 3.0V (Typical) again. As soon as the power voltage reaches 3.0V (Typical), the entire chip will be reset for about
150ms.
RESET
NT6868C can also be externally reset through the RESET pin. A reset is initiated when the signal at the RESET pin is
held LOW for at least 10 system clocks. As soon as the RESET signal goes high, the NT6868C begins to reset for about
150ms. The following shows the definition of the RESET input at LOW pulse width.
V
DD
VDD
20%VDD
20%VDD
Trstb
7
NT6868C
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Supply Voltage . . . . . . . . . . . . . . -0.3V to +7.0V
Input/Output Voltage . . . . . . GND -0.2V to VDD + 0.2V
Operating Ambient Temperature . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . -55°C to +125°C
Operating Voltage (VDD) . . . . . . . . . .+4.5V to 5.5V
DC Electrical Characteristics(VDD = 5V, GND = 0V, TA = 25°C, FOSC = 4MHz, unless otherwise specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
mA
V
Conditions
No load
Power Supply Current
20
ICC
Input High Voltage
2
V
IH
Input Low Voltage
0.8
V
V
IL
Output High Voltage (Port 0, 1, 2, 3)
Output High Voltage (CLK, DATA)
Output High Voltage (CLK, DATA)
Output Low Voltage (PORT 0, 1, 2)
Output Low Voltage (PORT 3)
Output Low Voltage (CLK, DATA)
Initial Frequency Variation 1
2.4
2.4
2.4
V
VOH1
VOH2
VOH3
VOL1
VOL2
VOL3
DF/F
IOH = -100mA
V
IOH = -400mA, Note 1
IOH = -800mA, Note 2
IOL = 4mA
V
0.4
0.4
V
V
IOL = 5mA
0.4
V
IOL = 10mA
+/-10
%
For RC OSC option
only; By Lots
DF/F
Frequency Variation 2
+/-1
17
%
For ceramic resonator
option only; By Lots
LED Sink Current (LED 0, 1, 2)
Low Voltage Reset Threshold
Power-on Reset Time
10
14
3.0
mA
V
ILED
VLVR
TPOR
TRSTB
RPH
VOL = 3.2V
120
2.5
150
180
ms
ms
10 system clocks
RESET Input Low Pulse Width
RESET Pull High Resistor
220
KW
Note 1: There are 2 types of DATA/CLK driving capabilities. This condition of VOH2 is the same as the specification of
NT6868A. Under this condition, the user can select mask option 1 or 3.
Note 2: The driving capability of DATA/CLK is higher than VOH2. Under this condition, the user can select mask option 5 or
7.
8
NT6868C
Application Circuit I (for reference only)
V
DD
4.7 - 10mf
V
DD
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30
P31
VDD
GND
LED0
LED1
Scroll Lock
Num Lock
Caps Lock
0.1mf
LED2
RESET
Optional
NT6868C
DATA
CLK
KBD DATA
KBD CLOCK
P20
P21
P22
P23
P24
P25
P26
P27
V
DD
R/OSCO
47K (System clock can be decreased
by increasing the resistance)
R0
R1
R2
R3
R4
R5
R6
(L)
R7
(R)
S0
Pause
F5
Ctrl
Ctrl
~
,
!
1
S1
S2
S3
Q
A
Esc
Z
K131
Tab
Caps
(K45)
@
2
W
E
Lock
S
D
Macro
X
C
K132
K133
F1
F2
#
3
F3
F4
%
5
$
4
S4
S5
R
U
T
Y
F
J
G
H
V
B
N
^
6
&
7
M
}
]
<
,
+
=
*
8
S6
S7
I
K
L
F6
K56
>
.
(
9
O
F7
APP
F8
-
{
[
:
;
"
'
|
?
/
)
0
S8
S9
P
\(K42)
Scroll
Lock
(L)
Alt
(R)
Alt
Print
Screen
Back
|
S10
K14
Space
\(K29)
F11
Enter
F12
F10
F9
7
4
1
Num
Lock
S11
S12
Home
End
2
Space
Delete
Insert
8
0
Ins
5
6
/
9
3
.
Page
Up
Page
Down
S13
S14
S15
S16
S17
PgUp
PgDn
(R)
Del
*
-
+
K107
(L)
Enter
(R)
Home
End
Shift
Shift
WINL
WINR
9
NT6868C
Application Circuit II (for reference only)
VDD
4.7 - 10mf
VDD
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P30
P31
VDD
GND
LED0
LED1
LED2
Scroll Lock
Num Lock
Caps Lock
0.1mf
RESET
Optional
NT6868C
KBD
DATA
DATA
CLK
KBD
CLOCK
P20
P21
P22
P23
P24
P25
P26
P27
R/OSCO
OSCI
4MHz
Ceramic Resonator
R0
R1
R2
R3
R4
R5
R6
R7
F5
(R)
(L)
Ctrl
S0
S1
S2
S3
Pause
Q
Ctrl
~
,
!
1
A
Esc
Z
K131
Tab
Caps
(K45)
@
2
W
E
Lock
S
D
Macro
X
C
V
K132
K133
F1
#
3
F3
F4
F2
%
5
$
4
S4
S5
R
U
T
Y
F
J
G
H
B
N
^
6
&
7
M
}
]
<
,
+
=
*
8
S6
S7
I
K
L
F6
K56
>
.
(
9
O
F7
APP
F8
{
[
:
;
"
'
|
?
/
)
0
S8
S9
P
\(K42)
-
Scroll
Lock
(L)
Alt
(R)
Alt
Print
Screen
Back
|
S10
K14
Space
\(K29)
F11
Enter
Num
Lock
F12
F10
F9
7
4
1
S11
S12
Home
End
Space
Delete
Insert
8
2
0
5
6
Ins
/
9
3
.
Page
Up
Page
Down
S13
S14
S15
S16
S17
PgUp
PgDn
Del
*
-
(R)
+
K107
(L)
Enter
(R)
Home
End
Shift
Shift
WINL
WINR
10
NT6868C
Application Circuit For Windows 2000 Standard Code
47K
S0
R_OSC
LED 0
P15
S1
Scroll Lock
P30
S2
S3
P31
P00
P01
P02
P03
.1uF
S4
Num Lock
Caps Lock
S5
LED 1
LED 2
S6
S7
P04
P13
S8
S9
P14
S10
S11
S12
S13
S14
S15
S16
S17
S18
P12
P10
P07
P06
P05
P11
P16
P17
P32
VDD
NT6868A/C
VDD
10uF
GND
GND
R0
R1
R2
R3
R4
R5
R6
R7
P20
P21
P22
DATA
DATA
P23
CLOCK
P24
P25
CLOCK
RESET
P26
P27
10
0.1uF
11
NT6868C
Key Matrix definition for Windows 2000 Standard Code
Power
Sleep
Pause
R-Ctrl
Wake Up
L-Ctrl
F5
126
163
164
64
46
47
48
49
52
53
54
42
165
58
1
116
2
S0
S1
Q
W
E
R
U
I
Tab
A
S
D
F
J
Esc
Z
X
C
V
M
(K131)
!
~
`
17
18
19
20
23
24
25
26
16
31
32
33
34
37
38
39
40
110
131
1
Caps Lock
(K45)
F4
(K132)
F1
@
2
30
45
132
112
113
6
3
S2
F3
(K133)
F2
#
3
114
115
133
4
S3
T
G
H
B
N
%
5
$
4
21
35
50
51
56
5
S4
Y
^
&
7
22
36
7
8
6
S5
}
K
L
F6
<
,
(K56)
App
+
=
*
28
117
13
119
12
9
]
8
S6
O
P
F7
>
.
F8
(
118
162
55
10
11
124
121
9
S7
{
:
;
"
'
|
\
?
/
_
-
)
27
41
60
[
0
S8
Scroll Lock
L-Alt
R-Alt
Print
Screen
125
62
S9
(K14)
Back Space
|
\
F11
Enter
F12
F9
F10
14
15
29
(101) 122
43
123
84
120
S10
S11
S12
S13
S14
S15
S16
7
4
1
Space
Num Lock
Delete
Power
91 (Home)
92
(
)
)
93 (End)
61
90
76
163
8
5
2
0
/
Insert
Sleep
96
(
)
97 (Num)
98
(
)
99
(Ins)
95 (Num)
89
75
164
9
6
3
.
*
-
Page Up
Page Down
101(Page Up) 102
(
103(Page Dn) 104 (Del)
100 (Num)
105 (Num)
85
86
+
(K107)
Enter
Home
End
Media
Next
106 (Num)
107
108 (Num)
83
79
80
81
180
Media
Previous
181
Media Stop
182
MediaPlay
183
Media Mute
184
Wake Up
L-Shift
R-Shift
Volume +
165
44
57
185
WWW Mail
187
WWW
Search
WWW
Home
L-Win
WWW Back
190
Volume -
160
186
188
189
WWW
Forward
191
WWW
Refresh
193
WWW
Bookmark
194
WWW Stop
192
R-Win
Kor_L
Kor_R
161
134
135
S17
S18
My
Computer
Media
Select
Calculator
195
196
197
12
NT6868C
Bonding Diagram
P
1
P
1
P
1
P
1
P
1
P
1
P
1
P
1
P
0
P
0
7
6
5
4
3
2
1
0
7
6
26
25
24
23
22
21
20
19
18
17
16
15
P05
P04
NT6868CH
P20
P21
P22
P23
27
28
29
30
14
13
12
11
P03
P02
P01
Y
P00
(0, 0)
1752.6m m
X
P24
P25
31
32
33
34
35
10
9
RESET
P34
P26
8
P33
P27
7
P32
LED0
37
38
39
40
1
LED1
36
2
3
4
5
6
P31
O
S
C
I
G
N
D
N
C
D
A
T
A
L
E
D
V
D
D
R
/
O
S
C
L
K
P
3
0
2
C
O
1930.4 m m
*Substrate Connect to Gnd
unit: mm
Pad No.
Designation
X
Y
Pad No.
Designation
X
Y
1
2
3
4
5
6
7
8
9
GND
NC
-26.70
103.30
233.30
497.55
623.30
752.55
765.20
765.20
765.20
-680.90
-743.05
-735.35
-743.05
-735.35
-735.95
-447.35
-317.35
-187.35
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
17.50
-112.50
-242.50
-372.50
-502.50
-645.00
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-765.55
-546.70
-416.70
-286.70
-156.70
734.15
734.15
734.15
734.15
734.15
734.15
576.30
434.30
304.30
174.15
44.00
DATA
CLK
P30
P31
P32
P33
P34
10
11
12
13
14
15
16
17
18
19
20
RESET
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
765.20
765.20
765.20
765.20
765.20
765.20
765.20
537.50
407.50
277.50
147.50
-57.35
72.65
-86.00
202.65
332.65
462.65
592.65
735.15
734.15
734.15
734.15
734.15
-216.00
-346.00
-476.00
-622.10
-632.30
-617.30
-617.30
-617.30
P27
LED0
LED1
LED2
VDD
R/OSCO
OSCI
13
NT6868C
Ordering Information
Part No.
NT6868CH
NT6868C
Package
CHIP FORM
40L DIP
Code Type No.
1XXXX
Oscillation Type
Built-in RC OSC
Data/Clk Driving capacitance
VOH2
VOH2
VOH3
VOH3
3XXXX
Ceramic Resonator
Built-in RC OSC
Ceramic Resonator
5XXXX
7XXXX
14
NT6868C
Package Information
DIP 40L Outline Dimensions
unit: inches/mm
D
40
21
1
20
E
S
Base Plane
Seating Plane
B
e
A
a
e1
B1
Symbol
Dimensions in inches
0.210 Max.
Dimensions in mm
5.33 Max.
A
A1
A2
0.010 Min.
0.25 Min.
0.155±0.010
3.94±0.25
B
B1
C
0.018 +0.004
-0.002
0.46 +0.10
-0.05
0.050 +0.004
-0.002
1.27 +0.10
-0.05
0.010 +0.004
-0.002
0.25 +0.10
-0.05
D
E
2.055 Typ. (2.075 Max.)
0.600±0.010
52.20 Typ. (52.71 Max.)
15.24±0.25
E1
e1
L
0.550 Typ. (0.562 Max.)
0.100±0.010
13.97 Typ. (14.27 Max.)
2.54±0.25
0.130±0.010
3.30±0.25
a
0° ~ 15°
0° ~ 15°
eA
S
0.655±0.035
16.64±0.89
0.093 Max.
2.36 Max.
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension S includes end flash.
15
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