NT68F62U [ETC]
8-Bit Microcontroller for Monitor (32K Flash MTP Type); 8位微控制器监视器( 32K闪存MTP型)型号: | NT68F62U |
厂家: | ETC |
描述: | 8-Bit Microcontroller for Monitor (32K Flash MTP Type) |
文件: | 总57页 (文件大小:504K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NT68F62
8-Bit Microcontroller for Monitor (32K Flash MTP Type)
Features
ꢀOperating voltage range: 4.5V to 5.5V
ꢀCMOS technology for low power consumption
ꢀ6502 8-bit CMOS CPU core
ꢀTwo layers of interrupt management
NMI interrupt sources
- INTE0 (External INT with selectable edge trigger)
- INTMUTE (Auto Mute Activated)
IRQ interrupt sources
ꢀ8 MHz operation frequency
ꢀ32K bytes of flash memory for Multi -Times Program
ꢀ512 bytes of RAM
- INTS0/1 (SCL Go-low INT)
ꢀ2Kbytes Masked BootROM for ISP.
ꢀ One 8-bit base timer
- INTA0/1 (Slave Address Matched INT)
- INTTX0/1 (Shift Register INT)
ꢀ13 channels of 8-bit PWM outputs with 5V open drain
ꢀ4 channel A/D converters with 6-bit resolution
ꢀ25 bi-directional I/O port pins (8 dedicated I/O pins)
ꢀHsync/Vsync signals processor for separate
- INTRX0/1 (Shift Register INT)
- INTNAK0/1 (No Acknowledge)
- INTSTOP0/1 (Stop Condition Occurred INT)
- INTE1 (External INT with Selectable Edge Trigger)
- INTV (VSYNC INT)
&
composite signals, including hardware sync signals
polarity detection and freq. counters with 2 sets of
Hsync counting intervals
- INTMR (Base Timer INT)
- INTADC (AD Conversion Done INT)
ꢀHardware watch-dog timer function
ꢀ40-pin P-DIP and 42-pin S-DIP packages
ꢀHsync/Vsync polarity controlled output, 5 selectable
free run output signals and self-test patterns, auto-
mute function, half freq. I/O function
ꢀTwo built-in IIC bus interfaces support VESA
DDC1/2B+
General Description
operation and two IIC bus interfaces. The user can store
EDID data in the 128 bytes of RAM for DDC1/2B, so that
the user can reduce a dedicated EEPROM for EDID. The
half frequency output function can save the external one-
shot circuit. All of these designs are borne of our
committment to offer our user savings on component costs.
The 42 pin S-DIP IC provides two additional I/O pins –
port40 & port41, Part number NT68F62U represents the S-
DIP IC. For future reference, port40 & port42 are only
available for the 42 pin S-DIP IC.
The NT68F62 is a new generation of monitor µC for auto-
sync and digital control applications. Particularly, this chip
supports various functions to allow users to easily develop
USB monitors. It contains the 6502 8-bit CPU core, 512
bytes of RAM for use as working RAM and as stack area,
32K bytes of Flash memory, 13-channels of 8-bit PWM D/A
converters, 4-channel A/D converters for detection of keys
which can save I/O pins, one 8-bit pre-loadable base timer,
an internal Hsync and Vsync signals processor and a
watch-dog timer, which prevents the system from abnormal
1
V1.0
NT68F62
Pin Configurations
40-Pin P-DIP
42-Pin S-DIP
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSYNCI/INTV [XA8]
HSYNCI[0]
DAC3 [NV]
DAC4/SCL1 [ERASE]
DAC5/SDA1 [MASS]
DAC6 [EXRSTB]
CREG[TMR]
[PG] DAC2
[0] DAC1/ADC3
[YE] DAC0/ADC2
[PG] DAC2
[0] DAC1/ADC3
[YE] DAC0/ADC2
[VPP] RESET
VDD
GND
[8MHZ]OSCO
[0]OSCI
[OE/SE] P15/INTE0
[XE] P14/PATTERN
VSYNCI/INTV [XA8]
HSYNCI[0]
DAC3 [NV]
DAC4/SCL1 [ERASE]
DAC5/SDA1 [MASS]
P41
DAC6 [EXRSTB]
CREG[TMR]
P07/HSYNCO [XA1]
P06/VSYNCO [XA0]
P05/DAC12 [XY5]
P04/DAC11 [XY4]
P03/DAC10 [XY3]
P02/DAC9 [XY2]
P01/DAC8 [XY1]
P00/DAC7 [XY0]
[VPP] RESET
VDD
P40
GND
[8MHZ]OSCO
[0]OSCI
P07/HSYNCO [XA1]
9
9
P06/VSYNCO [XA0]
P05/DAC12 [XY5]
P04/DAC11 [XY4]
P03/DAC10 [XY3]
P02/DAC9 [XY2]
P01/DAC8 [XY1]
P00/DAC7 [XY0]
10
11
12
13
14
15
16
17
18
19
20
10
11
12
13
14
15
16
17
18
19
20
21
[OE/SE] P15/INTE0
[XE] P14/PATTERN
[XA5] P13/HALFI
[XA4] P12/HALFO
[XA3] P11/ADC1
[XA2] P10/ADC0
[XA5] P13/HALFI
[XA4] P12/HALFO
[XA3] P11/ADC1
[XA2] P10/ADC0
[1]P16/INTE1
[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
P31/SCL0 [XA7]
P30/SDA0 [XA6]
P20 [DB0]
P21 [DB1]
P22 [DB2]
[1]P16/INTE1
[DB7] P27
[DB6] P26
[DB5] P25
[DB4] P24
[DB3] P23
P31/SCL0 [XA7]
P30/SDA0 [XA6]
P20 [DB0]
P21 [DB1]
P22 [DB2]
* [ ]: Flash Mode
* [ ]: Flash Mode
Block Diagram
V
DD
SCL0
SDA0
SCL1
CREG
GND
Voltage
32KB Flash memory &
Regulator
IIC BUS
2KB BootROM
OSCI
OSCO
SDA1
SRAM + STACK
512 Bytes
DAC0 - DAC7
DAC8 - DAC12
PWM DACs
Timing Generator
INTE0/1
VSYNCI/INTV
HSYNCI
ADC0 - ADC3
CPU core
6502
A/D Converter
8-Bit Base Timer
Watch Dog Timer
P00 - P07
VSYNCO
HSYNCO
P10 - P16
P20 - P27
P30 - P31
I/O Ports
Interrupt
PATTERN
HALFI
Controller
HALFO
P40 - P41
JEDEC Control
Block
H/V Sync Signals
Processor
ISP Control
Block
2
NT68F62
Pin Description
Pin No.
Designation
Reset Init.
I/O
Description
40 Pin
42 Pin
1
1
DAC2
O
Open drain 5V, D/A converter output 2
Open drain 5V, D/A converter output 1, shared with the A/D
converter channel 3 input
2
3
4
2
3
4
DAC1/ADC3
DAC0/ADC2
DAC1
DAC0
O
O
I
Open drain 5V, D/A converter output 0, shared with the A/D
converter channel 2 input
Schmitt Trigger input pin, low active reset with internal
RESET
pulled down 50KΩ resistor *
5
6
7
8
5
7
8
9
VDD
GND
P
P
O
I
Power
Ground
OSCO
OSCI
Crystal OSC output
Crystal OSC input
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
shared with input pin of external interrupt source0 (NMI),
withSchmitt trigger, selectable triggered, and internal pulled
up 22KΩ resistor
9
10
P15/INTE0
I/O
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
10
11
12
13
14
11
12
13
14
15
P14/PATTERN
P13/HALFI
P12/HALFO
P11/ADC1
I/O
I/O
I/O
I/O
I/O
shared with the output of the self test pattern
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
P13
P12
P11
P10
shared with the half hsync input
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
shared with the half hsync output
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
shared with the A/D converter channel 1 input
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
P10/ADC0
shared with the A/D converter channel 0 input
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
shared with input pin of external interrupt source1, with
Schmitt Trigger, selectable triggered, and an internal pulled
up 22KΩ resistor
15
16
P16/INTE1
P16
I/O
3
NT68F62
Pin Description (continued)
Pin No.
Designation
Reset Init.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
40 Pin
42 Pin
Bi-directional I/O pin, push-pull structure with high current
drive/sink capability
16 - 23
17 - 24
P27 – P20
Open drain 5V bi-directional I/O pin P30, shared with the
SDA0 pin of IIC bus Schmitt Trigger buffer
24
25
26
27
28
29
30
31
32
33
25
26
27
28
29
30
31
32
33
34
P30/SDA0
P30
P31
P00
P01
P02
P03
P04
P05
P06
P07
Open drain 5V bi-directional I/O pin P31, shared with the
SCL0 pin of IIC bus Schmitt Trigger buffer
P31/SCL0
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
P00/DAC7
shared with open drain 5V D/A converter output 7
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
P01/DAC8
shared with the open drain 5V D/A converter output 8
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
P02/DAC9
shared with the open drain 5V D/A converter output 9
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
P03/DAC10
P04/DAC11
P05/DAC12
P06/VSYNCO
P07/HSYNCO
shared with the open drain 5V D/A converter output 10
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
shared with the open drain 5V D/A converter output 11
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
shared with the open drain 5V D/A converter output 12
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
shared with the vsync out
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
shared with the hsync out
34
35
35
36
DAC7
DAC6
O
O
Open drain 5V, D/A converter output 7
Open drain 5V, D/A converter output 6
Open drain 5V, D/A converter output 5, shared with open
drain SDA1 line of IIC bus, Schmitt Trigger buffer
36
38
DAC5/SDA1
DAC5
O
4
NT68F62
Pin Description (continued)
Pin No.
Designation
Reset Init.
I/O
Description
40 Pin
42 Pin
Open drain 5V, D/A converter output 4, shared with the
open drain SCL1 line of IIC bus, Schmitt Trigger buffer
37
39
DAC4/SCL1
DAC3
DAC4
O
O
38
39
40
41
Open drain 5V, D/A converter output 3
Debouncing & Schmitt Trigger input pin for video horizontal
sync signal, internal pull high, shared with the composite
sync input
HSYNCI
I
I
Debouncing & Schmitt trigger input pin for video vertical
sync signal, internal pull high, shared with the input pin of
the external interrupt source, intv, with Schmitt Trigger,
selectable triggered and internal pulled up 22KΩ resistor
40
42
VSYNCI/INTV
VSYNCI
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
-
-
6
P40
P41
I/O
I/O
only 42 pin S-DIP available
Bi-directional I/O pin with internal pulled up 22KΩ resistor,
37
only 42 pin S-DIP available
* This RESET pin must be pulled high by an external pulled-up resistor (5KΩ suggestion), or it will remain at low voltage to
continually rest system.
5
NT68F62
Functional Description
1. 6502 CPU
The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true
indexing capability, programmable stack pointer and variable length stack, a wide selection of addressable memory ranges,
and interrupt input options.
The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Please refer to the 6502 data sheet for more detailed
information.
7
7
7
0
0
0
Accumnlator A
Index Register Y
Index Register X
15
8
Program Counter PCH
PCL
7
7
0
0
Stack Pointer SP
0
7
C
N
V
D
I
Z
Status Register P
B
Carry
1=TRUE
Zero
IRQ Disable
Decimal Mode
1=Result ZERO
1=DISABLE
1=TRUE
BRK Command 1=BRK
Overflow
1=TRUE
Negative
1=NEG
Figure 1.1. The 6502 CPU Registers and Status Flags
6
NT68F62
2. Instruction Set List
Instruction Code
ADC
AND
ASL
Meaning
Operation
Add with carry
Logical AND
A + M + C → A, C
A•M → A
Shift left one bit
C ← M7…M0 ← 0
Branch on C = 0
Branch on C = 1
Branch on Z = 1
BCC
BCS
BEQ
BIT
Branch if carry clears
Branch if carry sets
Branch if equal to zero
Bit test
A•M, M7→N, M6→V
Branch on N = 1
Branch on Z = 0
Branch on N = 0
Forced Interrupt PC+2↓ PC↓
Branch on V = 0
Branch on V = 1
0 → C
BMI
Branch if minus
BNE
BPL
Branch if not equal to zero
Branch if plus
BRK
BVC
BVS
CLC
CLD
CLI
Break
Branch if overflow clears
Branch if overflow sets
Clear carry
Clear decimal mode
Clear interrupt disable bit
Clear overflow
0 → D
0 → I
CLV
0 → V
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
Compare Accumulator to memory
Compare with index register X
Compare with index register Y
Decrement memory by one
Decrement index X by one
Decrement index Y by one
Logical exclusive-OR
Increment memory by one
Increment index X by one
Increment index Y by one
A - M
X - M
Y - M
M - 1 → M
X - 1 → X
Y - 1 → Y
A ⊕ M→A
M + 1 → M
INX
X + 1 → X
INY
Y + 1 → Y
7
NT68F62
Instruction Set List (continued)
Instruction Code
Meaning
Operation
JMP
JSR
LDA
LDX
LDY
LSR
NOP
ORA
PHA
PHP
PLA
PLP
ROL
ROR
RTI
Jump to new location
Jump to subroutine
(PC+1)→ PCL, (PC+2)→ PCH
PC+2↓, (PC+1)→ PCL, (PC+2)→ PCH
Load accumulator with memory
Load index register X with memory
Load index register Y with memory
Shift right one bit
M → A
M → X
M → Y
0 → M7…M0 → C
No operation (2 cycles)
A + M → A
A ↓
No operation
Logical OR
Push accumulator on stack
Push status register on stack
Pull accumulator from stack
Pull status register from stack
Rotate left through carry
Rotate right through carry
Return from interrupt
P ↓
A ↑
P ↑
C ← M7…M0 ← C
C → M7…M0 → C
P ↑, PC ↑
PC ↑, PC+1 → PC
A - M - C → A, C
1 → C
RTS
SBC
SEC
SED
SEI
Return from subroutine
Subtract with borrow
Set carry
Set decimal mode
1 → D
Set interrupt disable status
Store accumulator in memory
Store index register X in memory
Store index register Y in memory
Transfer accumulator to index X
Transfer accumulator to index Y
Transfer stack pointer to index X
Transfer index X to accumulator
Transfer index X to stack pointer
Transfer index Y to accumulator
1 → I
STA
STX
STY
TAX
TAY
TSX
TXA
TXS
TYA
A → M
X → M
Y → M
A → X
A → Y
S → X
X → A
X → S
Y → A
* Refer to 6502 programming data book for more details.
8
NT68F62
3. RAM: 512 X 8 bits
The built-in 512 X 8-bit SRAM is used for data memory and stack area. The RAM addressing range is from $0080 to $027F.
The contents of RAM are undetermined at power-up and are not affected by system reset. Software programmers can
allocate stack area in the RAM by setting stack pointer register (S). Since the 6502 default stack pointer is $01FF,
programmers must set S register to FFH when starting the program.
as;
LDX #$FF
TXS
$0000
System Registers
Unused
$003E
$0080
RAM
stack pointer
$01FF
( 512 Bytes )
$027F
$0280
Unused
$77FF
$7800
Boot
( 2 K Bytes )
ROM
$7FFA
$7FFB
$7FFC
$7FFD
NMI-L
NMI-H
RST-L
RST-H
IRQ-L
IRQ-H
NMI vector
RESET vector
IRQ vector
$7FFE
$7FFF
$8000
Flash
( 32 K Bytes )
Memory
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
NMI-L
NMI-H
RST-L
RST-H
IRQ-L
IRQ-H
NMI vector
RESET vector
IRQ vector
4.1. BootROM: 2K X 8 bits
NT68F62 Provides 2K bytes of Boot-ROM for ISP. The memory space is from $7800 to $7FFF. The addresses, from $7FFA
to $7FFF, are reserved for the 6502 CPU vector.
4.2. Flash memory: 32K X 8 bits
NT68F62 provides 32K flash memory space for programming. The flash memory space is located from $8000 to $FFFF.
The addresses, from $FFFA to $FFFF, are reserved for the 6502 CPU vectors, thus users must arrange them by
themselves. This flash memory can be progammed repeatly at limited times to guarantee its performance.
9
NT68F62
5. System Registers
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Registers for I/O Port0 & Port1
$0000
$0001
PT0
PT1
FFH
7FH
P07
P06
P16
P05
P15
P04
P14
P03
P13
P02
P12
P01
P11
P00
P10
RW
RW
―
Control Register to Control Port2 I/O Direction
P26OE P25OE P24OE P23OE
Control Registers for I/O Port2 - 4
$0002
PT2DIR
FFH
W
P27OE
P22OE
P21OE
P20OE
$0003
$0004
$0005
PT2
PT3
PT4
FFH
03H
03H
P27
P26
P25
P24
P23
P22
―
P21
P31
P41
P20
P30
P40
RW
RW
RW
―
―
―
―
―
Only available for the 42 Pin SDIP version
Control Registers for Synprocessor
―
$0006
$0007
SYNCON
HV CON
FFH
FFH
R
―
―
―
―
―
―
―
―
―
INSEN
HSEL
S/ C
W
―
―
INSEN
HPOLI
―
ENHSEL
VPOLI
HSEL
S/ C
FFH
FFH
HSYNCI
VSYNCI
HPOLO
HPOLO
VPOLO
VPOLO
R
W
―
―
―
ENHOUT
HCL7
ENHOUT
HCL6
―
$0008
$0009
HCNT L
HCNT H
00H
00H
HCL5
―
HCL4
―
HCL3
HCH3
HCL2
HCH2
HCL1
HCH1
HCL0
HCH0
R
R
HCNTOV
CLRHOV
VCL7
W
R
―
VCL6
―
―
―
―
―
―
―
$000A
$000B
VCNT L
VCNT H
00H
00H
VCL5
VCH5
VCL4
VCH4
VCL3
VCH3
VCL2
VCH2
VCL1
VCH1
VCL0
VCH0
VCNTOV
CLRVOV
R
W
W
―
―
―
―
―
―
―
―
―
―
$000C
$000D
FREECON
HALFCON
FFH
FFH
ENPAT
PAT1
FREQ2
FREQ1
FREQ0
W
W
―
―
―
―
―
―
NOHALF
ENHALF
HALFPOL
$000E
$000F
AUTOMUTE
ENDAC
FFH
FFH
HDIFFVL3 HDIFFVL2 HDIFFVL1 HDIFFVL0
ENHDIFF
ENPOL
ENOVER
Control Registers to Enable PWM 8 - 15 Channels
W
―
―
ENDK10
ENDK8
ENDK12
ENDK11
ENDK9
ENDK7
Control Registers for ADC 0 - 3 Channels
$0010
ENADC
FFH
W
―
―
―
CSTA
―
ENADC3
AD03
ENADC2
AD02
ENADC1
AD01
ENADC0
AD00
$0011
$0012
$0013
$0014
AD0 REG
AD1 REG
AD2 REG
AD3 REG
C0H
00H
00H
00H
AD05
AD15
AD25
AD35
AD04
AD14
AD24
AD34
R
R
R
R
―
―
―
―
AD13
AD12
AD11
AD10
―
AD23
AD22
AD21
AD20
―
AD33
AD32
AD31
AD30
―
10
NT68F62
System Registers (continued)
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Register for Polling (Read) Interrupt Groups & Clearing (Write) INTE0 & INTMUTE Interrupt Requests
$0016
NMIPOLL
IRQPOLL
00H
00H
INTE0
CLRE0
IRQ1
INTMUTE
CLRMUTE
IRQ0
R
W
R
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
$0017
IRQ2
Control Registers of Interrupt Enable
$0018
$0019
$001A
$001B
IENMI
IEIRQ0
IEIRQ1
IEIRQ2
00H
00H
00H
00H
INTE0
INTMUTE
RW
RW
RW
RW
―
―
―
―
―
―
―
―
―
―
―
―
INTS0
INTS1
―
INTA0
INTA1
―
INTTX0
INTTX1
INTADC
INTRX0
INTRX1
INTV
INTNAK0 INTSTOP0
INTNAK1 INTSTOP1
INTE1
INTMR
Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests
$001C
$001D
$001E
IRQ0
IRQ1
IRQ2
00H
00H
00H
INTS0
CLRS0
INTS1
CLRS1
―
INTA0
CLRA0
INTA1
CLRA1
―
INTTX0
CLRTX0
INTTX1
INTRX0
CLRRX0
INTRX1
CLRRX1
INTV
INTNAK0 INTSTOP0
CLRNAK0 CLRSTOP0
INTNAK1 INTSTOP1
CLRNAK1 CLRSTOP1
R
W
R
―
―
―
―
―
―
―
―
―
―
―
―
CLRTX1
INTADC
CLRADC
W
R
INTE1
INTMR
CLRV
CLRE1
CLRMR
W
―
―
Selection of Edge Triggered for INTV, INTE0 & 1 Interrupts
$001F
$0020
TRIGGER
CLR WDT
FFH
INTVR
INTE1R
0
INTE0R
1
R/W
W
―
―
―
―
―
Control Registers for Clearing Watch Dog Timer
0
1
0
1
0
1
―
Control Register for DDC1/2B+ of Channel 0
$0021
$0022
$0023
$0024
CH0ADDR
CH0TXDAT
CH0RXDAT
CH0CON
A0H
00H
00H
E0H
ADR7
TX7
ADR6
TX6
ADR5
TX5
RX5
―
ADR4
TX4
ADR3
TX3
ADR2
TX2
RX2
―
ADR1
TX1
W
W
R
―
TX0
RX0
―
RX7
RX6
RX4
RX3
RX1
START
STOP
W
MD1/ 2
ENDDC
TXACK
START
STOP
R
―
―
―
―
―
SRW
$0025
CH0CLK
FFH
DDC2BR2 DDC2BR1 DDC2BR0
W
―
―
MODE
MRW
RSTART
Control Register for DDC1/2B+ of Channel 1
$0026
$0027
$0028
CH1ADDR
CH1TXDAT
CH1RXDAT
A0H
00H
00H
ADR7
TX7
ADR6
TX6
ADR5
TX5
ADR4
TX4
ADR3
TX3
ADR2
TX2
ADR1
TX1
W
W
R
―
TX0
RX0
RX7
RX6
RX5
RX4
RX3
RX2
RX1
11
NT68F62
System Registers (continued)
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0029
CH1CON
E0H
START
STOP
W
―
―
―
MD1/ 2
ENDDC
TXACK
START
STOP
R
―
―
―
―
―
SRW
$002A
CH1CLK
FFH
DDC2BR2 DDC2BR1 DDC2BR0
W
―
―
MODE
MRW
RSTART
Control Registers for Base Timer
$002E
$002F
BT
00H
03H
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
W
W
BTCON
―
―
―
―
―
―
BTCLK
ENBT
Control Registers for PWM Channel 0 - 13
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
DACH0
DACH1
DACH2
DACH3
DACH4
DACH5
DACH6
80H
80H
80H
80H
80H
80H
80H
―
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
―
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
―
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
―
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
―
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
―
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
―
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
―
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
―
RW
RW
RW
RW
RW
RW
RW
DACH7
DACH8
DACH9
DACH10
DACH11
DACH12
80H
80H
80H
80H
80H
80H
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
DKVL7
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
DKVL6
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
RW
RW
RW
RW
RW
RW
DKVL2
ISP
DDC0_IS
P
00H
03H
DDC1_ISP
CH1_A0
R
$003E
ISP REG
W
CH0_A0
12
NT68F62
6. Timing Generator
This block generates the system timing and control signals
to be supplied to the CPU and on-chip peripherals. A
crystal quartz, ceramic resonator, or an external clock
signal which will be provided to the OSCI pin generates
system timing. It generates 8MHz for the system clock and
4MHz for the CPU. Although internal circuits have a
feedback resistor and compacitor included, users can
externally add these components for proper operating.
The typical clock frequency is 8MHz. Different frequencies
will affect the operation of those on-chip peripherals whose
operating frequency is based on the system clock.
OSCI
8MHz
OSCI
External Clock
Unconnected
OSCO
OSCO
(2)
(1)
NT68F62
NT68F62
Figure 6.1. Oscillator Connections
7. RESET
The NT68F62 can be reset by the external reset pin or by
the internal watch-dog timer. This is used to reset or start
the microcontroller from a POWER DOWN condition.
During the time that this reset pin is held LOW (*reset line
must be held LOW for at least two CPU clock cycles),
writing to or from the µC is inhibited. When a positive edge
is detected on the RESET input, the µC will immediately
begin the reset sequence.
The reset status is as follows:
1. PORT0、PORT1、PORT2、PORT3 (& PORT4) pins
will act as I/O ports with HIGH output
2. Sync processor counters reset and VCNT | HCNT
latches cleared
3. All sync outputs are disabled
4. Base timer is disabled and cleared
5. Various Interrupt sources are disabled and cleared
6. A/D converter is disabled and stopped
7. DDC1/2B+ function is disabled
After a system initialization time of six CPU clock cycles,
the mask interrupt flag will be set and the µC will load the
program counter from the memory vector locations $FFFC
and $FFFD. This is the start location for program control.
8. PWM DAC0 – DAC6 output 50% duty waveform and
DAC7 - DAC12 is disabled
9. Watch-dog timer is cleared and enabled
An internal Schmitt Trigger buffer at the RESET pin is
provided to improve noise immunity.
13
NT68F62
8. A/D Converters
The structure of these analog to digital converters is 6-bit
successive approximation. Analog voltage is supplied from
external sources to the A/D input pins and the result of the
conversion is stored in the 6-bit data latch registers ($0011
& $0014). The A/D channels are activated by clearing the
correspondent control bits in the ENADC control register.
When users write '0' into one of the enabled control bits, its
correspondent I/O pin or DAC will be switched to the A/D
converter input pin (ADC0 & ADC1 are shared with
PORT10 & PORT 11; ADC2 & ADC3 are shared with
DAC0 & DAC1). Conversion will be started by clearing the
CSTA
bit (CONVERSION START) in the ENADC control
register. When the conversion is finished, the system will
set this INTADC bit. Users can monitor this bit to get the
valid A/D conversion data in the AD latch registers ($0011 -
$0014). Users can also open the interrupt sources to
remind users to get the stable digital data. Notice that only
at the activated A/D channel, its latched data are available.
The analog voltage to be measured should be stable during
the conversion operation and the variation must not exceed
LSB for the best accuracy in measurement.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0010
ENADC
FFH
W
―
―
―
CSTA
―
ENADC3
AD03
ENADC2
AD02
AD12
AD22
AD32
INTV
ENADC1
AD01
ENADC0
AD00
$0011
$0012
$0013
$0014
$001B
$001E
AD0 REG
AD1 REG
AD2 REG
AD3 REG
IEIRQ2
C0H
00H
00H
00H
00H
00H
AD05
AD15
AD25
AD35
―
AD04
AD14
AD24
AD34
―
R
R
―
―
―
―
―
―
―
AD13
AD11
AD10
―
AD23
AD21
AD20
R
―
AD33
AD31
AD30
R
―
INTADC
INTADC
CLRADC
INTE1
INTE1
CLRE1
INTMR
INTMR
CLRMR
R/W
R
―
IRQ2
INTV
―
―
―
CLRV
W
―
―
―
Reference ADC Table (VDD = 5.0V)
15
16
17
18
19
1A
1B
1.50V
1.58V
1.66V
1.74V
1.82V
1.90V
1.98V
1C
1D
1E
1F
20
21
22
2.06V
23
24
25
26
27
28
29
2.59V
2A
2B
2C
2D
2E
2F
30
3.14V
2.12V
2.20V
2.28V
2.35V
2.44V
2.51V
2.67V
2.75V
2.82V
2.91V
2.98V
3.07V
3.22V
3.30V
3.38V
3.46V
3.54V
3.62V
Note: It is strongly recommended that the ADC’s input signal should be allocated within the ADC’s linear voltage
range (1.5V~3.5V) to obtain a stable digital value. Do not use the outer ranges (0V~1.4V & 3.6V~5.0V) in which
the converted digital value is not guaranteed.
14
NT68F62
9. PWM DACs (Pulse Width Modulation D/A Converters)
There are 13 PWM D/A converters with 8-bit resolution in the NT68F62. All of these D/A (DAC0 - DAC12) converters are of
open-drain output structure with an external 5V applied maximum. DAC0 – DAC6 are dedicated PWM channels, and DAC7 -
DAC12 are shared with the I/O pins. These shared PWM channels are activated by clearing the correspondent control bits in
the ENDAC control register ($000F). When users write '0' into one of the enable control bits, its correspondent I/O pin will be
switched to a PWM output pin.
The PWM refresh rate is 62.5KHz operating on an 8MHz system clock. There are 13 readable DACH registers
corresponding to 13 PWM channels ($0030 - $003D). Each PWM output pulse width is programmable by setting the 8 bit
digital to the corresponding DACH registers. When these DACH registers are set to 00H, the DAC will output LOW (GND
level) and every 1 bit addition will add 62.5ns pulse width. After reset, all DAC outputs are set to 80H (1/2 duty output).
(Please refer to Figure 9.1 for the detailed timing diagram of the PWM D/A output.)
8MHz Fosc
PWM value : 255
00
0
1
2
3
m-1
m
0
1
255
01
02
03
m
255(FF)
Figure 9.1. The DAC Output Timing Diagram and Wave Table
15
NT68F62
PWM DACs (continued)
DAC0 & DAC1 are shared with the ADC2 & ADC3 input pins respectively. If ENADC2/3 bit in the ENADC control register is
cleared to LOW, the A/D converters will activate simultaneously. After the chip is reset, ENADC2/3 bits will be in HIGH state
and DAC0 & DAC1 will act as PWM output pins.
DAC4 & DAC5 are shared with SCL1 & SDA1 I/O pins respectively. If users clear the ENDDC bit in the CH1CON control
register to LOW, channel 1 of the DDC will be activated. When used as the DDC channel, the I/O port will be of an open
drain structure and include a 'Schmitt Trigger' buffer for noise immunity. After the chip is reset, ENDDC bits will be in HIGH
state and DAC4 - DAC5 will act as PWM output pins.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$000F
ENDAC
FFH
W
―
―
ENDK8
ENDK12 ENDK11
ENDK10 ENDK9
ENDK7
$0010
ENADC
FFH
W
―
―
―
CSTA
ENADC3 ENADC2 ENADC1 ENADC0
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
DACH0
DACH1
DACH2
DACH3
DACH4
DACH5
DACH6
80H
80H
80H
80H
80H
80H
80H
―
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
―
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
―
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
―
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
―
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
―
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
―
RW
RW
RW
RW
RW
RW
RW
―
―
DACH7
DACH8
DACH9
DACH10
DACH11
DACH12
80H
80H
80H
80H
80H
80H
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL7 DKVL6
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL5
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL4
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL3
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL2
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL1
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
DKVL0
RW
RW
RW
RW
RW
RW
DAC control register ($000F) and DAC value register ($0030 - $003D)
16
NT68F62
10. Watch-Dog Timer (WDT)
The NT68F62 implements a watch-dog timer reset to avoid
system stop or malfunction. The clock of the WDT is taken
from the on-chip RC oscillator, which does not require any
external components. Thus, the WDT will run, even if the
clock on the OSCI/OSCO pins of the device has been
stopped. The WDT time interval is about 0.5 second. The
WDT must be cleared within every 0.5 second when the
software is in normal sequence, otherwise the WDT will
overflow and cause a reset. The WDT is cleared and
enabled after the system is reset, and can not be disabled
by the software. Users can clear the WDT by writing 55H to
the CLRWDT register ($0020).
as;
LDA #$55
STA $0020
Addr.
$0020
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
CLR WDT
-
0
1
0
1
0
1
0
1
W
11. Interrupt Controller
The system provides two kinds of interrupt sources: NMI &
IRQ. The NMI cannot be masked if user enabled this NMI
interrupt. Users will execute the NMI interrupt vector any
time that sources are activated. The IRQ interrupts can be
masked by executing a CLI instruction or by setting the
interrupt mask flag directly in the µC status register. In the
process of an IRQ interrupt, if the interrupt mask flag is not
set, the µC will begin an interrupt sequence. The program
counter and processor status register will be stored in the
stack. The µC will then set the interrupt mask flag high so
that no further interrupts may occur. At the end of this
cycle, the program counter will be loaded from addresses
$FFFE & $FFFF, thus transferring program control to the
memory vector located at these addresses. For NMI
interrupt, µC will transfer execution sequence to the
memory vector located at addresses $FFFA & $FFFB.
When manipulating various interrupt sources, NT68F62
divides them into two groups for accessing them easily.
One is the NMI group and the other is the IRQ group.
-
The NMI group includes INTE0, INTMUTE.
The IRQ group includes the subgroup of IRQ0,
IRQ1,RQ2:
-
IRQ0: DDC1/2B+ Channel 0 interrupt sources; It
includes INTS0, INTA0, INTTX0, INTRX0,
INTNAK0 and INTSTOP0 interrupts.
IRQ1: DDC1/2B+ Channel 1 interrupt sources; It
includes INTS0, INTA1, INTTX1, INTRX1,
INTNAK1 and INTSTOP1.
IRQ2: It includes INTADC, INTV, INTE1 and INTMR
interrupt sources.
Below are the interrupt sources.
Nonmaskable Interrupt Group:
Interrupt
Meaning
Action
INTE0 INT
External 0 INT
It will be activated by the rising or falling edge of the external interrupt pulse.
The triggered edge can be selected by EDGE0 bit.
INTMUTE
Auto Mute
It will be activated when the mute condition occurs (Hsync frequency change).
Please refer the synprocessor section for a more detailed explanation.
Maskable Interrupt Group:
Interrupt
Meaning
Action
INTADC
A/D Conversion
Done
User activates the ADC by clearing the CSTART bit. When the AD
conversion is done, this bit will be set.
INTV INT
Vsync INT
It will be activated by the rising edge of every vsync pulse.
INTE1 INT
External 1 INT
It will be activated by the rising or falling edge of the external interrupt pulse.
The triggered edge can be selected by EDGE1 bit.
INTMR INT
Timer INT
It will be activated by the rising edge of every ??? when the Base Timer
counter overflows and counting from $FF to $00.
17
NT68F62
DDC Channel 0/1 Maskable Interrupt Sources:
Interrupt
Meaning
Action
INTS INT
SCL Go-Low INT
In DDC1 mode, it will be activated when the external device proceed a DDC2
communication. This action includes pulling the SCL line to ground or sending
out a 'START' condition directly. The system will respond to this action by
changing DDC1 mode to DDC2 slave mode.
INTA INT
Address Matched It will be activated in DDC2 slave mode when the external device calls a
INT
NT68F62 slave address. If this calling address matches the NT68F62 address,
the system will generate this interrupt to remind the user
INTTX INT
INTRX INT
INTNAK INT
Transfer Buffer
Empty INT
It will be activated in DDC2 mode when the transmission buffer, IIC_TXDAT, is
empty in transmission mode.
Receiving Buffer
Overflow INT
It will be activated in DDC2 mode when the new data are stored in the
IIC_RXDAT register in receive mode.
No Acknowledge In transmission mode, this interrupt will be activated when the NT68F62 has
INT
send out one byte of data but the external device does not respond with an
acknowledgement bit to it.
INTSTOP INT
DDC2 Stop INT
In SLAVE mode, this interrupt will be activated when the NT68F62 receives a
'STOP' condition.
IRQ0
IEIRQ0
INTSTOP0
INTNAK0
INTRX0
INTTX0
INTA0
IRQ0
INTS0
IRQ1
IRQ2
IEIRQ1
INTSTOP1
INTNAK1
INTRX1
INTTX1
INTA1
IRQ1
IRQ (to CPU 6502)
INTS1
IEIRQ2
INTMR
INTE1
INTV
IRQ2
INTADC
NMIPOLL
INTMUTE
INTE0
IENMI
NMI (to CPU 6502)
Figure 11.1. Interrupt Controller Structure
18
NT68F62
Enabling Interrupts: The system will disable all of these
interrupts after reset. Users can enable each of the
interrupts by setting the interrupt enable bits at the IENMI,
IEIRQ0 ~ IEIRQ2 control registers. For example, if users
want to enable the external interrupt 0 (INTE0), write '1' to
the INTE0 bit in the IENMI control register. At the INTE0
pin, whenever NT68F62 detects an interrupt message, it
will generate an interrupt sequence to fetch the NMI vector.
Because these IEX control registers can be read, users can
read back what interrupts he has activated. At polling
sequence, users need not poll those unactivated interrupts.
Polling Interrupts: When an NMI interrupt occurs, during the
NMI interrupt service routine, users must poll the INTE0 &
INTMUTE bit in the NMIPOLL control register to confirm the
NMI interrupt source. The polling sequence decides the
priority of the NMI interrupt acceptance. When an IRQ
interrupt occurrs, during the IRQ interrupt service routine,
users must poll the IRQ0 – IRQ2 in the IRQPOLL control
register to confirm the IRQ interrupt source. In the same
way, the polling sequence decides the priority of the IRQ
interrupt acceptance. When deciding the IRQ source, users
can further confirm the real interrupt source by polling the
Correspondent IRQX control register ($001C - $001E).
Requesting Interrupts be set : No matter whether the user
has set the interrupt enable bits or not, if the interrupt
triggered condition is matched, the system will set the
correspondent bits in the IRQ0 ~ IRQ3 control registers or
in the NMIPOLL control register (INTE0 & INTMUTE bits).
For example, if at the VSYNCI pin, the system detects a
pulse occurring, the system will set the INTV bit in the IRQ2
control register.
Clearing the Interrupt Request bit: When an interrupt
occurrs, the CPU will jump to the address defined by the
interrupt vector to execute the interrupt service routine.
Users can check which one of the interrupt sources is
activated and operating a task. Upon entering the interrupt
service routine, the request bit that caused the interrupt
must be cleared by the user before finishing the service
routine and returning to the normal instruction sequence. If
users forget to clear this request bit, after returning to the
main program, it will interrupt CPU again because the
request bit remains activated. Simply, users just need to
write '1' to the polling bits in the NMIPOLL & IRQX registers
($0016 & $001C - $001E) to clear those completed
interrupt sources.
Interrupt Groups: The system divides the IRQ interrupt
sources into several groups, ex IRQ0, IRQ1, and IRQ2. In
each of these groups, if its membership in one of the
interrupt groups has been activated, its group bit in the
IRQPOLL control register will be set. For example, if the
INTS0 of the first DDC1/2B+ channel is activated, the
INTS0 bit in the IRQ0 control register will be set and the
IRQ0 bit in the IRQPOLL control register will also be set.
Notice that the IRQ0 bit in the IRQPOLL control register will
be cleared by the system when all of its interrupt sources,
INTS0, INTA0, INTTX0, INTRX0, INTNAK0 and INTSTOP0
have been cleared by the user or the system. The NMI
group follows the same procedure as the IRQ groups.
Selecting interrupt trigger edge: INTVR, INTE0R & INTE1R
interrupt sources are the edge triggered type of interrupts.
The system allows the selection of rising or falling edge
triggers to be used under the user’s control. After reset, the
rising edge triggers are provided and the content is 'FF' in
the TRIGGER control register ($001F). The user just clears
the control bits in this TRIGGER register and switches
these interrupts to be falling edge triggered.
19
NT68F62
Control Bit Description
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Register for Polling Interrupt
$0016
NMIPOLL
00H
INTE0
CLRE0
IRQ1
INTMUTE
CLRMUTE
IRQ0
R
W
R
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
―
$0017
IRQPOLL
00H
IRQ2
Control Registers of Interrupt Enable
$0018
$0019
$001A
$001B
IENMI
IEIRQ0
IEIRQ1
IEIRQ2
00H
00H
00H
00H
INTE0
INTNAK0
INTNAK1
INTE1
INTMUTE
INTSTOP0
INTSTOP1
INTMR
RW
RW
RW
RW
―
―
―
―
―
―
―
―
―
―
―
―
INTS0
INTS1
―
INTA0
INTA1
―
INTTX0
INTTX1
INTADC
INTRX0
INTRX1
INTV
Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests
$001C
$001D
IRQ0
IRQ1
00H
00H
INTS0
CLRS0
INTS1
CLRS1
―
INTA0
CLRA0
INTA1
CLRA1
―
INTTX0
INTRX0
INTNAK0
INTSTOP0
R
W
R
―
―
―
―
―
―
―
―
―
―
CLRTX0 CLRRX0 CLRNAK0 CLRSTOP0
INTTX1 INTRX1 INTNAK1 INTSTOP1
CLRTX1 CLRRX1 CLRNAK1 CLRSTOP1
W
W
CLRADC
CLRV
CLRE1
CLRMR
Selection of Edge Triggers for INTE0 & 1 Interrupt
INTVR
$001F
TRIGGER
FFH
INTE1R
INTE0R
R/W
―
―
―
―
―
20
NT68F62
and then the input signals can be read. This port output is
high after reset.
12. I/O PORTs
The NT68F62 has 25 pins dedicated to input and output.
P00 - P05 are shared with DAC7 - DAC12 respectively. If
These pins are grouped into 4 ports.
ENDK7 - ENDK12 is set to LOW in the ENDAC register,
P00 - P05 will act as DAC7 - DAC12 respectively (Figure
12.1. PORT0: P00 - P07
12.2). After the chip is reset, ENDK7 - ENDK12 will be in
the HIGH state and P00 - P05s will act as I/O ports.
PORT0 is an 8-bit bi-directional CMOS I/O port with PMOS
as internal pull-up (Figure 12.1). Each pin of PORT0 may
be bit programmed as an input or output port without
software controlling the data direction register. When Port0
works as an output, the data to be output are latched to the
port data register and output to the pin. PORT0 pins that
have '1's written to them are pulled HIGH by the internal
PMOS pull-ups. In this state they can be used as inputs
P06 、 P07 are shared with VSYNCO
& HSYNCO
respectively. If ENHOUT、ENVOUT is set to LOW in the
HVCON register, P06 、 P07 will act as VSYNCO &
HSYNCO respectively (Figure 12.3). After the chip is reset,
ENHOUT & ENVOUT will be in the HIGH state and
P06、P07 will act as I/O pins.
Addr.
$0000
$0007
Register
PT0
HV CON
INIT
FFH
FFH
Bit7
P07
―
Bit6
P06
―
Bit5
P05
HSYNCI
Bit4
P04
VSYNCI
Bit3
P03
HPOLI
Bit2
P02
VPOLI
Bit1
P01
HPOLO
Bit0
P00
VPOLO
R/W
RW
R
FFH
FFH
HPOLO
ENDK8
VPOLO
ENDK7
W
W
ENHOUT ENVOUT
―
―
―
―
ENDK11
$000F
ENDAC
ENDK12
ENDK10
ENDK9
―
―
PWM
V
DD
Output
PWM
Data In
I/O
Figure 12.2. PWM Output Structure
V
DD
Data Out
O/P
Data In
Data Out
Figure 12.1. I/O Structure
Figure 12.3. Output Structure
21
NT68F62
12.2. Port1: P10 - P16
PORT10 - PORT16 is a 7-bit bi-directional CMOS I/O port
with PMOS as internal pull-up (Figure 12.1). Each bi-
directional I/O pin may be bit programmed as an input or
output port without software controlling the data direction
register. When Port1 works as an output, the data to be
output is latched to the port data register and output to the
pin. Port1 pins that have '1's written to them are pulled high
by the internal PMOS pull-ups. In this state they can be
used as inputs and then the input signals can be read. This
port output is high after reset.
sync processor paragraph. After the chip is reset, the
ENHALF bits will be in the HIGH state and P12、P13 will
act as I/O pins.
P14 is shared with the output pin of the self test pattern. If
users clear the PATTERN bit in the SYNCON control
register and the free running function has been activated,
the P14 will switch to be the output pin of the self test
pattern. This pattern output pin is of the push-pull structure.
After the chip is reset, the PATTERN bits will be in the
HIGH state and P14 will act as an I/O pin. (Refer to the
'Syncprocessor' section for more detailed information.)
P10 & P11 are shared with AD0 & AD1 input pins
respectively. If the ENADC0/ 1 bit in the ENADC control
register is cleared to LOW, the A/D converters will activate
P15 & P16 can be shared with the external interrupt INTE0
& INTE1 pins if the INTE0/1 bits are set in the control
register of the interrupt enable ($0018 & $001B). These
interrupt pins have 'Schmitt Trigger' input buffers. After the
chip is reset, INTE0/1 bits will be in the HIGH state and P15
& P16 will act as I/O pins.
simultaneously. After the chip is reset, ENADC0/1 bits will
be in the HIGH state and P10 - P11 will act as I/O pins.
P12、P13 are shared with the HALF SIGNALS input and
OUTPUT pins by accessing the OUTCON control register.
If the ENHALF bit is cleared to LOW, P13 will switch to
HALFHI pin (input pin) and P12 will switch to HALFHO pin
(output pin, Figure 12.3). For HALFHI & HALFHO pin
descriptions, please refer half frequency function in the H/V
Refer to the 'INTERRUPT CONTROLLER' paragraph
above for more details about the interrupt function.
Addr.
$0001
$000C
Register
PT1
INIT
7FH
FFH
Bit7
―
Bit6
P16
Bit5
P15
Bit4
P14
Bit3
P13
Bit2
P12
Bit1
P11
Bit0
P10
R/W
RW
W
FREECON
FREQ2
―
―
―
PAT0
FREQ1
FREQ0
ENPAT
$0010
ENADC
FFH
W
―
―
―
CSTA
―
ENADC3
ENADC2
―
ENADC1
INTE0
ENADC0
INTMUTE
INTMR
$0018
$001B
IENMI
00H
00H
RW
RW
―
―
―
―
―
―
―
IEIRQ2
INTV
INTE1
―
―
V
DD
VDD
Data Out
I/P
.
I/O
Data Input
Data OE
Data In
Figure 12.4. Schmitt Input Structure
Figure 12.5. I/O Structure
22
NT68F62
12.3. PORT2: P20 - P27
PORT2, an 8-bit bi-directional I/O port (Figure 12.5), may be programmed as an input or output pin by the software control.
When setting the PT2DIR control bit to '0', its correspondent pin will act as an output pin. On the other hand, clear PT2DIR
bit to '1'and it will act as an input pin. When programmed as an input pin, it has an internal pull-up resistor. When
programmed as an output pin, the data to be output is latched to the port data register and output to the pin with a push-pull
structure. This port acts as an input port after reset.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0002
$0003
PT2DIR
PT2
FFH
FFH
W
P27OE
P27
P26OE
P26
P25OE
P25
P24OE
P24
P23OE
P23
P22OE
P22
P21OE
P21
P20OE
P20
RW
$0010
$0029
ENADC
FFH
FFH
W
CSTA
―
―
―
ENADC3
STOP
ENADC2
RXACK
ENADC1
TXACK
ENADC0
CH1CON
START
RW
ENDDC
MD1/
SRW
―
2
12.4. PORT3: P30 - P31
PORT3 is a 2 bit bi-directional open-drain I/O port (Figure 12.6). Each pin of Port3 may be bit programmed as an input or
output port with open drain structure. When Port3 works as an output pin, the data to be output is latched to the port data
register and output to the pin. When Port3 pins have '1's written to them, users must connect PORT3 with the external
pulled-up resistor and then PORT3 can be used as an input (the input signal can be read). This port output is hiGH after
reset.
P30、P31 include Schmitt Trigger buffers for noise immunity and can be configured as the IIC pins SDA0 & SCL0
respectively. If ENDDC is set to LOW in the CH0DDC control register, P30、P31 will act as SDA0 & SCL0 I/O pins
respectively and will be of an open drain structure (Figure 12.6). After the chip is reset, this ENDDC bit will be in the HIGH
state and PORT3 will act as I/O pin.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0004
PT3
FFH
P31
P30
RW
―
―
―
―
―
―
$0024
CH0CON
FFH
START
STOP
RXACK
I/O
TXACK
RW
ENDDC
MD1/
SRW
―
2
Data Out
Data In
Figure 12.6. PORT3
23
NT68F62
12.5. PORT4: P40 - P41
PORT4 is available only on the 42pin SDIP IC. PORT40 - PORt41 is a 2-bit bi-directional CMOS I/O port with PMOS internal
pull-up (Figure 12.1). Each bi-directional I/O pin may be bit programmed as an input or output port without software
controlling the data direction register. When Port4 works as an output port, the data to be output is latched to the port data
register and output to the pin. Port4 pins that have '1's written to them are pulled high by the internal PMOS pull-ups. In this
state they can be used as input pins. The input signal can be read. This port outputs HIGH after reset.
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
$0005
PT4
FFH
P41
P40
RW
―
―
―
―
―
―
13. H/V Sync Signals Processor
The functions of the sync processor include polarity detection, Hsync & Vsync signals counting, and programmable sync
signals output. It also provides 3-sets of free running signals and special outputs of the test pattern during the burn-in
process when activating the free running output function. The NT68F62 can properly handle either composite or separate
sync signal inputs even without sync signal input. As to processing the composite sync signal, a hardware separator will be
activated to extract the HSYNC signal under the users control. The input at HSYNCI can be either a pure horizontal sync
signal or a composite sync signal. For the sync waveform refer to Figure 13.1 & Figure 13.2.
The sync processor block diagram is shown in Figure 13.3. Both VSYNCI & HSYNCI pins have Schmitt Triggers and filtering
processes to improve noise immunity. Any pulse that is shorter than 125 ns, will be regarded as a glitch and will be ignored.
(a) Positive polarity
(b) Negative polarity
Figure 13.1. Separate H Sync. Waveform
(a) Positive Polarity
(b) Negative Polarity
Figure 13.2. Composite H Sync. Waveform
24
NT68F62
VCNTL
VCNTH
Control
Logic
Enable
V sync.
Latch
INTV
S/C
Enable
Reset
8us
VSYNC
INPUT
Schmitt
Trigger
Digital
Filter
V sync.
counter
V
1
0
HSEL
ENHSEL
16.384 ms
32.968 ms
0
1
0
Enable
Reset
H sync.
counter
1
AUTO
MUTE
V
Enable
H sync.
Latch
H & V
INTMUTE
Sync.
Polarity
Detector
H
HSYNC
INPUT
Digital
Filter
Schmitt
Trigger
Sync
Separator
HCNTL
HCNTH
HPOLO
HPOLI
H Sync.
Output
Control
H
HSYNCO
PATTERN
ENPAT, PAT10/1
Pattern
O/P
FREQ0/1/2
FREE_RUN
Control
Control
S/C
VPOLI
V Sync.
Output
Control
V
0
1
VSYNCO
V
VPOLO
Figure 13.3. Sync. Processor Block Diagram
25
NT68F62
13.1. V & H Counter Register: VCNTL/H, HCNTL/H
Vsync counter: VCNTL/H, the 14-bit READ ONLY register, contains information on the Vsync frequency. An internal counter
counts the numbers of 8us pulses between two VSYNC pulses. When the next VSYNC signal is recognized, the counter is
stopped and the VCNTH/L register latches the counter value. Then the counter counts from zero again for evaluating the
next VSYNC time interval. The counted data can be converted to the time duration between two successive Vsync pulses. If
there is no VSYNC signal , the counter will overflow and set the VCNTOV bit (in the VCNTH register) to HIGH. Once the
VCNTOV is set to HIGH, it stays in the HIGH state until '1' is written to it (CLRVOV bit).
Hsync counter: If the ENHSEL bit is set to HIGH, the internal counter counts the Hsync pulses between two Vsync pulses.
The HCNTL/H control registers contain the numbers of Hsync pulse between two Vsync pulses. These data can determine if
the Hsync frequency is valid or not to determine the accurate video mode.
The system supports two other options of the time interval for the user to count the frequency of Hsync pulses. If users clear
the ENHSEL and set the HSEL bits properly, this internal counter counts the Hsync pulses during a system defined time
interval. The time interval is defined below:
Hsync Freq
Note
ENHSEL
HSEL
1
0
0
-
Disabled
16.384 ms
32.768 ms
After system reset or users disabling
0
1
After system reset, this interval will be disabled and the content of ENHSEL & HSEL0 bits will be '1'. When this function is
disabled, the HCNTL/H counter works on the VSYNC pulse. It is invalid to write '00' to them.
Latching the hsync counter: The counted value will be latched by the HCNTH/L register pairs that are updated by the Vsync
pulse or by the system defined time interval. (Refer to the Figure 13.4 for the operation of the HCNTL/H counter.) If the
counter overflows, the HCNTOV bit (in the HCNTH register) will be set to HIGH. Once the HCNTOV is set to HIGH, it keeps
in the HIGH state until '1' is written to it (CLRHOV bit). When setting this CLRHOV bit, the HCNT counter will not be reset to
zero.
Latch HCNT register
Reset H sync. counter
Start pulse counting
Latch HCNT register
Reset H sync. counter
Start pulse counting
●
●
●
VSYNCI
HSYNCI
●
●
●
●
●
●
16.384ms/32.768ms
(Setting HSEL0/1 bits)
●
●
●
HSYNCI
Figure 13.4. Hsync Counter Operation
26
NT68F62
●
●
●
(1) HSYNCI
(2) HSYNCI
Composite H sync. waveform (H EOR V)
Composite H sync. waveform (H OR V)
●
●
●
Hsync pulse or no pulse, the output signal of Hsync will be inserted.
2µs
HSYNCO
VSYNCO
●
●
●
Original
Hsync Pulse
Original
Inserted Hsync Pulse
Hsync Pulse
Widen 9 s
µ
Figure 13.5. Composite H & V Sync. Processing
27
NT68F62
Sync. Mode
Processing
Set S/C = '0'
System Default:
S/C = '1' & ENSEL = '1'
Open INTV & clear INTV flag
Freq.
Clear VCNTOV & HCNTOV
Open INTV & clear INTV flag
Calculating
Set S/C = '1' & ENSEL = ''0'
& SELECT TIME INTRVAL
(16.384 or 32.968ms)
Clear VCNTOV & HCNTOV
Delay 2 * TIME INTELVAL
No
INTV ?
Yes
1. Extract VCNTL/H 14 bit data
2. 14 bits data * 8 us
= Vsync. time duration
3. Its reciprocal
Delay 132 ms
Yes Off Mode
HCNTH = '00'
?
Delay 132 ms
is Vsync. freq.
No
Yes
Suspend Mode
Yes
VCNTOV = '1'
?
VCNTOV = '1'
?
No
1. Extract HCNTL/H
12 bit data
STAND-BY Mode
Yes
No
2. 12 bit data * Vsync. freq.
= Hsync. freq.
HCNTH = '00'
?
or 12 bits data/time interval
(16.382 or 32.968 ms)
3. Its reciprocal
Worng Mode
Yes
HCNTH ='00'
NORMAL Mode
Seperate Sync.
?
No
is Hsync. time duration.
No
Read VCNT|HCNT
Counter Register
Read VCNT|HCNT
Counter Register
Return
NORMAL Mode
Composite Sync.
Freq.
Calculating
Return
Figure 13.6. H & V Sync. Software Control Flow Chart (for reference only)
28
NT68F62
13.2. Sync Processor Control Register:
Polarity: The detection of Hsync or Vsync polarity is
achieved by the hardware circuit that samples the sync
signal's voltage level periodically. Users can read the
HPOLI & VPOLI bits from the HVCON register, the bit = '1'
represents positive polarity and '0' represents negative
polarity. Furthermore, users can read the HSYNCI and
VSYNCI bits in the HVCON register to detect the H & V
sync input signal. Users can control the polarity of the H &
V sync output signal by writing the appropriate data to the
HPOLO and VPOLO bits in the HVCON register, '1'
represents positive polarity and '0', negative polarity.
Sync output: In pin assignment, VSYNCO & HSYNCO
represent Vsync & Hsync output, which are shared with
P06 & P07 respectively. If ENVOUT & ENHOUT are set
to '0' in the HVCON register, P06 & P07 will act as
VSYNCO & HSYNCO output pins. When the input sync is a
separate signal, the V/HSYNCO will output the same signal
as the input without delay. But if the input sync is a
composite signal, the VSYNCO signal will have a fixed
delay time of about 20ns and the HSYNCO has a nonfixed
delay time of about 125ns.
Half frequency Input and output: In pin assignment, when
Composite sync: Users have to determine whether the
incoming signal is separate sync or composite sync and set
the S/C & ENHSEL /HSEL bit properly. If the input sync
signal is composite and after setting S/ C to '0', the sync
separator block will be activated (please refer to Figure
13.5). At the area of a Vsync pulse, there can exist Hsync
pulses or not. For the output of Hsync, users can activate
hardware to interpolate the Hsync pulses in that area by
users set ENHALF bits to '0' in the HALFCON register, the
HALFHO pin will act as an output pin and output half of the
input signal in the HALFHI pin with 50% duty (see Figure
13.7). If set NOHALF to '0', HALFHO will output the same
signal in the HALFHI pin and the user can control its
polarity of output HALFHO by setting HALFPOL bit, '1' for
positive and '0' for negative polarity. After the chip is reset,
ENHALF 、 NOHALF & HALFPOL will be in the HIGH
state and P12 & P13 will act as I/O pins. It is recommended
to add a Schmitt Trigger buffer at the front of the HALFI pin.
clearing the INSEN bit. The width of these inserted pulses
is fixed at 2uS and the time interval is the same as the
previous one. According to the last Hsync pulse outside the
Vsync pulse duration, the hardware will arrange the interval
of these hardware interpolated pulses. These inserted
Hsync pulse perhaps have maximum phase deviation of
125 nS. The Vsync pulse can be extracted by hardware
from the composite Hsync signal and the delay time of the
output Vsync signal will be limited to less than 20ns. To
insert the Hsync pulse safely, the extracted Vsync pulse will
be widened about 9µs. Although , the system will insert the
Hsync pulse evenly, the last inserted Hsync pulse will have
a different frequency from the original ones.
Free run signal output: The user can select one of the free
running frequencies (listed below) outputting to HYSNCO &
VSYNCO pin by setting the FREQ0/1/2 bits. If the user
does not enable the H/VSYNCO by clearing the ENVOUT
or the ENHOUT bits, any setting of FREQ0/1/2 bits will be
invalid. After system reset, NT68F62 does not provide free
running frequency and both of the FREQ0/1/2 bits are set
to ' 1'. The free running frequency can be set according the
table below:
The system will not implement this insertion function so
users must clear the INSEN bit in the SYNCON control
register to activate this function. After reset, the S/ C &
INSEN bits default value are HIGH and clear the VCNT |
HCNT counter latches to zero.
Free Running Freq.
Hsync Freq.
Vsync Freq.
Note
FREQ2
FREQ1
FREQ0
Refer to
1
0
0
0
8M/256=31.2K
Hsync/512=61.0Hz
Figure 13.7
2
3
4
5
0
0
0
1
1
1
0
1
1
0
1
1
1
0
8M/4/9/5=44.4K
8M/128=62.5K
8M/4/5/5=80K
Hsync/512=86.8Hz
Hsync/3/5/7/8=74.4Hz
Hsync/1024=78.1Hz
Hsync/1024=88.7Hz
1
0/1
0
8M/4/2/11=90.9K
1
Disabled Free
Run function
After System
Reset
29
NT68F62
Self test pattern: On activating the free running function, the system will generate the test pattern when clearing the ENPAT
bit. The PORT14 pin will switch from I/O pin to pattern output pin (push-pull structure). The system provides four types of test
patterns. Refer to the figure below. Set the PAT0 bits to select the pattern type (Figure 13.8). If the free run function has not
been enabled, any change of ENPAT & PAT0 bits will be invalid. Refer to the Figure 13.9 for the porch time of the video
pattern.
PAT0
Test Pattern
Note
0
1
(1)
(2)
Only activated when ENPAT bit is cleared
The porches of the self test pattern are listed below:
Free Running
Front Porch of
BACK Porch of
Front Porch of
HBLANK
BACK Porch of
HBLANK
VSYNC
HSYNC
Freq.
VBLANK
VBLANK
PULSE WIDTH
PULSE WIDTH
1
2
3
4
5
460ns
1.18µs
424ns
185ns
436ns
128µs
90.5µs
51µs
864µs
589µs
528µs
596µs
515µs
2.00µs
1.93µs
1.92µs
1.94µs
1.94µs
64µs
64µs
64µs
64µs
64µs
1µs
1µs
1µs
1µs
1µs
51.5µs
46.6µs
Mode change detection: The system provides a hardware detection of a Sync signal change and supports the user to
respond to this transition with a proper process as soon as possible. There are three kinds of detection that will set the
INTMUTE bit.
Hsync counter: Users can enable the HDIFF comparison by clearing the ENHDIFF bit and then preloading a different value
to the HDIFF0-3 bits in the AUTOMUTE control register ($000E). The system will latch the new value of theHsync counter
and compare it with the last latched value. If this difference is great than the user defined value at theHDIFF0-3 bits then the
system will set the INTMUTE interrupt bit.
H/V polarity: Users can enable polarity detection by clearing the ENPOL bit. The system will set the INTMUTE bit when the
polarity of Hsync or Vsync have been changed.
H/V counter overflow: Users can enable the detection of sync counters overflow by clearing the ENOVER bit. The system
will set the INTMUTE bit whenever the counter of Hsync or Vsync has overflowed.
The above three sources of setting this INTMUTE bit can be enabled or disabled by user. If the user opens this interrupt and
this interrupt event occured, the system will generate a NMI interrupt to remind users any time. At the user's manipulation, a
software debounce to confirm the transition of a sync signal one more time will make the frequency detection more stable
and reliable, but it will affect the response time. After the system reset, this 'automute' function will be disabled and the
HDIFF0~2 control bits will be cleared to ' $0F'.
HALFHI
HALFHO: Half freq. Output signal (50% duty)
HALFHO output signal when NOHALF bit clear to LOW
(the same signal as in the HALFHI pin)
Figure 13.7. Half Freq. Sync. Waveform
30
NT68F62
(1)
(2)
Figure 13.8. Two Types of Testing Pattern
64µs
VSYNC
Video
Back-Porch
Front-Porch
µ
1 s
HSYNC
Video
Back-Porch
Front-Porch
Figure 13.9. The Porch of the Free Running Self Test Pattern
31
NT68F62
13.3 Power Saving Mode detect:
Video modes are listed below, especially from mode 2 to mode 4 just for power saving. All of the modes can be easily
detected by NT68F62 (Figure 13.6).
Mode
(1) Normal
H-Sync
Active
V-Sync
Active
(2) Stand-by
(3) Suspend
(4) Off
Inactive
Active
Inactive
Active
Inactive
Inactive
Control Bit Description:
Addr.
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Registers for Synprocessor
$0006
SYNCON
FFH
FFH
R
―
―
―
―
―
―
―
―
―
―
―
INSEN
HSEL
S/ C
W
INSEN
HPOLI
―
ENHSEL
VPOLI
―
HSEL
S/ C
$0007
HV CON
FFH
FFH
HSYNCI VSYNCI
HPOLO
HPOLO
VPOLO
VPOLO
R
W
―
―
ENHOUT
HCL7
ENVOUT
HCL6
―
$0008
$0009
HCNT L
HCNT H
00H
00H
HCL5
HCL4
HCL3
HCH3
HCL2
HCH2
HCL1
HCH1
HCL0
HCH0
R
R
HCNTOV
―
―
CLRHOV
VCL7
W
R
―
―
―
―
―
―
―
$000A
$000B
VCNT L
VCNT H
00H
00H
VCL6
―
VCL5
VCH5
VCL4
VCH4
VCL3
VCH3
VCL2
VCH2
VCL1
VCH1
VCL0
VCH0
VCNTOV
CLRVOV
R
W
―
―
―
―
―
―
―
―
―
―
$000C
$000D
$000E
FREECON
HALFCON
AUTOMUTE
FFH
FFH
FFH
W
W
W
ENPAT
ENHALF
ENHDIFF
PAT0
NOHALF
ENPOL
FREQ2
FREQ1
FREQ0
HALFPOL
ENOVER
―
―
―
―
―
―
HDIFFVL3 HDIFFVL2 HDIFFVL1 HDIFFVL0
32
NT68F62
14. Base Timer (BT)
The BASE TIMER is an 8-bit counter, and its clock source
can be chosen from 1µs or 1ms by setting the BTCLK bit
('0' for 1µs and '1' for 1ms). The BT can be enabled or
disabled by the ENBT bit in the BTCON register. The BT
will start counting while clearing the ENBT bit to ‘0’. After
preloaded with a value by writing a value to the BT register
(write only) at any time and then the BT will start to count
up from this preloaded value. When the BT’s value reaches
FFH, it will generate a timer interrupt if the timer interrupt is
enabled, and then the counter will wrap around to 00H. The
timer’s maximum interval is 256ms or 256µs depending on
the BTCLK value.
the chip is reset, the BTCLK and ENBT bits are set to '1'
(the BT is disabled). Before enabling the BT, it can be
1us
0
1ms
BT7 BT6 BT5 BT4 BT3 BT2 BT1 BT0
INTMR INT
1
BTCLK
Control Bit Description:
Addr.
$002E
$002F
Register
BT
INIT
00H
03H
Bit7
BT7
―
Bit6
BT6
―
Bit5
BT5
―
Bit4
BT4
―
Bit3
BT3
―
Bit2
BT2
―
Bit1
Bit0
R/W
W
BT1
BT0
BT CON
W
BTCLK
ENBT
33
NT68F62
15. IIC Bus Interface: DDC1 & DDC2B Slave Mode
Interface: IIC bus interface is a two-wire, bi-directional
serial bus which provides a simple, efficient way for data
communication between devices, and minimizes the cost of
connecting among various peripheral devices. NT68F62
provides two IIC channels. Both of them are shared with I/O
pins and their structures are open drain. When the system
is reset, these channels are originally of general I/O pin
structure. All of these IIC bus functions will be activated
Data transfer: At first, the user must put one byte of
transmitted data into the CH0/1TXDAT register in advance,
and activate the IIC bus by setting the ENDDC bit to '0'.
Then open the INTTX0/1 interrupt source by setting
INTTX0/1 to '1' in the IEIRQ0/1 registers. On the first 9
rising edges of Vsync, the system will shift out invalid bits in
the shift register to the SDA pin to empty the shift register.
When the shift register is empty and on the next rising edge
of Vsync, it will load data from the CH0/1TXDAT registers
to the internal shift register. At the same time, the NT68F62
will shift out the MSB bit and generate an INTTX0/1
interrupt to remind the user to put the next byte data into
the CH0/1TXDAT register. After eight rising clocks, there
will have been eight bits shifted out in proper order and shift
register will become empty again. At the ninth rising clock,
it will shift the ninth bit (null bit '1') out to the SDA. And on
the next rising edge of Vsync clock, the system will
generate an INTTX0/1 interrupt again. In the same way, the
NT68F62 will load new data from the CH0/1TXDAT
registers to the internal shift register and shift out one bit
right away. Beware: the user should put one new data into
the CH0/1TXDAT registers before the shift register is empty
(the next INTTX0/1 interrupt). If not, the hardware will
transmit the last byte of data repeatedly.
only after their ENDDC bits are cleared to '0' (CH0/1CON
registers).
DDC1 & DDC2B+ function: Two modes of operation have
been implemented in the NT68F62, uni-directional mode
(DDC1 mode) and bi-directional mode (DDC2B+ mode).
These channels will be activated as DDC1 function initially
when users enable the DDC function. These channels will
switch automatically to DDC2B+ function from DDC1
function when a low pulse greater than 500ns is detected
on the SCL line. Users can start a master communication
directly from the DDC1 communication by clearing the
MODE bit in the CH0/1CLK control register.
The channels can return to DDC1 function when users set
the MD1/ 2 bit to '1' in the CH0/1CON registers.
Vsync clock: Only in the separate SYNC mode can the
Vsync pulse be used as a data transfer clock and its
frequency can be up to 25KHz maximum. In composite
Vsync mode, NT68F62 can not transmit any data to the
SDA pin, regardless of whether the Vsync can be extracted
from the composite Hsync signal.
15.1. DDC1 bus interface
Vsync input and SDA pin: In DDC1 function, the Vsync pin
is used as an input clock pin and the SDA pin is used as a
data output pin. This function comprises two data buffers:
one is the preloading data buffer for putting one byte data
in advance by the user (CH0/1TXDAT), and the other is the
shift register for shifting out one bit data to the SDA line,
which users can not access directly. These two data buffers
cooperate properly. For the timing diagram please refer to
Figure 15.1. After the system resets, the IIC bus interface is
in DDC1 mode.
34
NT68F62
Control Bit Description:
Addr.
Register
INIT
Bit7
―
―
―
―
―
―
―
―
―
Bit6
―
―
―
―
―
―
―
―
―
Bit5
―
Bit4
―
Bit3
―
Bit2
―
Bit1
Bit0
R/W
$0016
NMIPOLL
00H
INTE0
INTMUTE
CLRMUTE
IRQ0
R
CLRE0
IRQ1
W
R
―
―
―
―
$0017
$0019
$001A
$001C
IRQPOLL
IEIRQ0
IEIRQ1
IRQ0
00H
00H
00H
00H
IRQ2
INTRX0
INTRX1
INTRX0
―
―
―
INTS0
INTS1
INTS0
CLRS0
INTS1
CLRS1
INTA0
INTA1
INTA0
INTTX0
INTTX1
INTTX0
INTNAK0 INTSTOP0
INTNAK1 INTSTOP1
INTNAK0 INTSTOP0
RW
RW
R
CLRA0 CLRTX0
INTA1 INTTX1
CLRA1 CLRTX1
CLRRX0 CLRNAK0 CLRSTOP0
INTRX1 INTNAK1 INTSTOP1
CLRRX1 CLRNAK1 CLRSTOP1
W
$001D
IRQ1
00H
R
W
Control Register for DDC1/2B+ of Channel 0
$0021
$0022
$0023
$0024
CH0ADDR
CH0TXDAT
CH0RXDAT
CH0CON
A0H
00H
00H
E0H
ADR7
TX7
ADR6
TX6
ADR5
TX5
RX5
―
ADR4
TX4
ADR3
TX3
ADR2
TX2
RX2
―
ADR1
TX1
W
W
R
―
TX0
RX0
―
RX7
RX6
RX4
RX3
RX1
START
STOP
TXACK
W
ENDDC MD1/ 2
START
STOP
RXACK
R
―
―
―
―
SRW
$0025
CH0CLK
FFH
DDC2BR2 DDC2BR1 DDC2BR0
W
―
―
MODE
MRW
RSTART
Control Register for DDC1/2B+ of Channel 1
$0026
$0027
$0028
$0029
CH1ADDR
CH1TXDAT
CH1RXDAT
CH1CON
A0H
00H
00H
E0H
ADR7
TX7
ADR6
TX6
ADR5
TX5
RX5
―
ADR4
TX4
ADR3
TX3
ADR2
TX2
RX2
―
ADR1
TX1
W
W
R
―
TX0
RX0
―
RX7
RX6
RX4
RX3
RX1
START
STOP
TXACK
W
ENDDC MD1/ 2
START
STOP
RXACK
R
―
―
―
―
SRW
$002A
$003E
CH1CLK
ISP REG
FFH
DDC2BR2 DDC2BR1
DDC2BR0
W
―
―
MODE
MRW
RSTART
00H
03H
ISP
DDC1_ISP DDC0_ISP
CH1_A0 CH0_A0
R
W
35
NT68F62
ENDDC
(in CH0CON register)
●
●
●
Vsync Pulse
●
●
●
9
1
2
3
4
5
6
7
8
9
1
2
1
2
3
4
●
●
●
●
●
●
INTV
Load data in the CH0TXDAT
register to shift register
●
●
●
INTTX
●
●
●
User can load next byte data
to CH0TXDAT register
●
●
●
Null
Bit
Null
Bit
●
●
●
●
●
●
8
7
6
5
1
8
7
6
5
4
3
2
1
8
7
SDA
Invalid data
Second Byte Data
Shift
8
7
6
5
4
3
2
1
register
MSB
LSB
First Byte Data
Figure 15.1. DDC1 Mode Timing Diagram
15.2. DDC2B + Slave & Master Mode Bus Interface
The built-in DDC2B+ IIC bus Interface features are as follows: 1. After entering into DDC1 function and clearing this bit,
SLAVE mode (NT68F62 is addressed by a master that
the system will be changed from DDC1 to DDC2B+
MASTER mode operation.
drives SCL signal)
- MASTER mode (NT68F62 addresses external
devices and sends out the SCL clock)
- Compatible with IIC bus standard
2. After entering into DDC2B+ slave mode function and
clearing this bit, the system will be changed from slave
mode into master mode operation.
- One default $A0 slave address ( can be disabled ) and
one user programmable address
During clearing of the MODE bit, the system will send out a
'START' condition and wait for the user to put the calling
address into the CH0/1TXDAT control register. Notice: the
user must predetermine the direction of the master mode
transmission before putting the calling address.
- Automatic wait state insertion
- Interrupt generation for status control
- Detection of START and STOP signals
The DDC2B+ will be activated as SLAVE mode initially.
Users can switch to MASTER mode by clearing the MODE
bit under either of these conditions listed as follows:
Below is the DDC2B+ function with channel 0, and the
manipulation of channel 1 is the same as channel 0.
36
NT68F62
STOP
START
CONDITION
CONDITION
SDA
●
●
●
●
●
●
● ● ●
8
9
1 - 7
8
9
1 - 7
8
9
1 - 7
SCL
ACK
ADDRESS
R/W
ACK
DATA
ACK
DATA
IIDAT Reg.
bit stream
●
●
●
●
●
●
4
ACK
8
7
6
5
1
8
7
6
5
4
3
2
1
8
7
ACK
MSB
MSB
LSB
LSB
MSB
Figure 15.2. DDC2B Data Transfer
37
NT68F62
S
Address
R/W
0
A
DATA
A
DATA
A
DATA
A
P
Data transferred
from external device
From external device to NT68F62
A = Acknowledge
S = START
P = STOP
From NT68F62 to external device
(a) WRITE Mode Data Format
wait
wait
wait
SCL
R/W
START
STOP
SDA
(external device)
DATA
1 0 1 0
0
0 0
DATA
DATA
0
INTS
INTA
INTRX
SDA
(NT68F62)
A
A
A
A
(b) WRITE Mode Timing Diagram
Figure 15.3. DDC2B Write Mode Spec.
38
NT68F62
S
NT68F62 Address
R/W
1
A
DATA
A
DATA
A
DATA
A
P
Data transferred
from NT68F62
From external device to NT68F62
A = Acknowledge
A = No acknowledge
S = START
P = STOP
From NT68F62 to external device
(a) Read Mode Data Format
wait
wait
wait
SCL
SDA
STOP
START
R/W
(external device)
1
1
0
0
0
0
0
1
A
A
INTS
INTA
INTTX
user load first data into TXDAT buffer
SDA
(NT68F62)
A
DATA
DATA
(b) READ Mode Timing Diagram
Figure 15.4. DDC2B Read Mode Spec.
39
NT68F62
15.3. DDC2B Slave Mode Bus Interface
and stores in the CH0RXDAT register. The system
indicates the data transfer direction. The NT68F62
supports the 'A0' default address and another set of
addresses that can be accessed by writing to the
CH0ADDR register. The ‘A0’ default address of the DDC
channel 0 or 1 can be disabled by bit0 or bit1 at the
CH0/1_A0 control register ($3E). Upon receiving the calling
address from an external device, the system will compare
this received data with the default 'A0' address (if it is not
disabled) and the data in the CH0ADDR register. If either of
these addresses matches, the system will set the INTA0 bit
in the IRQ0 register. If the user sets the INTA0 bit to '1' (in
the IEIRQ0 register) in advanced and addresses match, the
NT68F62 will generate an INTA0 interrupt. Under the
address matching condition, the NT68F62 will send an
acknowledgement bit to an external device. If the address
does not match, the NT68F62 will not generate the INTA0
interrupt and will neglect the data change on the SDA line
in the future.
Enable IIC and INTS: After the user clears the ENDDC to
‘0’, NT68F62 will enter into DDC1 mode, and it will switch
to DDC2B SLAVE mode when a low pulse is detected on
the SCL line. The DDC2B bus consists of two wires, SCL
and SDA; SCL is the data transmission clock and SDA is
the data line. NT68F62 will remind the user that the mode
has changed by generating an INTS interrupt. When users
2
set MD1/ to '1' at this time, the NT68F62 will return back
to DDC1 mode. (For DDC2B please refer to Figure 15.2.)
The figure exhibits what isimportant in IIC: START signal,
slave ADDRESS, transferred data (proceed byte by byte)
and a STOP signal.
Start condition: When SCL & SDA lines are at HIGH state,
an external device (master) may initiate communication by
sending a START signal (defined as SDA from high to low
transition while SCL is at high state). When there is a
START condition, NT68F62 will set the 'START' bit to '1'
and the user can poll this status bit to control the DDC2B
transmission at any time. This bit will stay as '1' until the
user clears it. After sending a START signal for DDC2B
communication, an external device can repeatedly send a
start condition without sending a STOP signal to terminate
this communication. This is used by the external device to
communicate with another slave or with the same slave in a
different mode (Read or Write mode) without releasing the
bus.
Data transmission direction: In the INTA0 interrupt servicing
routine, the user must check the LSB of the address data in
the CH0RXDAT register. According to the IIC bus protocol,
this bit indicates the DDC2B data transfer direction in later
transmission; '1' indicates a request for a 'READ MODE'
action (external master device read data from system), '0'
indicates a 'WRITE MODE' action (external master device
write data to system). For the timing about READ mode
and WRITE mode please refer to Figure 15.3 and Figure
15.4. The data transfer can proceed byte by byte in a
Address matched and INTA0: After the STARTcondition a
slave address is sent by an external device. When the IIC
bus interface changes to DDC2B mode, NT68F62 will act
as a receiver first to receive this one byte data. This
address data is 7 bits long followed by the eighth bit (R/W)
that the system receives as an address data from an
external device,
direction specified by the R/ W bit after a successful slave
address is received.
The system will switch to either 'READ' mode or 'WRITE'
mode automatically whichever is determined by this
direction bit.
INTSTOP
STOP Detector
TXDAT
SDA
INTTX
in9 bits Shift Registerout
TXACK
INTNAK
clk
VSYNC
SCL
ENDDC
INTRX
RXDAT
INTS
INTA
R/W
Compare Logic
ADDR
MD1/2
MODE
DDC2BR [2..0]
Clock Generator
Figure 15.5. DDC Structure Block
40
NT68F62
Data transfer and wait: The data on the SDA line must be
stable during the HIGH period of the clock on the SCL line.
The HIGH and LOW state of the SDA line can only change
when the clock signal on the SCL line is LOW. Each byte of
data is eight bits long and one clock pulse for one bit of
data transfer. Data is transferred with the most significant
bit (MSB) first. In the wired-AND connection, any slower
device can hold the SCL line LOW to force the faster
device into a waiting state. Data transmission will be
suspended until the slower device is ready for the next byte
transfer by releasing the SCL line.
The INTTX0 on the READ mode: An external device can
read data from NT68F62. During INTTX0 interrupt, the
system will load new data from the CH0TXDAT register
which the user has earlier put into this internal shift register.
Then , the system will begin to send out this new data
continually . After this newly loaded data had been shifted
out by every SCL clock, the system will request the user to
put the next byte of data into the CH0TXDAT register by
the INTTX0 interrrupt.
If both of the shift register and the CH0TXDAT register are
empty and the user still cannot load data into the
CH0TXDAT register, the NT68F62 system will let SCL pin
keep ‘LOW’ and wait the another new data after receiving
the acknowledgment bit from external device.
Acknowledge: The acknowledgment will be generated at
the ninth clock by whomever is receiving data. In the
WRITE MODE, the NT68F62 system must respond to this
When SCL is held low by the system and after the user had
put one new byte of data into the CH0TXDAT register, the
SCL will be released for generation of the SCL
transmission clock. At this time, the system will load this
byte of data into the shift register and generate an INTTX0
interrupt again to remind the user to putt the next byte into
the CH0TXDAT register. For the timing diagram refer to
Figure 15.4.
After every one byte of data transfer, the system will
monitor if the external master device has sent out the
acknowledgment bit or not. If not, the system will set the
INTNAK bit (the acknowledgment is LOW signal). Users
will get an INTNAK interrupt if the INTNAK has been
enabled as a interrupt source.
acknowledgment. Users should clear the TXACK bit in the
CH0CON to open the ‘ACK’ function. After receiving one
byte of data from the external device, NT68F62 will
automatically send this acknowledgment bit.
In the READ mode, an external device must respond to the
acknowledgment bit after every byte of data is sent out.
The system will set the INTNAK bit when the external
device does not send out the '0' acknowledgment bit.
Furthermore, the user can open this interrupt source by
clearing the INTNAK bit in the IEIRQ0 register.
The INTTX0 & INTRX0 interrupt: After NT68F62 completes
one byte transmission or receiving, it will generate INTTX0
(READ mode) & INTRX0 (WRITE mode) interrupts. These
interrupts are generated at the falling edge of the ninth
clock. Users can control the flow of DDC2B transmissions
at these interrupts.
STOP condition: When SCL & SDA lines have been
released (held on 'high' state), DDC2B data transfer is
always terminated by a STOP condition generated by an
external device. A STOP signal is defined as a LOW to
HIGH transition of SDA while SCL is at HIGH state. When
there is a STOP condition, NT68F62 will set the 'STOP' bit
& INTSTOP bit to '1' and the user can poll this status bit or
The INTRX0 on the WRITE mode: NT68F62 reads data
from the external master device. When users detect an
INTRX0 interrupt, it means that one byte of data has been
received and the user can read out by accessing the
CH0RXDAT control register. At the same time, if the user
responded to an 'ACK' signal beforehand, the shift register
will send out this 'ACK' bit (low voltage) and continue to
receive the next byte data. If both of the shift register and
the CH0RXDAT register are full and the user still does not
load data from the CH0RXDAT register, the NT68F62
system will let the SCL pin keep ‘LOW’ and will wait for
user to retrieve this collected data. After the user obtains
one byte of data from the CH0RXDAT register, the SCL will
be released for generation of the SCL transmission clock.
At this time , the external device can continue sending the
next byte of data to NT68F62. The timing diagram refers to
Figure 15.3. The user must respond with a NAK signal
beforehand to stop the transmission.
open
a
INTSTOP interrupt to control the DDC2B
transmission at any time. This bit will stay as '1' until the
user clears it by writing '1' to this bit. Notice: The SCL and
SDA lines must conform to IIC bus specifications. For the
software flowchart please refer to Figure 15.6. Please refer
to the standard IIC bus specification for details.
Change to DDC1 mode: After an external device terminates
DDC2 transmission by sending a STOP condition, users
can set MD1/ 2 to '1' for changing to DDC1 mode. On the
other hand, when the SCL line has been released (pulled-
up), the user can force NT68F62 to DDC1 mode
communication at any time.
41
NT68F62
Interrupt
IRQ0/1 Group
Service Routine
Polling
Need
Polling
Need
Polling
INTA?
Need
Polling
INTS?
Need
Polling
INTRX?
Need
No
No
No
No
No
No
No
Need
Polling
INTTX?
Polling
INTV?
INTNAK?
yes
yes
yes
yes
yes
yes
READ
Mode
WRITE
Mode
No
No
INTS
?
INTA
?
INTV
?
No
No
INTRX
?
INTTX
?
INTNAK?
yes
yes
DDC1
yes
yes
yes
DDC2
yes
Change To DDC2
Slave Mode &
Read Out the SRW bit
Reset Buffer Index
Read One Byte
Data From
Change To
DDC1 Mode
No
Trans.
Over
?
RECEIVING Mode
CH0RXDAT Reg.
(MD_CON = 1)
yes
Put Slave Addr. Into
CH0ADDR Reg.
yes
Put One Byte
Data Into
No
Recv.
Over
?
READ Mode
?
Put $FF Into
CH0TXDATReg.
CH0TXDAT Reg.
(release SDA line)
No
yes
Open
Open
INTTX & INTS
Put One Byte data Into
INTRX, INTNAK
& INTA
CH0TXDAT Reg.
No
Return to
DDC1?
No
Return to
DDC1?
Open
Other INT.
Service
Open
INTTX, INTNAK &
INTA
INTTX, INTNAK
& INTA
yes
yes
Open INTA
Transmission failed
Open
Open
Open
INTA
Open
INTA
INTA & INTV
INTA & INTV
System release SCL &
SDA & send out STOP
condition User can do
some process
Open
INTRX, INTNAK &
INTA
Return
SLAVE Mode Operation
Figure 15.6. Slave Mode INT Operation
42
NT68F62
15.4 DDC2B+ Master Mode Bus Interface
Most of the DDC manipulation is the same as SLAVE mode
except the SCL clock generation. In the MASTER mode,
the control of the SCL clock source belongs to NT68F62.
Users must set the calling address and transmission
direction in advance. Access the MODE & MRW bits to
control the transmission flow of DDC2B+ master mode
communication.
voltage) and continue to receive the next byte of data. If
both the shift register and the CH0RXDAT register are full
and the user still does not load data from the CH0RXDAT
register, the SCL will be held LOW and will wait for
NT68F62. After the user has received one byte of data
from the CH0RXDAT register, the SCL will be released for
generation of SCL transmission clock. An external device
can continue sending the next byte of data to NT68F62.
Refer to Figure 15.7 for the timing diagram. The user must
Start condition: After user clears the ENDDC & MODE
bits, the system will generate a 'START' condition on the
SCL & SDA lines and wait for the user to put the calling
address into the TXDAT buffer and send it to SDA line. The
frequency of SCL is dependant on the baud-rate setting
value (DDCBR0 - DDCBR2) in the register CH0CLK. The
respond to
a NAK signal in advance to stop the
transmission. Before the last two bytes of data are
received, the user should respond with a 'NAK' signal.
Then, the system will send out a 'NAK' bit after receiving
the last byte of data and enact the 'STOP' condition to
notify the slave that current transmission is terminated.
data transmission direction will be dependant on the MRW
bit and the LSB of the calling address, '1' for read operation
and '0' for write operation.
The INTTX0 on the WRITE mode: The external device
reads data from NT68F62. During an INTTX0 interrupt, the
system will load new data (that the user has already put
into the internal shift register) from the CH0TXDAT register
and continue sending out this new data. After this new
loading data has been shifted out by every SCL clock, the
system will request the user to put the next byte of data into
the CH0TXDAT register.
Calling address: The calling address is 8 bits long. It should
be put in the CH0TXDAT. The setting of the LSB bit in this
TXDAT buffer should be the same as the MRW bit.
STOP condition: There are several cases in which the
system will send out a 'STOP' condition on the SCL & SDA
lines. First, in the 'READ' operation, if the user sets the
TXACK bit to '1', the system will send out the 'NAK'
condition on the bus after receiving one byte of data and
will then send out the 'STOP' condition automatically later.
Second, in the 'START' condition and after the sending out
a calling address, if no slave has responded to an 'ACK'
signal, the master will send out the 'STOP' condition
If both of the shift register and the CH0TXDAT register are
empty and the user still cannot load data into the
CH0TXDAT register, the NT68F62 system will let SCL pin
keep ‘LOW’ and wait the another new data after receiving
the acknowledgment bit from external device.
If SCL is held low by the system, and the user has put one
new byte of data into the CH0TXDAT register, the SCL will
be released for generation of SCL transmission clock. At
this time, the system will load this byte of data into the shift
register and generate an INTTX0 interrupt again to remind
the user to put the next byte into the CH0TXDAT register.
Refer to Figure 15.8 for the timing diagram.
automatically. Third, if the user sets the MODE bit to '1',
the system will generate a 'STOP' condition after the
current byte transmission is done. Notice that if the slave
device did not release the SCL and SDA line, the system
can not send out the 'STOP' condition.
After the 'STOP' condition, the master will release the SCL
& SDA lines and return to SLAVE mode.
Repeat start condition: If the user clears the RSTART bit
to '0' in the ' WRITE' operation, the system will send out a
'Repeat Start'. Notice that if the slave device does not
release the SCL and SDA lines, the system can not send
out a 'REPEAT START condition.
The INTTX0 & INTRX0 interrupt: After NT68F62 completes
one byte transmission or receiving of data, it will generate
INTTX0 (WRITE mode) & INTRX0 (READ mode) interrupts.
Users can control the flow of DDC2B transmission at these
interrupts.
SCL baud rate selection: There are three Baud Rate bits for
users to select one of eight clock rates on the SCL line.
After a system reset, the default value of these Baud Rate
bits (DDC2BR0-2) are '111'.
The INTRX0 on the read mode: NT68F62 reads data from
an external slave device. When users detect an INTRX0
interrupt, it means that one byte data has been received
and the user can read out by accessing CH0RXDAT control
register. At the same time, if the user sent an 'ACK' signal
beforehand, the shift register will send out an 'ACK' bit (low
43
NT68F62
DDC2BR2
0.00
DDC2BR1
0.00
DDC2BR0
0.00
Baud Rate
400K
0.00
0.00
1.00
200K
0.00
1.00
0.00
100K
0.00
1.00
1.00
50K
1.00
0.00
0.00
25K
1.00
0.00
1.00
12.5K
6.25K
3.125K
1.00
1.00
0.00
1.00
1.00
1.00
wait
9
wait
wait
SCL
R/W
9
9
1 2
3
4
5
6
7 8
1 2 3 4 5 6 7 8
1 2
3 4 5 6 7 8
SDA
(external device
putting data)
DATA
A
DATA
DATA
MODE = 0
Wait for user to put calling address into TXDAT buffer
If user read out first byte data from RXDAT buffer,
system will respond ACK, NAK or REPeat START
STOP
START
SDA
(NT68F62)
A
A
ADDRESS
A
INTRX
Before user reads out this byte data from RXDAT buffer,
he can set TXACK = 1 to terminate communication
If user does not read out this byte data from RXDAT buffer,
the shift register will wait after receiving next byte data
Figure 15.7. DDC2B+ MASTER READ Mode Timiing
44
NT68F62
wait
wait
wait
wait
SCL
R/W
SDA
(external device)
A
A
A
MODE = 0
wait for user putting calling address into TXDAT buffer
STOP
START
1
2
3
4
5
6
7 8 9
1
2
3
4
5
6
7 8 9
1
2
3
4
5
6
7 8 9
SDA
(NT68F62)
A
ADDRESS
DATA
DATA
INTTX
If user wants to terminate this communication,
he can set MODE = 1 to send out STOP condition
or clear RSTART = 0 to send out REPEAT START
System will wait if user didn't send out the first byte
data. As user loaded one byte data into TXDAT buffer,
system will latch to shift register and send out MSB bit
right away.
After sending out first byte data, user will get another
INTTX to put next byte data into TXDAT buffer,
If user does not send out the second byte data, the
system will wait again after shifted out first byte data.
Figure 15.8. DDC2B+ MASTER WRITE Mode Timing
45
NT68F62
Control Register:
Addr
Register
INIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Control Register for Polling Interrupt Groups
$0016
NMIPOLL
00H
INTE0
INTMUTE
R
―
―
―
―
―
―
―
―
―
―
―
―
CLRE0
CLRMUT
E
W
$0017
IRQPOLL
00H
IRQ2
IRQ1
IRQ0
R
―
―
―
―
―
Control Registers of Interrupt Enable
$0018
$0019
$001A
$001B
IENMI
IEIRQ0
IEIRQ1
IEIRQ2
00H
00H
00H
00H
INTE0
INTNAK0
INTNAK1
INTE1
INTMUTE
INTSTOP0
INTSTOP1
INTMR
W
W
W
W
―
―
―
―
―
―
―
―
―
―
―
―
INTS0
INTS1
―
INTA0
INTA1
―
INTTX0
INTTX1
―
INTRX0
INTRX1
INTV
Control Registers for Polling Interrupt Requests
$001C
$001D
$001E
IRQ0
IRQ1
IRQ2
00H
00H
00H
INTS0
CLRS0
INTS1
CLRS1
―
INTA0
CLRA0 CLRTX0
INTA1 INTTX1
INTTX0
INTRX0
CLRRX0
INTRX1
CLRRX1
INTV
INTNAK0
INTSTOP0
R
W
R
―
―
―
―
―
―
―
―
―
―
―
―
CLRNAK0 CLRSTOP0
INTNAK1 INTSTOP1
CLRNAK1 CLRSTOP1
CLRA1 CLRTX1
W
R
INTADC
INTE1
INTMR
―
CLRADC
CLRV
CLRE1
CLRMR
W
―
―
Control Register for DDC1/2B+ of Channel 0
$0021
CH0ADDR
A0H
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
W
―
TX0
RX0
―
$0022
$0023
$0024
CH0TXDAT 00H
CH0RXDAT 00H
TX7
RX7
TX6
RX6
TX5
RX5
―
TX4
RX4
TX3
RX3
TX2
RX2
―
TX1
RX1
W
R
CH0CON
E0H
START
STOP
W
ENDDC
MD1/ 2
TXACK
START
STOP
R
―
―
―
―
―
SRW
$0025
CH0CLK
FFH
A0H
DDC2BR2 DDC2BR1 DDC2BR0
W
―
―
MODE
MRW
RSTART
Control Register for DDC1/2B+ of Channel 1
$0026
$0027
$0028
$0029
CH1ADDR
ADR7
TX7
ADR6
TX6
ADR5
TX5
RX5
―
ADR4
TX4
ADR3
TX3
ADR2
TX2
RX2
―
ADR1
TX1
W
W
R
―
TX0
RX0
―
CH1TXDAT 00H
CH1RXDAT 00H
RX7
RX6
RX4
RX3
RX1
CH1CON
E0H
START
STOP
W
ENDDC
MD1/ 2
TXACK
START
STOP
R
―
―
―
―
SRW
$002A
CH1CLK
FFH
DDC2BR2 DDC2BR1 DDC2BR0
W
―
―
MODE
MRW
RSTART
46
NT68F62
Master Receiver
No
Reset Buffer Index
Just Recv.
One Byte Data?
No
Yes
Last Comm,
ENDDC = 0
is Repeat Start?
Yes
After Recv. Data
Yes
Send Repeat Start?
No
No
No
Just Recv.
One Byte Data?
ENDDC = 0
Yes
Send NO_ACK
Set Last Byte Flag
Yes
After Recv. Data
Send Repeat Start?
ENDDC = 0
Send Address
No
Send Repeat Start
Set Last Byte Flag
Open INTTX & INTNAK
MODE = 0
Send NO_ACK
Send Address
Send Address
Set Last Byte Flag
Send Repeat Start
set last byte flag
Open INTTX & INTNAK
Open INTRX & INTNAK
Send Address
Open INTTX INTNAK
No
Wait INT
Recev. Over?
Yes
Return
Figure 15.9. Master Receiver Operation
Master transmitter
Reset buffer index
No
Last Comm,
is Repeat Start?
Yes
Send Address
MODE = 0
Send Repeat Start
Send Address
Open INTTX INTNAK
Open INTTX & INTNAK
No
Wait INT
Trans. Over?
Yes
Return
Figure 15.10. Master Transmitter Operation
47
NT68F62
Interrupt
IRQ0/1 Group
Service Routine
Need
Polling
INTRX?
No
Need
Polling
INTTX?
Need
Polling
No
No
No
INTNAK?
Yes
yes
Yes
No
Last two
No
No
byte data?
INTRX ?
Yes
INTNAK?
yes
INTTX?
Yes
Yes
Other interruptProcess
or Have someerror
No
No
send repeat
start?
last byte
data ?
No
No
No
Transmission failed
Last byte
Trans.?
Calling
Address?
Yes
Send repeat start
set last byte flag
Yes
Yes
Yes
Read One Byte
Data From
Send repeat start
set last byte flag
CH0RXDATReg.
No Slave Device Exist
System will send outSTOP &
set MODE bit to 1 automatically
send repeat
start?
Receiver Over
close INT interrupt
Write 1 to MODE bit
Read One Byte
Yes
(system send out a STOP)
Data From
Write 1 to MODE bit
Read One Byte
Data From
CH0RXDATReg.
(system send out a STOP)
CH0RXDATReg.
Send repeat start
Put next byte data
into
CH0TXDATReg.
Trans. over
close INT interrupt
Open INTRX & INTNAK INT
Open INTRX & INTNAK INT
Return
Figure 15.11. Master Mode INT Operation
48
NT68F62
User Referenced Flow Chart
Comparison With NT68P61A
Item
Maximum ROM Size
RAM Size
NT68P61A Status
24K Bytes
NT68F62 Status
32K Bytes
Notes
256 Bytes
512 Bytes
PWM Channel
14 channels
13 channels
5V & 12V Open Drain O/P
31.25 KHz
5V Open Drain O/P Only
62.5 KHz
PWM Channel Refresh
Rate
A/D Converter Channel
V Counter Bit No.
2 channels
12 Bits
4 channels
14 Bits
6 bit resolution
(handle Vsync freq. down
to 30.5Hz)
(handle Vsync freq. down
to 7.6Hz)
H Interval
8.192 ms
16.384 & 32.768 ms
Auto Mute
X
2 sets
X
O
5 sets
O
Free Run Freq.
Self Test Pattern
IIC Bus Channel
IIC Bus Baud Rate
IIC Mode Supported
External Interrupt
NMI Interrupt
2 self test patterns
1 channel
Max 100KHz
DDC1/2B
1 set
2 channels
Max 400KHz
DDC1/2B+
2 sets
O
X
Interrupt Trigger Edge
Programmable
X
O
MASK ROM option
24K
32K
49
NT68F62
°
DC Electrical Characteristics (VDD = 5V, TA = 25 C, Oscillator freq. = 8MHz, Unless otherwise specified)
Symbol
IDD
Parameter
Operating Current
Min.
Typ.
Max.
Unit
mA
V
Conditions
20
No Loading
VIH1
Input High Voltage
2
P00-P07, P12-P16,
P20-P27, P40, P41
RESET , HALFHI INTE0, INTE1
VIH2
VIL1
Input High Voltage
Input Low Voltage
3
V
V
SCL0/1, SDA0/1,P10, P11, P30, P31 pins
0.8
P00-P07, P12-P16,
P20-P27, P40, P41
RESET , HALFHI, INTE0, INTE1
VIL2
IIH
Input Low Voltage
Input High Current
1.5
V
SCL0/1, SDA0/1, P10, P11 P30 ,P31 pins
-200
-350
P00-P07, P10-P16,
P20-P27, P40,P41
µA
VSYNCI, HSYNCI, HALFHI, RESET
(VIH=2.4V);
VOH1
Output High Voltage
2.4
V
P00-P07, P10-P16, P40,
P41 (IOH = -100µA)
VSYNCO, HSYNCO (IOH = -4mA)
HALFHO (IOH = -4mA)
PATTERN, P20-P27 (IOH = -10mA)
External applied voltage
VOH2
VOL
Output High Voltage
(DAC0-DAC12)
5
V
V
Output Low Voltage
0.4
P00-P07, P10-P16, P40,
P41, DAC0-12 (IOL= 4mA)
SCL0/1, SDA0/1 (IOL= 5mA)
VSYNCO, HSYNCO (IOL = 4mA)
HALFHO (IOL = 4mA)
PATTERN, P20-P27 ( IOL= 10mA)
ROL
Pull Down Resistor ( RESET)
25
11
50
22
KΩ
KΩ
ROH1
Pull up Resistor
(INTE0, INTE1)
33
33
ROH2
Pull up Resistor
11
22
KΩ
(PORT0, PORT1, & PORT4)
VIH
VIL
Input High Voltage
2.2
1.2
V
V
V
V
HSYNCI,VSYNCI
Input Low Voltage
VjitterH
VjitterL
Input Jitter Low Voltage
Input Jitter High Voltage
1.6
1.0
2.0
1.4
HSYNCI
HSYNCI
50
NT68F62
HSI
VIH = 2.2V
VjitterH = 1.8V
VjitterL = 1.2V
VIL = 0.8V
HSO
51
NT68F62
°
AC Electrical Characteristics (VDD = 5V, TA = 25 C, Oscillator freq.= 8MHz, unless otherwise specified)
Symbol
Fsys
Parameter
System Clock
Min.
Typ.
Max.
Unit
MHz
µs
Conditions
8
tCNVT
A/D Conversion Time
A/D Converter Error
750
1
Voffset
Vlinear
LSB
V
A/D Input Dynamic Range of
Linearity Conversion
1.5
3.5
tDELAY
The Delay Time of Vsync input
and Vsync output
20
ns
Composite sync with fixed
delay (Refer Figure 13.5)
tRESET
Fvsync
tVPW
Reset Pulse Width Low
Vsync Input Frequency
Vsync Input Pulse Width
Hsync Input Frequency
2
8
tCYCLE
Hz
tCYCLE = 2/ Fsys
25K
300
120
7
tVSYNC = 1/Fvsync
8
µs
Fhsync
tHPW1
30
0.25
KHz
µs
tHSYNC = 1/Fhsync
Maximum Pulse Width of Hsync
Input High (Positive Polarity)
tHPW2
Minimum Pulse Width of Hsync
Input Low (Positive Polarity)
9.125
µs
µs
tERROR1
tERROR2
Counting Deviation of Base
Timer
1
1
1µs clock source
Counting Deviation of Base
Timer
ms
1ms clock source
52
NT68F62
DDC1 Mode
Symbol
tVPW
Parameter
Vsync High Time
Min.
0.50
Typ.
Max.
300
Unit
µs
Conditions
Fvsync
tDD
Vsync Input Frequency
Data Valid
32
25K
500
500
Hz
ns
ns
tVSYNC =1/Fvsync
200
tMODE
Time for Transition to DDC2B
Mode
SCL
t
MODE
t
DD
SDA
Bit 0
Null Bit
Bit 7
Bit 6
VSYNC
t
VPW
Composite
●
● ●
Hsync Input
tHPW2
tHPW1
Extracted
Vsync Output
tDELAY
53
NT68F62
DDC2B+ Mode
Symbol
Parameter
Min.
Typ.
Max.
Unit
fSCL
tBUF
SCL Clock Frequency
400
KHz
Bus Free Between a STOP and START Condition
Hold Time for START Condition
LOW Period of the SCL Clock
4.7
0.8
1.3
0.8
1.3
200
300
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
tHD; STA
tLOW
tHIGH
HIGH Period of the SCL Clock
tSU; STA
tHD; DAT
tSU; DAT
tR
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Rising Time of Both SDA and SCL Signals
Falling Time of Both SDA and SCL Signals
Set-up Time for STOP Condition
1
tF
300
tSU; STO
0.80
SDA
SCL
t
BUF
t
F
t
LOW
t
R
t
HD; STA
t
SU; STA
t
HD; STA
t
HD; DAT
t
SU; DAT
tSU; STO
t
HIGH
STOP
START
STOP
START
54
NT68F62
Ordering Information
Part No.
NT68F62
NT68F62U
Packages
40L P-DIP
42L S-DIP
55
NT68F62
Package Information
P-DIP 40L Outline Dimensions
unit: inches/mm
D
40
21
20
1
E
S
Base Plane
Seating Plane
B
e
A
a
e1
B1
Symbol
Dimensions in inches
0.210 Max.
Dimensions in mm
5.33 Max.
A
A1
A2
0.010 Min.
0.155±0.010
0.25 Min.
3.94±0.25
B
B1
C
0.018 +0.004
-0.002
0.46 +0.10
-0.05
0.050 +0.004
-0.002
1.27 +0.10
-0.05
0.010 +0.004
-0.002
0.25 +0.10
-0.05
D
E
2.055 Typ. (2.075 Max.)
0.600±0.010
52.20 Typ. (52.71 Max.)
15.24±0.25
E1
e1
L
0.550 Typ. (0.562 Max.)
0.100±0.010
13.97 Typ. (14.27 Max.)
2.54±0.25
0.130±0.010
3.30±0.25
α
0° ~ 15°
0° ~ 15°
eA
S
0.655±0.035
0.093 Max.
16.64±0.89
2.36 Max.
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E1 does not include resin fins.
3. Dimension S includes end flash.
56
NT68F62
Package Information
S-DIP 42L Outline Dimensions
unit: inches/mm
D
42
22
21
pin 1 index
1
ME
Z
Base Plane
Seating Plane
e
MH
1
b1
b
e
Symbol
Dimensions in inches
0.200 Max.
0.020 Min.
0.157 Max.
0.051 Max.
0.031 Min.
0.021 Max.
0.016 Min.
0.013 Max.
0.010 Min.
1.531 Max.
1.512 Min.
0.551 Max.
0.539 Min.
0.070
Dimensions in mm
A
A1
A2
b
5.08 Max.
0.51 Min.
4.0 Max.
1.3 Max.
0.8 Min.
0.53 Max.
0.40 Min.
0.32 Max.
0.23 Min.
38.9 Max.
38.4 Min.
14.0 Max.
13.7 Min.
1.778
15.24
3.2 Max.
2.9 Min.
15.80 Max.
15.24 Min.
17.15 Max.
15.90 Min.
0.18
b1
c
D(1)
E(1)
e
e1
L
0.600
0.126 Max.
0.114 Min.
0.622 Max.
0.600 Min.
0.675 Max.
0.626 Min.
0.007
ME
MH
w
Z(1)
0.068 Max.
1.73 Max.
Notes:
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
57
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