PEF24911 [ETC]
ISDN Line Interface ; ISDN线路接口
| 型号： | PEF24911 |
| 厂家： | 
ETC |
| 描述： | ISDN Line Interface
|
| 文件： | 总13页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Delta Sheet
DS 6, 2000-12-01
Quad ISDN 2B1Q Echocanceller Digital Front End
DFE-Q V2.1
PEF 24911 Version 2.1
This Delta Sheet lists the add-on features and differences between the DFE-Q V2.1
and the DFE-Q V1.3.
1
Power Supply
The DFE-Q V2.1 requires a +3.3 V ±0.3 V power supply. The inputs and outputs remain
5 V TTL compatible.
•
Table 1
Mode
Power Consumption
Typ. values Max. values Unit
Test conditions
Power-up
85
100
mA
3.3 V, open outputs,
all Channels
inputs at VDD /V
SS
Power-down
35
t.b.d.
mA
3.3 V, open outputs,
inputs at VDD /V
SS
All measurements of the power consumption are performed with random 2B+D data in
active states, 3.3 V (0° C - 70° C)
PEF 24911
Revision History:
2000-12-01
DS 6
DS 5
Previous Version:
09.00
Major changes since last revision:
MTO Function removed
State Diagram updated
Previous Version:
06.00
DS 4
Major changes since revision 05.99:
Typical values of Power Consumption added
Delay for Recognition of C/I code changed 2nd time
MON 8 Messages in State ’Reset’
Delta Sheet
2000-12-01
PEF 24911
Pinning
2
Pinning
Table 2 lists the changes that were made concerning the pinning, Table 3 specifies new
pin functions that were introduced with version 2.1.
Table 2
Pin No.
32
Pinning Changes
V2.1
V1.3
Comment
PUP
N.C.
additional push-pull mode for pin
DOUT eases interface adaptation
36
55
45
n.c.
DSYNC
SLOT
N.C.
obsolete
renamed
SLOT0
SLOT1
increased max data rate (4 MBit/s)
requires an additional SLOT pin
53
56
LT
LT
dedicated LT mode pin is obsolete
SSP
TSP
dedicated pin for ’Send Single
Pulses’ test mode
58
62
PBX
DT
PBX
TP
function removed
dedicated pin for ’Data Through’
test mode
63
TRST
TP1
BScan power-on-reset is replaced
by a dedicated reset line
Delta Sheet
2
2000-12-01
PEF 24911
Pinning
Table 3
Pin No.
Pin Definitions and Functions
Symbol Input (I) Function
Output (O)
32
55
45
PUP
I
Push Pull Mode
(PD)
in push pull mode ’0’ and ’1’ is actively driven
during an occupied time-slot, outside the
active time-slots DOUT is high impedance
(tristate)
’1’= configures DOUT as push/pull output
’0’= configures DOUT as open drain output
SLOT0
I
IOM®-2 Channel Slot Selection 0
assigns IOM®-2 channels in blocks of 4
SLOT1, 0:
’00’= IOM®-2 channels 0 to 3
’01’= IOM®-2 channels 4 to 7
’10’= IOM®-2 channels 8 to 11
’11’= IOM®-2 channels 12 to 15
SLOT1
I
IOM®-2 Channel Slot Selection 1
(PD)
assigns IOM®-2 channels in blocks of 4
53
56
LT
I
I
reserved, clamp to one
SSP
Send Single Pulses (SSP) Test Mode
enables/disables SSP test mode
’1’= SSP test mode enabled,
alternating +/-3 pulses are issued at the four
line ports in 1.5 ms intervals
’0’= SSP test mode disabled
58
PBX
I
reserved, clamp to zero
Delta Sheet
3
2000-12-01
PEF 24911
Pinning
Table 3
Pin No.
Pin Definitions and Functions (cont’d)
Symbol Input (I)
Output (O)
Function
62
DT
I
Data Through (DT) Test Mode
enables/disables DT test mode
’1’= DT test mode enabled,
the U-transceiver is forced on all line ports to
enter the ’Transparent’ state
’0’= DT test mode disabled
63
TRST
I
JTAG Boundary Scan Disable
(PU)
resets the TAP controller state machine
(asynchronous reset), internal pullup
’1’= reset inactive
’0’= reset active
PU:Pull Up
PD:Pull Down
Delta Sheet
4
2000-12-01
PEF 24911
Max. Data Rate On IOM®-2 Doubled
48 47 46 45 44 43 42 41 40 39 3837 36 3534 33
49
CRCON
32
31
30
29
28
27
26
PUP
D1A
D0A
CLS0
ST00
50
51
D2D
D3D
CLS2
52
53
54
55
56
LT
VDD
ST01
ST10
VSS
SLOT0
SSP
VSS
25
24
23
22
P-MQFP-64
57
58
59
60
61
ST11
ST20
VDD
PBX
AUTO
RES
CLS3
21
20
19
18
17
ST21
CLS1
ST30
ST31
62
63
64
DT
TRST
TCK
SDX
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16
pinning.emf
Figure 1
Pin Diagram of the DFE-Q V2.1
3
Max. Data Rate On IOM®-2 Doubled
With version 2.1 the maximum data rate on IOM®-2 is doubled from 2 MBit/s to 4MBit/s.
The 4MBit/s mode corresponds to a DCL frequency of 8192 kHz.
Delta Sheet
5
2000-12-01
PEF 24911
MON-12 Protocol
4
MON-12 Protocol
MON-12 commands feature via the IOM®-2 Monitor channel direct access to the device
internal register map. The MON-12 protocol works in the manner of a serial
microprocessor interface.
New functions such as digital local loopbacks, BER measurement etc. are only
accessible via MON-12 commands. Functions that were so far provided via MON-8
commands, e.g. FEBE/NEBE counter status retrieval, can be accessed as well via the
MON-12 protocol. For a detailed description of the register set please refer to the data
sheet of the DFE-Q V2.1
5
Bit Error Rate Measurement
For bit error rate monitoring the DFE-Q V2.1 features an 16-bit Bit Error Rate counter
(BERC) per line. As soon as the BER function is enabled zeros are sent in the selected
channels and incoming ones are counted until the BER function has been disabled again
by the user.
6
Advanced Filter Options for MON-0 and MON-2
Messages
Additionally to the existing mode pins, AUTO and CRCON, the internal MFILT register
provides a wide range of filter options for the passing on of MON-0 and MON-2
messages. The new MON-12 protocol gives access to the MFILT register. The following
options are provided,
– MON-0:
Transparent, On Change, TLL
TLL (Triple-Last-Look)
On Change, TLL, CRC, CRC & TLL
On Change, TLL, CRC, CRC & TLL
in transparent mode
in automode
– MON-2:
vs. IOM®-2
vs. State Machine
7
Digital Local Loops
Besides the remote loopback stimulation and the local analog loopback (C/I= ARL) the
DFE-Q V2.1 features digital local loopbacks via its internal register set. The local
loopbacks that are additionally provided by the LOOP register are shown in Figure 2.
The local loops can be activated at any time independent of the current activation status
using the MON-12 protocol.
Delta Sheet
6
2000-12-01
PEF 24911
Digital Local Loops
LOOP.LB1=1 or
LOOP.LB2=1 or
LOOP.LBBD= 1
&
LOOP.LB1=1 or
LOOP.LB2=1 or
LOOP.LBBD= 1
&
LOOP.U/IOM=
0
LOOP.U/IOM=
1
DFE-Q V2.1
DSP
U Protocol Processing Unit
SIU
2B1Q
Encod e r
Scrambler
U Fram ing
Echo
Canceller
IOM®-2
A
G
C
2B1Q
Decoder
PDM
Filter
De-
Scrambler
U De-
Fram ing
+
Eq ualiz e r
System
Interface
Unit
Timing
Recovery
Activation/Deactivation
Controller
LOOP.DLB= 1
DFE-Q V2.1
DSP
U Protocol Processing Unit
SIU
2B1Q
Enco de r
Scrambler
U Fram ing
IOM®-2
Echo
Canceller
System
Interface
Unit
A
G
C
PDM
Filter
2B1Q
Decoder
De-
Scrambler
U De-
Fram ing
Equalizer
+
Timing
Recovery
Activation/Deactivation
Controller
loopreg.emf
Figure 2
Loopbacks Featured by Register LOOP
Delta Sheet
7
2000-12-01
PEF 24911
D-Channel Arbitration
8
D-Channel Arbitration
D-channel arbitration is not supported by version 2.1.
9
C/I code ’LTD’ omitted
The C/I command ’LTD’ is no more supported, since the LTD function corresponds to
that of C/I ’RES’. Upon C/I ’RES’ the DFE-Q V2.1 stops transmitting signals on U and
ignores wake-up signals.
On contrast to the DFE-Q V1.x the relay driver and status pins are not affected by the
software reset C/I ’RES’ in version 2.1. The relay driver and status pins are only reset by
a hardware reset.
10
State Machine
Some minor changes were made regarding the state machine. The improvements are
summarized and listed in Table 4. See also the state diagrams in Figure 3 (V2.1) and
Figure 4 (V1.3).
Delta Sheet
8
2000-12-01
PEF 24911
State Machine
TN & ( AR or AR0 or
ARX or UAR or DC)
Pin-RES or
C/I= ’RES’
DR
.
.
SL0
SL0
Reset
DEAC
Deactivated
DI
ARL
T2S
T1S, T2S
T1S, T2S
( AR or AR0 or
ARX or UAR )
& /TN
.
.
SL0
TL
T2E
Reset for Loop
DI
Alerting
DI
RES1
Pin-SSP or
C/I= ’SSP’
DR
T2E
T3S
T2S
.
SP/SL0
T3E
.
Test
DEAC
RES1
T1E
SL0
Wait for TN
DI
TN
T4S, T1S
.
T1S
T4S,
.
SL0
SL0
T9S, T4S
Awake Error
AR
Awake
AR
LSEC or
T4E
(T9E & LSEC)
or T4E
T5S
.
SL1
.
T1S, T5S
SL0
EC-Training
Alerting_Error
RES1
AR
EI3
LSEC or T5E
SL2
T6S
a=0,d=1
EC-Converged
ARM
SEC or T6E or ARL
T2S
RES1
SL2
a=0,d=1
EQ-Training
(/T1E or ARX) & SFD &
(BBD0 or BBD1 or
CRCOK)
ARM
EI 3
T1E
SL3T**) a=0,d=1
SL3T a=1,d=1
DR or LOF
or LSUE
T8S
Pend.Transparent
Line Active
UAI/FJ
DR or LOF
or LSUE
act =1 & /AR0
sai=0 & act=0
UAI, FJ
T8E
UAR
Any State
Pin-DT or DT
AR0
AR0
a=0,d=1
SL3T
a=1,d=1
SL3T
DR or LOF
or LSUE
DR or LOF
or LSUE
Transparent
AI/FJ EI2/FJ
S/T Deactivated
sai=1
act=0
act=1
AR/FJ
UAI/FJ
sai=0
DR T10S
LOF
LSUE
a=0,d=1
SL3T a=0,d=1
Loss of Synchr.
SL3T a=0,d=0
SL3T
Pend. Deactivation
Loss of Signal
RSY
RES1
DEAC
LSL
RES1
T10E
T7S
.
.
.
SL0
SL0
SL0
LSU
LSU
TN
Tear Down Error
RSY
Tear Down
DEAC
Receive Reset
T7S
LSL
T7E
**) When state Line Active is entered the first time
at startup the 2B+D data must be clamped to ’0’,
until act= ’1’ has been received from the NT
LT_SM_2B1Q_cust.emf
Figure 3
State Diagram of V2.1
Delta Sheet
9
2000-12-01
PEF 24911
State Machine
DEAC
LTD
Figure 4
State Diagram of V1.3
Delta Sheet
10
2000-12-01
PEF 24911
RITL/WLL Functions
Table 4
Differences to LT-SM of DFE-Q V1.3
No. V1.3 State/
Signal
Change in V2.1
Comment
1. ’Test’ State
split into two states
- Reset State
defined reset and test states
- Test State
2.
state ’Alerting Error’
introduced for a clear separation
of the normal operation state from
the error condition state (which will
result in a deactivation)
3. state
C/I code output in state
’Transparent’ ’Transparent’ dependent on
received act bit
4. state ’S/T
Deactivated’
C/I code output in state ’S/T
Deactivated’ dependent on
sai bit status
5. C/I code LTD C/I code ’LTD’ is omitted
function corresponds to that of C/I
’RES’
6. C/I code INT
C/I code ’INT’ is not
supported
INT was listed in former
documents of V1.x due to an
editorial fault
11
RITL/WLL Functions
RITL/WLL functions are not supported by the DFE-Q version 2.1.
12
Retrieving Coefficients
MON-8 commands with bit r=1, that were defined for former versions, are no more
supported.
Delta Sheet
11
2000-12-01
PEF 24911
Boundary Scan Instruction Set
13
Boundary Scan Instruction Set
The Boundary-Scan instructions ’CLAMP’ and ’HIGHZ’ are introduced in version 2.1.
The instruction ’SSP’ and ’DT’ are omitted since these test functions can be triggered
either by the pins SSP and DT or - channel selective - by the C/I codes SSP and DT.
CLAMP allows the state of the signals included in the boundary scan driven from the
PEB 24911 to be determined from the boundary scan register while the bypass register
is selected as the serial path between TDI and TDO. These output signals driven from
the DFE-Q V2.1 will not change while CLAMP is selected.
HIGHZ sets all output pins included to the boundary scan path into a high impedance
state. In this state, an in-circuit test system may drive signals onto the connections
normally driven by the DFE-Q V2.1 outputs without incurring the risk of damage to the
DFE-Q V2.1.
Table 5
TAP Controller Instructions
Code
0000
0001
0010
0011
0100
0101
1111
Instruction
EXTEST
Function
External testing
INTEST
Internal testing
SAMPLE/PRELOAD
IDCODE
Snap-shot testing
Reading ID code
CLAMP
Reading outputs
HIGHZ
Z-State of all boundary scan output pins
Bypass operation
BYPASS
14
Version Update of the Boundary Scan IDCODE
Register
Version
Device Code
Manufacturer Code
0000 1000 001
Output
0001
0000 0000 0111 0010
1
-->
TDO
Delta Sheet
12
2000-12-01
PEF 24911
MON-8 AID Version Identification
15
MON-8 AID Version Identification
On receiving the MON-8 Command RID the DFE-Q responds with the MONITOR
message AID coded 8006H .
This code is unique for version 2.1 with respect to other DFE-Q versions
16
Recognition delay of C/I code changes
The DFE-Q V2.1 has implemented a new architecture for low power consumption.
Furthermore it is developed for complete compatibility in MONITOR and C/I messages.
The new architecture , however, leads to changes in response times compared to former
versions, that could affect the compatibility to software with rigid time-out settings.
The evaluation of changes of the incoming C/I-code takes longer than in former versions
of the PEB 24911:
• Recognition of changes to unconditional commands (I.e.: to RES, SSP, and DT) takes
up to 2,5 msec instead of 0.25 msec in former versions
• In the C/I channel in states ’Test’ and ’Reset’ recognition of changes can also take up
to 2,5 msec instead of 0.25 msec in former versions
• In states other than ’Reset’ or ’Test’ recognition of changes to all other conditional
commands takes up to 0,5 ms instead of 0.25 msec in former versions
The C/I codes shall be repeated at least the times above, before the C/I code may be
changed. Surveillance timers have to be set to values beyond the named times.
17
MON-8 messages in State ’Reset’
The issuing of MON-8 messages has been improved in state ’Reset’
If the state ’Reset’ is entered due to a hardware reset (pin RES=0) the device will issue
a MON-8 message AST afterwards if one of the pins STxy is high to communicate this
status to the system software.
The usage of MON-8 commands is not blocked during a Software Reset, i.e. the C/I-
command RES is applied. Even while the SW-reset is activated, the relay driver pins can
be programmed by the MON-8 message SETD, and the status pins can be read with
RST messages or will autonomously communicate changes of the status. The device will
also answer on a RID-command with a AID-message.
18
C/I-channel indication in Hardware Reset
As long as pin RES is low, the issued C/I-code is DI (1111b) instead of DEAC (0001b) for
all channels. After putting RES to high the C/I-codes change to DEAC.
Delta Sheet
13
2000-12-01
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