PI6CV850 [ETC]
TEN DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|TSSOP|48PIN|PLASTIC ; 10个分发输出时钟驱动器| CMOS | TSSOP封装| 48PIN |塑料\n
| 型号： | PI6CV850 |
| 厂家： | 
ETC |
| 描述： | TEN DISTRIBUTED-OUTPUT CLOCK DRIVER|CMOS|TSSOP|48PIN|PLASTIC
|
| 文件： | 总7页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6CV850
2.5-V Phase Lock Loop Clock Driver
with I2C Control Interface
Description
Features
PI6CV850isahigh-performance,low-skew,low-jitter zero-delaybuffer
that distributes a differential clock input pair (CLK, CLK) to ten
differentialpairofclockoutputs(Y[0:9],Y[0:9])andonedifferentialpair
feedbackclockoutput(FBOUT,FBOUT).Clockoutputsarecontrolled
Phase-Lock Loop Clock Driver for Double Data Rate
Synchronous DRAM Applications
SpreadSpectrumClockCompatible
Operating Frequency: 60 to 170 MHz
LowJitter(cycle-cycle):<|75ps|
2
byinputclocks(CLK,CLK),feedbackclocks(FBIN,FBIN),I CControl
2
Interface,andAnalogPowerinput(AV ).I CControlInterfacecan
DD
Distributes One Differential Clock Input to Ten
DifferentialOutputs
I 2 C Serial Interface Provides Output Enable and
Functional Control
Three-State Outputs when I2C low-level control
bit is written
3-state individual output clock pairs. When AV is strapped LOW,
PLL is turned off and bypassed for test purposes.
DD
2
The device provides a standard mode (100kbits/s) I C serial interface
for device control. Implementation is as a slave/receiver, and address
2
2
is specified in I C device address table. Both I C inputs (SDATA &
SCLK) provide integrated pullup resistors (typically 140 kohms) .
2
Two 8-bit I C registers provide individual enable control for each
Operatesfromdual2.5-Vand3.3VSupplies
output pair. At powerup, all outputs default to enabled . Each pair can
be placed in a 3-state mode with a low-level output when a low-level
controlbitiswrittentothecontrolregister.Registersmustbeaccessed
in sequence (random access of the registers not supported).
ExternalFeedbackPins(FBIN,FBIN)areusedto
Synchronize the Outputs to the Input Clocks
LowJitter<100ps
LowSkew<100ps
For reduced EMI, the PI6CV850 also tracks Spread Spectrum
Clocking.
Low Phase Offset: TBD
48-PinTSSOPPackage
Since the PI6CV850 is based on PLL circuitry, it requires a stabili-
zationtimetoachievephase-lockofthePLL.Thisstabilizationtime
is required following power up. Also required are changes to
BlockDiagram
2
various I C controls that effect the PLL.
3
Y0
Y0
SCLK
SDATA
AV
2
Test and
Logic
PinConfiguration
5
6
Y1
Y1
DD
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
GND
Y0
1
GND
Y5
10
9
Y2
Y2
2
Y0
3
Y5
20
19
V
4
VDDQ
Y6
DDQ
Y1
Y3
Y3
5
Y1
6
Y6
22
23
Y4
Y4
GND
GND
Y2
7
GND
GND
Y7
8
46
47
9
Y5
Y5
Y2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Y7
48-Pin
A
V
V
DDQ
SDATA
DDQ
SCLK
44
43
Y6
Y6
CLK
CLK
FBIN
39
40
FBIN
Y7
Y7
V
V
DDQ
DDI2C
AV
FBOUT
FBOUT
GND
Y8
DD
29
30
Y8
Y8
AGND
GND
Y3
13
CLK
14
CLK
PLL
36
35
Y3
Y8
29
28
27
26
25
FBIN
FBIN
27
26
V
V
DDQ
DDQ
Y9
Y9
Y4
Y9
Y4
Y9
32
33
GND
GND
FBOUT
FBOUT
PS8481B
01/15/02
1
PI6CV850
2.5-V Phase Lock Loop Clock Driver
withI2C ControlInterface
PinoutTable
Pin Name
Pin No.
I/O Type
Description
CLK
CLK
13
14
I
Reference Clock input
Clock outputs.
Yx
3,5,10,20,22,27,
29,39,44,46
O
Yx
2,6,9,19,23,26,
30,40,43,47
Complement Clock outputs.
Feedback output.
FBOUT
FBOUT
33
32
FBIN
FBIN
35
36
Feedback input.
I
VDDQ
4,11,21,
Power
Power Supply for I/O. 2.5Volts
28,34,38,45
AVDD
16
Analog /core power supply. AVCC can be used to bypass the PLL for testing
purposes. WhenAVCC is strapped to ground, PLLis bypassed and CLK is buffered
directly to the device outputs. 2.5Volts
AGND
GND
17
Ground
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground
1,7,8,18,24,25,
31,41,42,48
SDATA
SCLK
37
12
15
Serial Data in for Serial Configuration port
Clock Input for Serial Configuration port
2.5V or 3.3V Supply for I2C Interface
I2C
2
VDDI C
Power
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
Parameter
I/O supply voltage range and analog/core supply voltage range
Input voltage range
Min.
0.5
0.5
0.5
65
Max.
Units
VDDQ, AVCC
3.6
VI
V
VDDQ+0.5
VO
Tstg
Output voltage range
o
Storage temperature
150
C
Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
PS8481B
01/15/02
2
PI6CV850
2.5-V Phase Lock Loop Clock Driver
withI2C ControlInterface
DC Specifications
Recommended Operating Conditions
Symbol
AVCC
VDDQ
VIL
Parameter
Analog/core supply voltage
Min.
Nom.
2.5
Max.
2.7
Units
2.3
V
Output supply voltage
2.3
2.5
2.7
Low-level input voltage for I2C
High-level input voltage for I2C
High-level output voltage, IOL = 12mA
Low-level output voltage, IOL = 12mA
Input differential-pair crossing voltage
Vss 0.3
0.8
VIH
2.0
VDDQ +0.3
VDDQ
VOH
VOL
1.7
0
0.6
VIX
(VDDQ/2) 0.2
(VDDQ/2) +0.2
Output differential-pair crossing voltage
at the DRAM clock input
VOX
(VDDQ/2) 0.2
(VDDQ/2) +0.2
VDDQ +0.3
0.71
VIN
VID
Input voltage level
0.3
0
Input differential voltage between CK and CK
2.5V or 3.3V for I2C supply
Output differential voltage
VDDI2C
VOD
TA
2.3
0.7
0
3.6
VDDQ +0.6
70
Operating free air temperature
°C
Electrical Characteristics
Parameter
Test Conditions
II = 18mA
AVCC, VDDQ
Min.
Typ.
Max.
1.2
±10
±5
Units
VIK
II
All inputs
2.3V
V
CK, FBIN
VI = VDDQ or GND
VI = VDDQ or GND
A
mA
pF
SDATA, SCLK
Dynamic supply current
CK and CK
2.7V
IDDQ
300
CI
VI = VDD or GND
2.5V
2.0
3.0
FBIN and FBIN
PS8481B
01/15/02
3
PI6CV850
2.5-V Phase Lock Loop Clock Driver
withI2C ControlInterface
Timing Requirements (Over recommended operating free-air temperature).
A
VCC
, V
= 2.5V ±0.2V
DDQ
Min.
60
Max.
170
170
60
Symbol
Description
Units
(1,2)
Operating clock frequency
f
CK
MHz
(3)
Application clock frequency
Input clock duty cycle
95
t
DC
40
%
s
t
PLL stabilization time after powerup
100
STAB
Notes:
1. The PLL is able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not
required to meet the other timing parameters. (Used for low-speed debug).
3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters.
ACSpecifications
Switching characteristics over recommended Operating free-air temperature range (unless otherwise noted)
AVCC, VDDQ = 2.5V ±0.2V
Parameter
tjit(cc)
Description
Cycle-to-cycle jitter
Diagram
see Figure 3
see Figure 4
see Figure 5
see Figure 6
see Figure 7
see Figure 8
see Figure 8
Min.
Nom.
Max
Units
75
75
t( )
Static phase error(1)
Output clock skew
Period jitter
0
tsk(o)
tjit(per)
tjit(hper)
tsl(i)
100
75
ps
75
100
1.0
Half-period jitter
100
2.0
2.0
Input clock slew rate(2)
Output clock slew rate(2)
V/ns
tsl(o)
1.0
The PLL on the PI6CV850 meets all the above parameters while supporting SSC synthesizers(3) with the following parameters.
SSC modulation frequency
SSC clock input frequency deviation
PLL loop bandwidth
30.00
0.00
50.00
0.50
kHz
%
2
MHz
degrees
Phase angle
0.031
Notes:
1. Static Phase Error does not include Jitter.
2. The slew rate is determined from the IBIS model and not from the test load.
3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification.
PS8481B
01/15/02
4
PI6CV850
2.5-V Phase Lock Loop Clock Driver
withI2C ControlInterface
FunctionTables
Select Functions
INPUTS
OUTPUTS
PLL
AVDD
GND
CLK
L
CLK
H
Y[0:9]
Y[0:9]
FBOUT
FBOUT
L
H
L
H
L
H
L
L
H
L
H
L
Bypassed/Off
Bypassed/Off
On
GND
H
L
2.5V (nom)
2.5V (nom)
L
H
H
L
H
L
H
H
On
Each output pair can be 3-state via the I2C interface, except FBOUT and FBOUT
I2C Device Address
The following section describes the I2C interface programming.
A7
1
A6
1
A5
0
A4
1
A3
0
A2
0
A1
1
A0
0
WritingtotheI2CInterface
1. Send the address D2
(H)
2. Send the dummy bytes and command code.
3. Send the number of data bytes.
Clock Generator
Addr (7 bits)
+8-Bits dummy
command code
+8-Bits
dummy
A(6:0)&
R/W#
ACK
ACK
ACK
Data Byte 1
ACK
Data Byte 4
ACK
D2(H)
I2CConfigurationCommandBitmap
Byte0:Enable/DisableRegister
(H=Enable,L=Disable)
Byte1:Enable/DisableRegister
(H=Enable,L=Disable)
Bit
7
Pins
3,2
PWD
Description
Y0,Y0
Bit
7
Pins
29,30
27,26
PWD
Description
Y8,Y8
Y9,Y9
6
5,6
Y1,Y1
6
5
10,9
20,19
Y2,Y2
5
4
Y3,Y3
4
H
H
3
22,23
Y4,Y4
3
Reserved
2
1
0
46,47
44,43
39,40
Y5,Y5
Y6,Y6
Y7,Y7
2
1
0
Note:Disable/OutputheldHiZ.
Note:Disable/OutputheldHiZ.
PS8481B
01/15/02
5
PI6CV850
2.5-V Phase Lock Loop Clock Driver
withI2C ControlInterface
VDD
Ω
Ω
Z=60
Z=60
C=14pF
R=120
Ω
GND
C=14pF
GND
PI6CV850
GND
Figure 1. Output Load
V
/2
DDQ
Z=60
Ω
Ω
R=10
R=10
Ω
Ω
Z=50
Z=50
Ω
C=14pF
/2
R=50
GND
Ω
Ω
–V
–V
DDQ
Z=60
Ω
C=14pF
/2
R=50
GND
DDQ
PI6CV850
SCOPE
–V
/2
DDQ
Figure 2. Output Load Test Circuit
PS8481B
01/15/02
6
PI6CV850
2.5-V Phase Lock Loop Clock Driver
withI2C ControlInterface
48-PinTSSOPMechanicalDrawing(A)
48
.236
.244
6.0
6.2
1
.488 12.4
.496 12.6
.047
1.20 Max
SEATING PLANE
0.09
0.20
.004
.008
0.45 .018
0.75 .030
.002
.006
0.05
0.15
.007
.010
.0197
BSC
.319
BSC
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.50
0.17
0.27
8.1
Ordering Information
P/N
Description
Temp
PI6CV850
48-Pin TSSOP package
Commercial
Pericom Semiconductor Corporation
2380BeringDrive SanJose, CA951311-800-435-2336 Fax(408)435-1100 http://www.pericom.com
PS8481B
01/15/02
7
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