UT1553BRTIGPX [ETC]

RTI Remote Terminal Interface; RTI的远程终端接口


型号：	UT1553BRTIGPX
厂家：	ETC
描述：	RTI Remote Terminal Interface RTI的远程终端接口
文件：	总52页 (文件大小：1271K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UT1553B RTI Remote Terminal Interface

❐ Operational status available via dedicated lines or

FEATURES

internal status register

❐ Complete MIL-STD-1553B Remote Terminal

❐ ASD/ENASC (formerly SEAFAC) tested and

interface compliance

approved

❐ Dual-redundant data bus operation supported

❐ Available in ceramic 84-lead leadless chip carrier and

❐ Internal illegalization of selected mode code

84-pin pingrid array

commands

❐ Full military operating temperature range, -55°C to

+125°C, screened to the speciﬁc test methods listed in

Table I of MIL-STD-883, Method 5004, Class B

❐ External illegal command deﬁnition capability

❐ Automatic DMA control and address generation

❐ JAN-qualiﬁed devices available

MODE CODE/

SUB ADDRESS

HOST

SYSTEM

ADDRESS

INPUTS

ILLEGAL

COMMAND

DECODER

CHANNEL

MEMORY

ADDRESS

CONTROL

OUTPUT EN

OUT

COMMAND

RECOGNITION

LOGIC

MEMORY

ADDRESS

OUTPUTS

DECODER

CHANNEL

CONTROL

INPUTS

CONTROL

AND

ERROR LOGIC

CONTROL

OUTPUTS

TIMEOUT

TIMERON

12MHz

MUX

DATA

TRANSFER

LOGIC

CLOCK AND

RESET LOGIC

ENCODER

OUT

RESET

2MHz

DATA I/O BUS

Figure 1. UT1553B RTI Functional Block Diagram

RTI-1

Table of Contents

1.0 ARCHITECTURE AND OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1.1 Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1.2 Transparent Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.2 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

1.3 Mode Codes and Subaddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.4 MIL-STD-1553B Subaddress and Mode Codes . . . . . . . . . . . . . . . . . . . . . . . .9

1.5 Remote Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.6 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.7 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.8 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.9 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.0

3.0

4.0

5.0

6.0

7.0

MEMORY MAP EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PIN IDENTIFICATION AND DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MAXIMUM AND RECOMMENDED OPERATING CONDITIONS. . . . . . . . . . . . . . . . . 21

DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

PACKAGE OUTLINE DRAWINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

RTI-2

Output Multiplexing and Self-Test Logic

This logic directs the output of the encoder to one of four

places:- Channel A outputs

- Channel B outputs

- Channel A decoders during self-test

- Channel B decoders during self-test

1.0 ARCHITECTURE AND OPERATION

The UT1553B RTI is an interface device linking a MIL-

STD-1553serialdatabusandahostmicroprocessorsystem.

The RTI’s MIL-STD-1553B interface includes encoding/

decoding logic, error detection, command recognition,

memory address control, clock, and reset circuits.

Clock and Reset Logic

Decoders

The UT1553B RTI requires a 12MHz input clock to operate

properly. The RTI provides a 2MHz output for the system

designer to use. The device provides a hardware reset pin

as well as software-generated reset.

The UT1553B RTI contains two separate free-running

decoders to insure that all redundancy requirements of MIL-

STD-1553B are met. Each decoder receives, decodes, and

veriﬁes biphase Manchester II data. Proper frequency and

edge skew are also veriﬁed.

Timer Logic

The UT1553B RTI has a built-in 730ms timer that is

activated when the encoder is about to transmit. The timer

is reset upon receipt of a valid command, master reset, or a

time-out condition.

Command Recognition Logic

The command recognition logic monitors the output of both

decoders at all times. Recognition of a valid command

causes a reset of present interface activity followed by

execution of the command. This procedure meets the

requirement for superseding valid commands.

1.1 HOST INTERFACE

Conﬁgure the RTI into the host system for either a direct

memory or transparent memory access. The following

sections discuss the system conﬁguration for each method

of memory management.

Encoder

Theencoderreceivesserialdatafromthedatatransferlogic,

converts it to Manchester II form with proper

synchronization and parity, and passes it to the output and

self-test logic.

1.1.1 Direct Memory Access

In the direct memory access conﬁguration the RTI and host

arbitrate for the shared 2K x 16 memory space. To request

access to memory the RTI asserts direct memory request

output (DMARQ); the system bus arbiter grants the RTI

access to memory by asserting the direct memory access

grantsignal(MEMCK).Thesystemarbitershouldnotassert

the MEMCK signal before the RTI has requested access to

memory (i.e., DMARQ asserted).

Data Transfer Logic

The data transfer logic provides double-buffered 16-bit

parallel-to-serial and serial-to-parallel conversion during

reception and transmission of data.

Memory Address Control

The memory address control logic controls the output of the

three-state address lines during memory access. In DMA

system implementations, the memory address control

provides RTI-generated addresses. In a pseudo-dual-port

memory conﬁguration, the memory address control logic

provides either RTI-generated or host system addressing.

Once granted access to memory, the RTI address out

(ADDR OUT(10:0)), RAM chip select (RCS), RAM read/

write(RRD/RWR), andDatabus(DATAI/O(15:0))provide

the interface signals to control the memory access. Figure

2 shows an example of a direct memory access system

conﬁguration; for clarity the interface buffers and logic are

excluded. The host microprocessor also gains access to

memory by arbitration.

Control and Error Logic

The control and error logic performs the following four

major functions:

Take care to insure that bus contention does not occur

between the host and RTIAddress buses or memory control

signals. To place the RTI Address Out bus in a high

impedance state negate the ADOEN input pin. Also note

thatoutputsRCSandRRD/RWRarenotthree-stateoutputs.

When the RTI is not writing to memory, bidirectional Data

bus DATA I/O(15:0) is an input (i.e., not actively driving

the bus).

Interface control for proper processing of MIL-

STD-1553B commands

Error checking of both MIL-STD-1553B data and

RTI operation

Memory control (DMA or pseudo-dual-port) for

proper data transfer

Operational status and control signal generation

RTI-3

Shared

Memory

CONTROL

Host

Computer

RTI

UT1553B

DATA(15:0)

ADDR(10:0)

DMA

CONTROLLER

Figure 2. Direct Memory Access Conﬁguration

The host microprocessor gains access to the RTI internal

registers by controlling input pins CS, CTRL, ADDR IN

(10:0), and RD/WR. During message processing the host

microprocessorshouldlimitaccesstoRTIinternalregisters.

The host microprocessor gains access to the RTI internal

registers by controlling input pins CS, CTRL, ADDR IN

(10:0), and RD/WR. During message processing the host

microprocessorshouldlimitaccesstoRTIinternalregisters.

The host should not assert CS while the RTI is performing

a memory access.

1.1.2 Transparent Memory Access

Conﬁgured in the transparent memory mode the host

microprocessor accesses shared memory through the RTI.

Arbitration for access to the bus is performed as discussed

in section 1.1.1 of this document.

1.2 Internal Register Description

The RTI uses three internal registers to allow the host to

control the RTI operation and monitor its status. The host

uses the following inputs Control (CTRL), Chip Select

(CS), Read/Write (RD/WR), and ADDR IN (0) to read the

16-bitSystemRegisterorwritetothe8-bitControlRegister.

The Control Register toggles bits in the MIL-STD-1553B

status word, enables biphase inputs, selects terminal active

ﬂag, and puts the part in self-test. The System Register

supplies operational status of the UT1553B RTI to the host.

The Last Command Register saves the command word for

a Transmit Last Command mode code, along with

operational status from the System Register.

When granted access to memory, the RTI asserts memory

control signals ADDR OUT(10:0), RCS, and RRD/RWR.

For host-controlled memory accesses the RAM memory

address from the host is propagated from theAddress In bus

ADDRIN(10:0)totheAddressOutbusADDROUT(10:0).

MemorycontrolsignalsRD/WRandCSarealsopropagated

through the RTI as RRD/RWR and RCS. Input CTRL is

negated during all transparent memory accesses to prevent

the RTI from inadvertently performing an internal register

access or software reset. While CS is asserted, the RTI’s

bidirectional Data bus DATA I/O (15:0) is an input (i.e., not

actively driving bus).

DATA(15:0)

CONTROL

Host

RTI

UT1553B

Shared

Memory

Computer

DATA I/O (15:0)

ADDR OUT (10:0)

ADDR IN (10:0)

DMA

CONTROLLER

Figure 3. Transparent Memory Access Conﬁguration

Control Register (Write Only)

RTI-4

The 8-bit write-only Control Register manages the operation of the RTI. Write to the Control Register by applying a logic zero

to CS, CTRL, RD/WR, and ADDR IN (0); if ADDR IN (0) is a logic one a master reset occurs. Data is loaded into the Control

Register via I/O pins DATA(7:0). Control Register writes must occur 50ns before the rising edge of COMSTR to latch data in

the outgoing status word.

Bit

Initial

Number

Condition

Description

[0]

Channel A Enable. A logic one enables Channel A biphase inputs.

Channel B Enable. A logic one enables Channel B biphase inputs.

Terminal Flag. A logic one sets the Terminal Flag bit of the Status Register.

System Busy. A logic one sets the Busy bit of the System Register and inhibits

RTI access to memory. No data words are retrieved or stored; command word is

stored.

[0]

Subsystem Busy. A logic one sets the Subsystem Flag bit of the Status Register.

Self-Test Channel Select. This bit selects which channel the internal self-test

checks; a logic one selects Channel A and a logic zero selects Channel B.

[0]

Self-Test Enable. A logic one sets the RTI in the internal self-test mode and inhib-

its normal operation. Internal testing is not visible on biphase output

channels.

[0]

Service Request. A logic one sets the Service Request bit of the Status Register.

CONTROL REGISTER (WRITE ONLY)

[0]

CH B

BUSY

[0]

CH A

SUBS

[0]

SELF

TEST

SELF

SRV

[0]

LSB

MSB

[ ] deﬁnes reset state

Figure 4. Control Register

System Register (Read Only)

The 16-bit read-only System Register provides the RTI system status. Read the System Register by applying a logic zero to

CS, CTRL, ADDR IN (0), and a logic one to RD/WR. The 16-bit contents of the System Register are read from data I/O pins

DATA(15:0).

Bit

Initial

Number

Condition

Description

[0]

MCSA(0). The LSB of the mode code or subaddress as indicated by the

logic state of bit 5.

[0]

MCSA(1). Mode code or subaddress as indicated by the state of bit 5.

MCSA(2). Mode code or subaddress as indicated by the state of bit 5.

MCSA(3). Mode code or subaddress as indicated by the state of bit 5.

MCSA(4). Mode code or subaddress as indicated by the state of bit 5.

MC/SA. A logic one indicates that bits 4 through 0 are the subaddress of

the last command word, and that the last command word was a normal

transmit orreceive command. A logic zero indicates that bits 4 through 0

are a mode code, and that the last command was a mode code.

[1]

Channel A/B. A logic one indicates that the most recent command arrived

onChannel A; a logic zero indicates that it arrived on Channel B.

RTI-5

[0]

[1]

Channel B Enabled. A logic one indicates that Channel B is available for

both reception and transmission.

Channel A Enabled. A logic one indicates that Channel A is available for

both reception and transmission.

Terminal Flag Enabled. A logic one indicates that the Bus Controller has

not issued an Inhibit Terminal Flag mode code. A logic zero indicates that

the Bus Controller, via the above mode code, is overriding the host sys-

tem’s ability to set the Terminal Flag bit of the status word.

[0]

Busy. A logic one indicates the Busy bit is set. This bit is reset when the

SystemBusy bit in the Control Register is reset.

Self-Test. A logic one indicates that the RTI is in the self-test mode. This

bit isreset when the self-test is terminated.

TA Parity Error. A logic one indicates the wrong Terminal Address parity;

it causes the biphase inputs to be disabled and a message error condition.

This bit is reset by reloading the terminal address latch with correct parity.

[0]

Message Error. A logic one indicates that a message error has occurred

since the last System Register read. This bit is not reset until the System

Valid Message. A logic one indicates that a valid message has been

received since the last System Register read. This bit is not reset until the

System Register has been examined.

Terminal Active. A logic one indicates the device is executing a transmit or

receive operation. The state of this bit is the logical NAND of the external

XMIT and RCV pins.

SYSTEM REGISTER (READ ONLY)

TERM

ACTV

VAL MESS TAPA SELF- BUSY

TFEN CH A

CH B

CHNL

A/B

MC/

MCSA MCSA MCSA MCSA MCSA

MESS

ERR

TEST

[0]

[1]

[0]

[1]

[0]

LSB

[0]

MSB

[ ] deﬁnes reset state

Figure 5. System Registers

RTI-6

Last Command Register (Read Only)

The 16-bit read-only Last Command Register provides the host with last command and operational status information. The

RTI transmits the lower 11 bits of this register along with terminal address upon receipt of a Transmit Last Command mode

code. Read the Last Command Register by applying a logic zero to CS, CTRL, and a logic one to RD/WR and ADDR IN (0).

The 16-bit contents of the Last Command Register are read from data I/O pins DATA(15:0).

Bit

Initial

Number

Condition

Description

0 through 10

[all 1s]

[0]

Least signiﬁcant 11 bits of the last command word.

Busy Bit. System Register bit 10.

[0]

Self-test. System Register bit 11.

[1]

Terminal Flag Enabled. System Register bit 9.

Channel A/B. System Register bit 6.

Illegal Command. The RTI illegalized the last command.

[1]

1.3 Mode Codes and Subaddresses

Mode codes which involve data transfer are processed like

receive and transmit commands. The RTI will not generate

DMA request for Transmit Status Word and Transmit Last

Command mode codes since the information is stored

internal to the RTI.

The UT1553B RTI provides subaddress and mode code

decoding meetingMIL-STD-1553B. Inaddition, the device

has automatic internal illegal command decoding for

reserved MIL-STD-1553B mode codes. Upon command

word validation and decode, status pins MCSA(4:0) and

MC/SA become valid. Status pin MC/SA will indicate

whether the data pins MCSA(4:0) are mode code or

subaddress information. Status Register bits 5 through 0

contain the same information as pins MCSA(4:0) and MC/

SA.

The following mode codes require assistance from the host:

- Synchronize

Initiate Self-Test

- Reset Remote Terminal

For example, the RTI will accept and respond to a Reset

Remote Terminal mode code; however it will not perform

a reset operation. The host must interpret the mode code and

take appropriate action.

The system designer can use signals MCSA(4:0), MC/SA,

BRDCST, XMIT, and RCV to illegalize mode codes,

subaddresses, and other message formats via the Illegal

Command (ILL COMM) input (see ﬁgure 23 on

page 36).

The RTI does not deﬁne or interpret the following data

words associated with mode code commands:

The RTI will internally decode the following mode codes

as illegal:

- Transmit Vector Word

- Dynamic Bus Control

Synchronize With Data Word

Transmit Bit Word

- Selected Transmitter Shutdown

- Override Selected Transmitter Shutdown

- All Reserved Mode Codes

The RTI will accept and respond to mode code with data;

the host must interpret or deﬁne the data word. The RTI will

store or retrieve the data required for mode code command

from block #1 of the receive or transmit page

If the RTI receives one of the above mode codes, the RTI

responds by transmitting a status word with the Message

Error bit set to logic one.

RTI-7

RTI MODE CODE HANDLING PROCEDURE

T/R

Mode Code

Function

Operation

10100

Selected Transmitter Shutdown

1. Command word stored

2. MES ERR pin asserted

3. Message error latch set in System Register

4. Status word transmitted

10101

Override Selected Transmitter

Shutdown

1. Command word stored

2. MES ERR pin asserted

3. Message error latch set in System Register

4. Status word transmitted

10001

00000

Synchronize (w/data)

1. Command word stored

2. Data word stored

3. Status word transmitted

Dynamic Bus Control

1. Command word stored

2. MES ERR pin asserted

3. Message error latch set in System Register

4. Status word transmitted

00001

00010

00011

00100

Synchronize

1. Command word stored

2. Status word transmitted

Transmit Status Word

1. Command word stored

2. Status word transmitted

Initiate Self-Test

1. Command word stored

2. Status word transmitted

Transmitter Shutdown

1. Command word stored

2. Alternate bus shutdown

3. Status word transmitted

00101

00110

00111

Override Transmitter Shutdown

Inhibit Terminal Flag Bit

1. Command word stored

2. Alternate bus enabled

3. Status word transmitted

1. Command word stored

2. Terminal Flag bit set to zero and disabled

3. Status word transmitted

Override Inhibit Terminal Flag Bit 1. Command word stored Bit

2. Terminal Flag bit enabled, but not set to logic one

3. Status word transmitted

01000

10010

10000

Reset Remote Terminal

1. Command word stored

2. Status word transmitted

Transmit Last Command Word

Transmit Vector Word

1. Status word transmitted

2. Last command word transmitted

1. Command word stored

2. Status word transmitted

3. Data word transmitted

10011

Transmit BIT Word

1. Command word stored

2. Status word transmitted

3. Data word transmitted

Notes:

1. Further host interaction required for mode code operation.

2. Reserved mode code; A) MES ERR pin asserted, B) Message Error bit set, C) status word transmitted (ME bit set to logic one).

3.Status word not affected.

RTI-8

1.4 MIL-STD-1553B Subaddress and Mode Code Deﬁnitions

Table 1. Subaddress and Mode Code Deﬁnitions Per MIL-STD-1553B

Message Format

Transmit

Subaddress Field

Binary (Decimal)

Receive

Description

00000 (00)

00001 (01)

00010 (02)

00011 (03)

00100 (04)

00101 (05)

00110 (06)

00111 (07)

01000 (08)

01001 (09)

01010 (10)

01011 (11)

01100 (12)

01101 (13)

01110 (14)

01111 (15)

10000 (16)

10001 (17)

10010 (18)

10011 (19)

10100 (20)

10101 (21)

10110 (22)

10111 (23)

11000 (24)

11001 (25)

11010 (26)

11011 (27)

11100 (28)

11101 (29)

11110 (30)

11111 (31)

Mode Code Indicator

User Deﬁned

Mode Code Indicator

Note:

1. Refer to mode code assignments per MIL-STD-1553B

1.5 Remote Terminal Address

Parity Checker

Assign the RTI remote terminal address by either a software

or hardware exercise. The host assigns the RTI remote

terminal address by performing a Control Register write;

the Terminal Address bus (TA(4:0)) is strobed into the RTI

Remote TerminalAddress Register upon completion of the

Control Register write. To assign the RTI remote terminal

address via hardware, use the TALEN/PARITY input pin

operating in the terminal latch address enable mode. The

Terminal Address bus is latched into the RTI while the

TALEN is asserted (i.e., logic low). Valid remote terminal

addresses (RTA) include decimal 0 through 31 if Broadcast

is disabled, 0 through 30 if Broadcast is enabled

An address parity check is performed to insure the remote

terminal address applied to TA(4:0) was properly latched

into the Remote Terminal Address Register. To perform a

parity check, enable the RTI parity circuit via EXT TEST

and EXT TST CH SEL A/B input pins. The parity bit is

entered through theTALEN/PARITY input pin operating in

the parity mode. Input pins EXT TEST and EXT TST CH

SELA/B control dual-function input pin TALEN/PARITY;

see table 2 for description of operation.

If a parity error exists, the Parity Error bit of the System

disabled(settologiczero), theMessageErrorbitsettologic

one, and the message error pin is asserted.

RTI-9

Table 2. Parity Checking

STATE #

EXT TEST

EXT TST CH SEL A/B

Function of TALEN/PARITY

Terminal Address Latch Enable. Active low

signal used to latch TA(4:0) into RTI. Internal

parity checker disabled.

Parity. Internal remote terminal address parity

checker enabled. TALEN/PARITY pin func-

tions as parity bit for TA(4:0) bus. Proper oper-

ation requires odd parity.

Terminal Address Latch Enable. Do not assert

EXT TST during reset, otherwise self-test is

invoked.

Terminal Address Latch Enable. Do not assert

EXT TST during reset, otherwise self-test is

invoked.

The following are examples of sequences used to enter

remote terminal addresses into the RTI.

1.6 Internal Self-Test

Setting bit 6 of the Control Register to a logic one enables

the internal self-test. Disable ChannelsA and B at this time

to prevent bus activity during self-test by setting bits 0 and

1 of the Control Register to a logic zero. Normal operation

is inhibited when internal self-test is enabled. The RTI’s

self-test capability is based on the fact that the MIL-STD-

1553B status word sync pulse is identical to the command

word sync pulse. Thus, if the status word from the encoder

is fed back to the decoder, the RTI will recognize the

incoming status word as a command word and thus cause

the RTI to transmit another status word. After the host

invokes self-test, the RTI self-test logic forces a status word

transmission even though the RTI has not received a

command word. The status word is sent to decoder A or B

depending on the channel the host selected for self-test. The

host controls the self-test by periodically changing the bit

patterns in the status word being transmitted. Writing to the

Control Register bits 2, 3, 4, and 8 changes the status word.

Monitortheself-testbysamplingeithertheSystemRegister

or the external status pins (i.e. Command Strobe

Example 1.

Hardware-Controlled Remote Terminal

Address (parity check disabled):

STATE 0, 2, or 3 (i.e., 00, 10, or 11)

TALEN - asserted (i.e., logic low)

TA(4:0) - valid RTA

Example 2.

Software-Controlled Remote Terminal

Address (parity check disabled):

EXT TEST and EXT TST CH SEL A/B

in STATE 0, 2, or 3 (i.e., 00, 10, or 11)

CTRL - logic zero

CS - logic zero

RD/WR - logic zero

ADDR IN (0) - logic zero

TALEN - logic one

TA(4:0) - valid RTA

Example 3.

Software Controlled Remote Terminal

Address (parity check enabled):

EXT TEST and EXT TST CH SEL A/B

in STATE 1 (i.e., 01)

CTRL - logic zero

(COMSTR),Transmit(XMIT),Receive(RCV)).Foramore

detailed explanation of internal self-test, consult the UTMC

publication RTI Internal Self-Test Routine.

CS - logic zero

RD/WR - logic zero

ADDR IN (0) - logic zero

PARITY - input must provide odd

parity

1.7 Power-up Master Reset

Reset the RTI by invoking either a hardware or software

master reset after power-up to place the device in a known

state. The master reset clears the decoder and encoder

registers, the command recognition logic, the control and

error logic (which includes the Status, Control and System

Registers), the data transfer logic, and the memory address

control logic.After reset, conﬁgure the device for operation

via a Control Register write.

for the TA(4:0) bus

TA(4:0) - valid RTA

For examples 1 and 2, enabling the parity check circuit

(STATE1)aftertheremoteterminaladdressisstoredresults

inaparitycheckofthedataloadedintotheRemoteTerminal

Address Register.

RTI-10

Perform a hardware reset by asserting the MRST input pin

foraminimumof500ns. DuringresetnegatetheEXTTEST

pin (i.e., logic low); assertion of the EXT TEST pin forces

the RTI to enter the external self-test mode of operation.

word, sets the Message Error output, and sets the message

error latch in the System Register.

Use the following RTI outputs to externally decode an

illegal command, Mode Code or Subaddress indicator (MC/

SA), ModeCodeorSubaddressbusMCSA(4:0), Command

Strobe (COMSTR), Broadcast (BRDCST), etc. (See ﬁgure

6 pages 11-12).

Software reset the RTI by simultaneously applying a logic

zero to input pins CS, RD/WR, and CTRL while the least

signiﬁcant bit of the address input bus is a logic one (ADDR

IN (0)=0).

To illegalize a transmit command the ILL COMM pin is

asserted 3.3ms after STATUS goes to a logic one.Assertion

of the ILL COMM pin within 3.3ms allows the RTI to

respond with the Message Error bit of the outgoing status

word at a logic one.

1.8 Encoder and Decoder

The RTI interfaces directly to a bus transmitter/receiver via

the RTI Manchester II encoder/decoder. The UT1553B RTI

receives the command word from the MIL-STD-1553B bus

and processes it either by the primary or secondary decoder.

Each decode checks for the proper sync pulse and

Manchester waveform, edge skew, correct number of bits,

and parity. If the command is a receive command, the RTI

processes each incoming data word for correct word count

and contiguous data. If an invalid message error is detected,

the message error pin is asserted, the RTI ceases processing

the remainder (if any) of the message, and it then suppresses

status word transmission. Upon command validation

recognition, the external status outputs are enabled.

Reception of illegal commands does not suppress status

word transmission.

For an illegal receive command, the ILL COMM pin is

asserted within 18.2ms after the COMSTR transitions to a

logic zero in order to suppress data words from being stored

(suppressDMARQassertions).Inaddition,theILLCOMM

pin must be at a logic one throughout the reception of the

message until STATUS is asserted.

If the illegal command is mode code 2, 4, 5, 6, 7, or 18,

assert the ILL COMM pin within 664ns after Command

Strobe (COMSTR) transitions to logic zero. Asserting the

ILL COMM pin within the 664 nanoseconds inhibits the

mode code function.

The above timing conditions also apply when the host

externally decodes an illegal broadcast command. The host

must remove the illegal command condition so that the next

command is not falsely decoded as illegal. These

requirements are easily met if the COMSTR output is used

to qualify the ILL COMM input to the RTI.

A timer precludes transmission greater than 730ms by the

assertion of fail-safe timer (TIMERON). This timer is reset

upon receipt of another valid command.

1.9 Illegal Command Decoding

The host has the option of asserting the ILL COMM pin to

illegalize a received command word. On receipt of an illegal

command, the RTI sets the message error bit in the status

BIPHASE IN

COMSTR

RCV

COMMAND WORD

DATA WORD

18.2µs

ILL COMM

DMA Activity Suppressed

STATUS

STATUS WORD

BIPHASE OUT

Note:

1. Illegalcommandcondition;statuswordMessageErrorbitsettologicone,RTIMESERRpinsettoalogicone, RTIStatusRegisterMessage

Error bit set to logic one.

Figure 6a. Illegal Receive Command Decoding

RTI-11

BIPHASE IN

COMSTR

COMMAND WORD

XMIT

1.0µs (min)

ILL COMM

3.3µs

DMA Activity Suppressed

STATUS

BIPHASE OUT

STATUS WORD

Note:

1. Illegal command condition; status word Message Error bit set to logic one, RTI MES ERR pin set to a logic one, RTI Status Register

Message Error bit set to logic one.

Figure 6b. Illegal Transmit Command Decoding

COMMAND WORD

BIPHASE IN

COMSTR

MC/SA

664ns

ILL COMM

Note:

1. To illegalize mode codes 2, 4, 5, 6, 7, or 18 assert ILL COMM within 664ns of COMSTR’s transition to logic zero. Asserting

the ILL COMM within 664ns inhibits the mode code function.

Figure 6c. Mode Code Command Decoding

The T/R bit of the command word becomes the most

signiﬁcant bit of the data pointer; theT/R bit servestodivide

2.0 MEMORY MAP EXAMPLE

The RTI is capable of addressing 2048 x 16 of external

memory for message storage. The 2K memory space is

divided into two 1K pages and subdivided into 32 blocks of

32 x 16:

the RAM into transmit and receive pages of 1K each. The

5-bit subaddress/mode ﬁeld is used to select 1 of 32 possible

message storage blocks within the transmit or receive

message page. The 5-bit word count/mode code ﬁeld acts

as a data pointer to select one of 32 locations within the

message storage block. Multiple word messages are stored

from top to bottom within the message storage block.

Page 1 (Receive): 32 blocks for receive messages

(32 x 16)

Page 2 (Transmit): 32 blocks for transmit messages

(32 x 16)

For mode commands, the address data pointer always

contains 00000 in the MC/SA ﬁeld, regardless of whether

00000 or 11111 was received. Forcing the mode code ﬁeld

to 00000 reserves the ﬁrst message storage block on both

pages (receive and transmit) for mode code messages that

require data. The 5-bit mode code speciﬁes which of the 32

locations within the message storage block to access.

Address Decode

The RTI derives addresses (i.e., data pointers) for external

memory directly from the 11 least signiﬁcant bits of the

command word. The address data pointer corresponds to

ADDR OUT (10:0) during RTI memory accesses.

T/R = ADDR OUT (10)

SUBADDRESS/MODE = ADDR OUT (9:5) WORD

COUNT/MODE CODE = ADDR OUT (4:0)

RTI-12

For “wrap-around” applications (transmission of data

previously received), force the RTI to store and receive

messages on one memory page. To accomplish one-page

operation do not use the T/R output pin. Eliminating the T/

R limits the RTI access to only one page and the RTI will

not differentiate between receive and transmit pages.

Table 3. RTI Memory Map

1: Receive Memory Map

Block # Operation

2: Transmit Memory map

Address Field (hex) Block #

Operation

Address Field (hex)

400 to 41F

Mode Code

000 to 01F

020 to 03F

Mode Code

Subaddress 1

Subaddress 2

Subaddress 3

Subaddress 4

Subaddress 5

Subaddress 6

Subaddress 7

Subaddress 8

Subaddress 9

Subaddress 10

Subaddress 11

Subaddress 12

Subaddress 13

Subaddress 14

Subaddress 15

Subaddress 16

Subaddress 17

Subaddress 18

Subaddress 19

Subaddress 20

Subaddress 21

Subaddress 22

Subaddress 23

Subaddress 24

Subaddress 25

Subaddress 26

Subaddress 27

Subaddress 28

Subaddress 29

Subaddress 30

Unused

Subaddress 1

Subaddress 2

Subaddress 3

Subaddress 4

Subaddress 5

Subaddress 6

Subaddress 7

Subaddress 8

Subaddress 9

Subaddress 10

Subaddress 11

Subaddress 12

Subaddress 13

Subaddress 14

Subaddress 15

Subaddress 16

Subaddress 17

Subaddress 18

Subaddress 19

Subaddress 20

Subaddress 21

Subaddress 22

Subaddress 23

Subaddress 24

Subaddress 25

Subaddress 26

Subaddress 27

Subaddress 28

Subaddress 29

Subaddress 30

Unused

420 to 43F

040 to 05F

060 to 07F

080 to 09F

0A0 to 0BF

0C0 to 0DF

0E0 to 0FF

100 to 11F

120 to 13F

140 to 15F

160 to 17F

180 to 19F

1A0 to 1BF

1C0 to 1DF

1E0 to 1FF

200 to 21F

220 to 23F

240 to 25F

260 to 27F

280 to 29F

2A0 to 2BF

2C0 to 2DF

2E0 to 2FF

300 to 31F

320 to 33F

340 to 35F

360 to 37F

380 to 39F

3A0 to 3BF

3C0 to 3DF

3E0 to 3FF

440 to 45F

460 to 47F

480 to 49F

4A0 to 4BF

4C0 to 4DF

4E0 to 4FF

500 to 51F

520 to 53F

540 to 55F

560 to 57F

580 to 59F

5A0 to 5BF

5C0 to 5DF

5E0 to 5FF

600 to 61F

620 to 63F

640 to 65F

660 to 67F

680 to 69F

6A0 to 6BF

6C0 to 6DF

6E0 to 6FF

700 to 71F

720 to 73F

740 to 75F

760 to 77F

780 to 79F

7A0 to 7BF

7C0 to 7DF

7E0 to 7FF

Notes:

1. Receive mode codes with data:

- Synchronize with data

- Selected Transmitter Shutdown (Illegal)

- Override Selected Transmitter Shutdown (Illegal)

2. Transmit mode codes with data:

- Transmit Vector Word

- Transmit Bit Word

RTI-13

3.0 PIN IDENTIFICATION AND DESCRIPTION

(K3) 13

ADDR IN 0

ADDR IN 1

ADDR IN 2

ADDR IN 3

ADDR IN 4

ADDR IN 5

ADDR IN 6

ADDR IN 7

ADDR IN 8

ADDR IN 9

ADDR IN 10

ADDRESS BUS

ADDR IN(10:0)

BIPHASE

OUT

BIPHASE OUT A O

BIPHASE OUT A Z

27 (L8)

28 (K8)

(K1)

(H2)

(G3)

(G1)

(F3)

(E1)

(F2)

(D2)

(B1)

(B2)

BIPHASE OUT B O

BIPHASE OUT B Z

32 (L11)

30 (L10)

BIPHASE

BIPHASE IN A O

BIPHASE IN A Z

37 (H10)

39 (G9)

BIPHASE IN B O

BIPHASE IN B Z

33 (K10)

34 (J10)

(A1) 74

DATA I/O 0

DATA BUS

DATA(15:0)

(B3) 73

(A2) 72

(A3) 71

(B4) 70

(A4) 69

(C5) 68

(B5) 67

(A5) 66

(A6) 65

(C7) 63

(B6) 61

DATA I/O 1

DATA I/O 2

DATA I/O 3

DATA I/O 4

DATA I/O 5

DATA I/O 6

DATA I/O 7

DATA I/O 8

DATA I/O 9

DATA I/O 10

DATA I/O 11

TERMINAL

ADDRESS

TA0

TA1

TA2

64 (C6)

62 (A7)

60 (B7)

TA3

TA4

58 (B8)

56 (B9)

TALEN/PARITY

52 (C10)

(A8) 59

(A9) 57

(A10) 55

(A11) 53

DATA I/O 12

DATA I/O 13

DATA I/O 14

DATA I/O 15

MODE/CODE

MCSA0

MCSA1

MCSA2

MCSA3

14 (L2)

16 (K4)

17 (L4)

18 (J5)

SUBADDRESS

UT1553B

RTI

(L1) 11

(J2) 10

ADDR OUT 0

ADDR OUT 1

ADDR OUT 2

ADDRESS BUS

ADDR OUT

(10:0)

MCSA4

19 (K5)

(J1)

(H1)

(G2)

(F1)

ADDR OUT 3

ADDR OUT 4

ADDR OUT 5

ADDR OUT 6

ADDR OUT 7

ADDR OUT 8

ADDR OUT 9

ADDR OUT 10

STATUS

SIGNALS

MES ERR

TIMERON

COMSTR

49 (D10)

41 (G11)

22 (J6)

(E3) 84

(E2) 82

(D1) 80

(C1) 78

(C2) 76

MC/SA

RCV

21 (K6)

51 (B11)

XMIT

38 (H11)

45 (E11)

43 (F9)

RRD/RWR

RCS

(L9) 29

(K9) 31

EXT TEST

EXT TST CH SEL A/B

TEST

STATUS

CH A/B

23 (J7)

26 (L6)

(D11) 48

(F11) 47

MEMCK

DMARQ

DMA

BRDCST

36 (J11)

(B10) 54

POWER

CONTROL

SIGNALS

BCEN

25 (K7)

44 (E9)

(K2) 12

(F10) 42

GROUND

RD/WR

CTRL

46 (E10)

50 (C11)

(K11) 35

12MHz

CLOCK

RESET

(L7) 24

(G10) 40

2MHz

MRST

ADOEN

ILL COMM

15 (L3)

20 (L5)

Note:

Pingrid array numbers are in parentheses. LCC pin numbers are not in parentheses.

Figure 7. UT1553B RTI Pin Description

RTI-14

Legend for TYPE and ACTIVE ﬁelds:

TI = TTL input

TO = TTL output

TUI = TTL input (pull-up)

TDI = TTL input (pull-down)

TTO = Three-state TTL output

TTB = Three-state TTL bidirectional

[ ] - Values in parentheses indicate the initialized state of

output pin.

DATA BUS

PIN NUMBER

TYPE

ACTIVE

NAME

DESCRIPTION

LCC

PGA

A11

TTB

DATA I/O 15

Bit 15 (MSB) of the bidirectional Data

bus.

A10

TTB

DATA I/O 14

DATA I/O 13

DATA I/O 12

DATA I/O 11

DATA I/O 10

DATA I/O 9

DATA I/O 8

DATA I/O 7

DATA I/O 6

DATA I/O 5

DATA I/O 4

DATA I/O 3

DATA I/O 2

DATA I/O 1

DATA I/O 0

Bit 14 of the bidirectional Data bus.

Bit 13 of the bidirectional Data bus.

Bit 12 of the bidirectional Data bus.

Bit 11 of the bidirectional Data bus.

Bit 10 of the bidirectional Data bus.

Bit 9 of the bidirectional Data bus.

Bit 8 of the bidirectional Data bus.

Bit 7 of the bidirectional Data bus.

Bit 6 of the bidirectional Data bus.

Bit 5 of the bidirectional Data bus.

Bit 4 of the bidirectional Data bus.

Bit 3 of the bidirectional Data bus.

Bit 2 of the bidirectional Data bus.

Bit 1 of the bidirectional Data bus.

Bit 0 (LSB) of the bidirectional Data bus.

INPUT ADDRESS BUS

PIN NUMBER

TYPE

ACTIVE

NAME

DESCRIPTION

LCC

PGA

ADDR IN 10

ADDR IN 9

ADDR IN 8

ADDR IN 7

ADDR IN 6

ADDR IN 5

ADDR IN 4

ADDR IN 3

ADDR IN 2

ADDR IN 1

ADDR IN 0

Bit 10 (MSB) of the Address Input bus.

Bit 9 of the Address Input bus.

Bit 8 of the Address Input bus.

Bit 7 of the Address Input bus.

Bit 6 of the Address Input bus.

Bit 5 of the Address Input bus.

Bit 4 of the Address Input bus.

Bit 3 of the Address Input bus.

Bit 2 of the Address Input bus.

Bit 1 of the Address Input bus.

Bit 0 (LSB) of the Address Input bus.

RTI-15

OUTPUT ADDRESS BUS

PIN NUMBER

TYPE

ACTIVE

NAME

DESCRIPTION

LCC

PGA

TTO

ADDR OUT 10

ADDR OUT 9

ADDR OUT 8

ADDR OUT 7

ADDR OUT 6

ADDR OUT 5

ADDR OUT 4

ADDR OUT 3

ADDR OUT 2

ADDR OUT 1

ADDR OUT 0

Bit 10 (MSB) of the Address Output bus.

Bit 9 of the Address Output bus.

Bit 8 of the Address Output bus.

Bit 7 of the Address Output bus.

Bit 6 of the Address Output bus.

Bit 5 of the Address Output bus.

Bit 4 of the Address Output bus.

Bit 3 of the Address Output bus.

Bit 2 of the Address Output bus.

Bit 1 of the Address Output bus.

Bit 0 (LSB) of the Address Output bus.

REMOTE TERMINAL ADDRESS INPUTS

PIN NUMBER

TYPE

ACTIVE

NAME

DESCRIPTION

LCC

PGA

TUI

TA4

TA3

TA2

TA1

TA0

Remote Terminal Address bit 4 (MSB).

Remote Terminal Address bit 3.

Remote Terminal Address bit 2.

Remote Terminal Address bit 1.

Remote Terminal Address bit 0.

C10

TALEN/PARITY

Remote Terminal Address Latch Enable/

Remote Terminal Parity Input. Function

of input is deﬁned by he state of pin EXT

TEST and EXT TST CH SEL A/B. For

EXT TEST = 0, EXT TST CH SEL A/B

= 1, TALEN/PARITY must provide odd

parity for the Remote Terminal Address.

For all other states of EXT TEST and

EXT TST CH SEL A/B (i.e., 00, 10, 11)

TALEN/PARITY functions as an active

low address strobe.

;

RTI-16

MODE CODE/SUBADDRESS OUTPUTS

TYPE

ACTIVE

PIN NUMBER

NAME

MC/SA

DESCRIPTION

LCC

PGA

Mode Code/Subaddress Indicator. If MC/SA is

low, it indicates that the most recent command

word is a mode code command. If MC/SA is

high, it indicates that the most recent command

word is for a subaddress. This output indicates

whether the mode code/subaddress outputs

(i.e., MCSA(4:0)) contain mode code or sub-

address information.

MCSA4 19

Mode Code/Subaddress 4. If MC/SA is low,

this pin represents the most signiﬁcant bit of

the the most recent command word (the MSB

of the mode code). If MC/SA is high, this pin

represents the MSB of the subaddress.

MCSA3 18

MCSA2 17

MCSA1 16

MCSA0 14

Mode Code/Subaddress 3.

Mode Code/Subaddress 2.

Mode Code/Subaddress 1.

Mode Code/Subaddress 0. If MC/SA is low,

this pin represents the least signiﬁcant bit of

the the most recent command word. If MC/SA

is high, this pin represents the LSB of the sub-

address

BIPHASE INPUTS

PIN NUMBER

NAME

DESCRIPTION

LCC

PGA

BIPHASE IN A Z

Receiver - Channel A, Zero Input. Idle low

Manchester input from the 1553 bus transceiver.

H10

J10

BIPHASE IN A O

BIPHASE IN B Z

BIPHASE IN B O

Receiver - Channel A, One Input. This input is

thecomplement of BIPHASE IN A Z.

Receiver - Channel B, Zero Input. Idle low

Manchester input from the 1553 bus transceiver.

K10

Receiver - Channel B, One Input. This input is

the complement of BIPHASE IN B Z.

RTI-17

BIPHASE OUTPUTS

PIN NUMBER

TYPE

ACTIVE

NAME

DESCRIPTION

LCC

PGA

BIPHASE OUT A Z

Transmitter - Channel A, Zero Output. This

Manchester-encoded data output is connected

to the 1553 bus transmitter input. The output is

idle low.

BIPHASE OUT A O

BIPHASE OUT B Z

Transmitter - Channel A, One Output. This

output is the complement of BIPHASE OUT

A Z. The output is idle low.

L10

Transmitter - Channel B, Zero Output. This

Manchester-encoded data output is connected

to the 1553 bus transmitter. The output is idle

low.

L11

BIPHASE OUT B O

Transmitter - Channel B, One Output. This

output is the complement of BIPHASE OUT

B Z. The output is idle low.

MASTER RESET AND CLOCK

PIN NUMBER

TYPE

ACTIVE

NAME

DESCRIPTION

LCC

PGA

G10

TUI

MRST

Master Reset. Initializes all internal functions of the

RTI. MRST must be asserted 500 nanoseconds

before normal RTI operation. (500ns minimum).

K11

12MHz

2MHz

12MHz Input Clock. This is the RTI system clock

that requires an accuracy greater than 0.01% with a

duty cycle from 50% ±10%.

2MHz Clock Output. This is a 2MHz output gener-

ated by the 12MHz input clock. This clock is

stopped when MRST is low.

POWER AND GROUND

PIN NUMBER

TYPE

ACTIVE

NAME

DESCRIPTION

+5V . Power supply must be +5V ±10%.

LCC

PGA

B10

PWR

F10

GND

Ground reference. Zero V logic ground.

RTI-18

CONTROL PINS

PIN NUMBER

LCC PGA

44 E9

TYPE

ACTIVE

NAME

DESCRIPTION

Chip Select. Active low input for host access of

transparent memory or the RTI internal registers. In

the transparent memory conﬁguration CS is propa-

gated through the RTI to the RCS output.

C11

CTRL

Control. The host processor uses the active low

CTRL input signal in conjunction with CS and RD/

WR to access the RTI internal registers. CTRL is

also used in the software assignment of the terminal

address and programmed reset.

ADOEN

RD/WR

Address Output Enable. When ADOEN is low the

Address Out bus (ADDR OUT (15:0)) is active. If

ADOEN = 1 the Address Out bus is high impedance.

E10

Read/Write. The host processor uses a high level on

this input in conjunction with CS and CTRL to read

the RTI internal registers. A low level on this input is

used in conjunction with CS and CTRL to write to

internal RTI registers. In the transparent memory

conﬁguration RD/WR is propagated through the RTI

to the RRD/RWR output.

TUI

TDI

BCEN

Broadcast Enable. Active low input enables broad-

cast commands.

ILL COMM

Illegal Command. The host processor uses the ILL

COMM input to inform the RTI that the present

command is illegal. ILL COMM is used in conjunc-

tion with MCSA(4:0) and MC/SA to deﬁne system

dependent illegal commands.

RTI-19

STATUS OUTPUTS

PIN NUMBER

TYPE

ACTIVE

NAME

RCS

DESCRIPTION

LCC

PGA

RAM Chip Select. Active low output used to

enable memory for access.

E11

RRD/RWR

COMSTR

TIMERON

RAM Read/Write. High output enables memory

read, low output enables memory write, used in

conjunction with RCS). Normally high output.

Command Strobe. COMSTR is an active low

output of 500ns duration identifying receipt of a

valid command.

G11

Fail-safe Timer. The TIMERON output pulses

low for 730ms when the RTI begins transmit-

ting (i.e., rising edge of STATUS) to provide a

fail-safe timer meeting the requirements of

MIL-STD-1553B. This pulse is reset when

COMSTR goes low or during Master Reset. in

the external self-test mode TIMERON does not

recognize COMSTR and resets after 730ms.

D10

MES ERR

Message Error. The active high MES ERR out-

put signals that the Message Error bit in the Sta-

tus Register has been set due to receipt of an

invalid command or an error during message

sequence. MES ERR will reset to logic zero on

receipt of next valid command.

H11

B11

J11

CH A/B

XMIT

Channel A/B. Output identifying the channel on

which the most recent valid command was

received. Channel A = 1, Channel B = 0.

Transmit. Active low output identiﬁes a

transmit command message transfer by the RTI

is in progress.

RCV

Receive. Active low output identiﬁes a receive

command message transfer by the RTI is in

progress.

BRDCST

STATUS

Broadcast. BRDCST is an active low output

that identiﬁes receipt of a valid broadcast com-

mand.

Status. Active high output pulse indicating that

the RTI is in the process of transmitting a status

word.

RTI-20

BUS ARBITRATION

PIN NUMBER

TYPE

ACTIVE

NAME

DMARQ

DESCRIPTION

LCC

PGA

F11

Direct Memory Access Request. Active high

output requesting RTI access to memory.

D11

MEMCK

Memory Clock (DMA Grant). Active low input

signaling the RTI that a memory access is

granted. Internal to the RTI, receipt of MEMCK

generates RAM chip select and RAM read/write

signals.

TDI

TUI

EXT TST

External Self-test Enable. Multi-function input

pin. In self-test mode forcing this pin high

allows the monitoring of self-test activity at the

bus stub. When the RTI is not in self-test this

pin deﬁnes the function of TALEN/PARITY.

EXT TST CH SEL

A/B

External Self-test Channel Select. A/B Multi-

function input pin. In self-test mode forcing this

pin high selects the channel on which the self-

test is performed (Channel A = 1, Channel B =

0). When the RTI is not in self-test this pin

deﬁnes the function of TALEN/PARITY.

4.0 OPERATING CONDITIONS

ABSOLUTE MAXIMUM RATINGS

(referenced to VSS)

SYMBOL

PARAMETER

LIMITS

UNIT

DC supply voltage

-0.3 to +7.0

Voltage on any pin

DC input current

Storage temperature

-0.3 to V +0.3

°C

±10

-65 to +150

300

STG

Maximum power dissipation

°C

Maximum junction temperature

Thermal resistance, junction-to-case

+175

°C/W

Note:

1. Stressesoutsidethelistedabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thisisastressratingonly, andfunctional

operation of the device at these or any other conditions beyond limits indicated in the operational sections of this speciﬁcation is not

recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Recommended Operating Conditions

SYMBOL

PARAMETER

LIMITS

4.5 to 5.5

0 to V

UNIT

DC supply voltage

DC input voltage

Temperature range

Operating frequency

-55 to +125

°C

12 ± .01%

MHz

RTI-21

5.0 DC ELECTRICAL CHARACTERISTICS

(VDD = 5.0V ± 10%; -55°C < TC < +125°C)

SYMBOL

PARAMETER

Low-level input voltage

High-level input voltage

CONDITION

MINIMUM MAXIMUM

UNIT

0.8

2.0

Input leakage current

TTL inputs

= V or V

-10

110

-2750

2750

-110

µA

Inputs with pull-down resistors

Inputs with pull-up resistors

= V

Low-level output voltage

High-level output voltage

= 4mA

0.4

= -400µA

2.4

-10

Three-state output

leakage current

= V or V

+10

µA

1, 2

Short-circuit output current

= 5.5V, V = V

= 5.5V, V = 0V

-90

Input capacitance

ƒ = 1MHz @ 0V

ƒ = 12MHz, CL = 50pF

Note 5

1.5

Output capacitance

OUT

Bidirect I/O capacitance

1, 4

Average operating current

Quiescent current

Notes:

1. Supplied as a design limit but not guaranteed or tested.

2. Not more than one output may be shorted at a time for a maximum duration of one second.

3. Measured only for initial qualiﬁcation, and after process or design changes that could affect input/output capacitance.

4. Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching.

Voltage supply should be adequately sized and decoupled to handle a large surge current.

5. All inputs with internal pull-ups or pull-downs should be left open circuit. All other inputs tied high or low.

BIT TIMES

1 2 3

4 5 6 7 8

10 11 12 13 14

15 16 17 18 19

COMMAND

WORD

T/R

DATA WORD COUNT/

MODE CODE

SYNC

REMOTE TERMINAL

ADDRESS

SUBADDRESS/MODE

CODE

DATA WORD

DATA

SYNC

STATUS WORD

REMOTE TERMINAL

RESERVED

ADDRESS

Figure 8. MIL-STD-1553B Word Formats

RTI-22

3, 4

6.0 AC ELECTRICAL CHARACTERISTICS

(Over recommended operating conditions)

MIN

MAX

MIN

MAX

INPUT

MIN

MAX

IN-PHASE

OUTPUT

OUT-OF-PHASE

OUTPUT

MIN

MAX

MIN

MAX

BUS

SYMBOL

PARAMETER

INPUT↑

to response↑

INPUT↓ to response↓

INPUT↑ to response↓

INPUT↓ to response↑

INPUT↓ to data valid

INPUT↓ to high Z

INPUT↑ to high Z

INPUT↑ to data valid

Notes:

1. Timing measurements made at (V_IHMIN + V_ILMAX)/2.

2. Timing measurements made at (V_OLMAX + V_OHMIN)/2.

3. Based on 50pF load.

Figure 9a. Typical Timing Measurements

(source)

REF

90%

REF

∑

10%

50pF

< 2ns

(sink)

REF

Input Pulses

Note:

30pF including scope probe and test socket

Figure 9b. AC Test Loads and Input Waveforms

RTI-23

10a

DMARQ

MEMCK

10b

10e

10d

RCS

10c

10i

10h

RRD/RWR

10g

10f

DATA BUS

ADDR OUT BUS

Figure 10. RTI Memory Write

SYMBOL

PARAMETER

ADDR OUT valid to DMARQ active

MINIMUM

MAXIMUM

UNITS

883

992

10a

10b

10c

2, 3

DMARQ active to MEMCK active

MEMCK active to RCS active

MEMCK inactive to RCS inactive

10d

10e

1, 2, 4

MEMCK pulse width

MEMCK active to DATA bus valid

115

101

10f

MEMCK inactive to DATA bus high

10g

impedance

MEMCK active to RRD/RWR active

10h

10i

MEMCK inactive to RRD/RWR inactive

Notes:

1. Allows a 20ns data valid set-up time before RCS and RRD/RWR go high.

2. The sum t_b+ t_emust not exceed 18.8ms.

3. Supplied as a design limit, but not guaranteed or tested.

4. Guaranteed by test.

RTI-24

11a

DMARQ

MEMCK

RCS

11h

11b

11e

11d

11c

11g

11f

DATA BUS

ADDR OUT BUS

Figure 11. RTI Memory Read

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNITS

ADDR OUT valid to DMARQ active

883

992

11a

14.9

DMARQ active to MEMCK active

µs

11b

MEMCK active to RCS active

11c

MEMCK inactive to RCS inactive

11d

1, 2, 4

MEMCK pulse width

11e

Input DATA valid to MEMCK inactive

Input DATA valid after RCS inactive

11f

11g

DMARQ active to MEMCK inactive

18.3

µs

11h

Notes:

1. Allows a 20ns data valid set-up time before RCS and RRD/RWR go high.

2. The sum t_b+ t_emust not exceed 18.8ms.

3. Supplied as a design limit, but not guaranteed or tested.

4. Guaranteed by test.

RTI-25

ADDR IN (0)

12d

12c

WRITE CONTROL

(CNTRL + CS + RD/WR)

Logical OR

12b

12a

DATA BUS

Figure 12. Control Register Write Timing

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNITS

Input DATA valid before WRITE

CONTROL inactive (set-up time)

12a

12b

Input DATA valid after WRITE

CONTROL inactive (hold-time)

ADDR IN valid before WRITE CONTROL

12c

12d

1, 3

asserts

ADDR IN valid after WRITE CONTROL

2, 3

negates

Notes:

1. Set-up time required to prevent inadvertent software reset.

2. Hold-time required to prevent inadvertent software reset.

3. Guaranteed by test.

RTI-26

ADDR IN (0)

READ CONTROL

(CNTRL + CS )

1, 2

Logical OR

13b

13c

DATA BUS

13a

Figure 13. System and Last Command Register Read Timing

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNITS

DATA bus valid after READ CONTROL

valid whilve ADDR IN (0) = 0 or 1

13a

132

DATA bus valid after ADDR IN (0) = 0 or

1 while READ CONTROL = 0

13b

READ CONTROL negation to DATA bus

13c

101

high impedance

Notes:

1. ADDR IN (0) = 0 System Register read.

2. ADDR IN (0) = 1 Last Command Register read.

3. Supplied as a design limit but not guaranteed or tested.

RTI-27

TIMERON

STATUS

14c

14a

14b

BIPHASE OUT

COMSTR

14d

Figure 14. RT Fail-Safe Timer Signal Relationships

SYMBOL

MINIMUM

MAXIMUM

UNITS

PARAMETER

STATUS active to TIMERON active

14a

TIMERON active to ﬁrst BIPHASE OUT

1.2

14b

transition

TIMERON low pulse width

732

14c

COMSTR active toTIMERON reset

14d

Note:

1. Supplied as a design limit, but not guaranteed or tested.

RTI-28

15b

RCS

15a

RD/WR

15dv

15c

RRD/RWR

ADDR IN BUS

15e

15f

ADDR OUT BUS

ADOEN

15g

15h

15i

15j

MEMCK

Figure 15. RTI Propagation Delays

PARAMETER

SYM-

MINIMUM

MAXIMUM

UNITS

CS active to RCS active

CS negation to RCS negation

RD/WR active to RRD/RWR active

15a

15b

15c

RD/WR negation to RRD/RWR negation

15d

CS active to ADDR OUT valid

15e

ADDR IN valid to ADDR OUT valid

15f

ADOEN negation to ADDR OUT high

15g

impedance

ADOEN active to ADDR OUT active

15h

CS active to MEMCK active

15i

(MEMCK not recognized)

CS negation to MEMCK active

15j

(MEMCK recognized)

Note:

1. Supplied as a design limit, but not guaranteed or tested.

2. Guaranteed by test.

RTI-29

COMMAND

BIPHASE IN

16a

16b

COMSTR

RCV

XMIT

16c

CH A/B

BRDCST

MC/SA

MCSA(4:0)

ADDR OUT

MESS ERR

16e

16d

Figure 16. Command Word Validation

SYMBOL

PARAMETER

MINIMUM

MAXIMUM

UNITS

µs

Command word parity to COMSTR and

3.58

3.67

16a

RCV or XMIT active

µs

502

2.66

COMSTR pulse width

499

2.58

430

16b

Command word parity to CH A/B valid

16c

16d

Status output signals valid to COMSTR

2, 4

active

MES ERR reset after COMSTR active

745

750

16e

Notes:

1. ADOEN is asserted (i.e., logic low).

2. Status signals include BRDCST, MC/SA, MCSA(4:0), and ADDR OUT.

3. Measured from mid-bit parity crossing.

4. Supplied as a design limit, but not guaranteed or tested.

RTI-30

DATA

BIPHASE IN

17a

STATUS

SYNC

BIPHASE OUT

17b

DMARQ

STATUS

RCV

17c

17d

17e

ADDR OUT

Figure 17. Receive Command Message Processing

UNITS

SYMBOL

PARAMETER

MAXIMUM

MINIMUM

µs

Data word parity bit to status word

8.80

9.37

17a

1, 3

response

2, 3

µs

Data word parity bit to DMARQ active

3.58

1.24

4.48

0.90

3.68

1.25

4.98

17b

17c

17d

STATUS active to BIPHASE OUT active

µs

STATUS pulse width

ADDR OUT valid before DMARQ (H)

17e

Notes:

1. Measured from last data word mid-bit parity crossing.

2. Measured from transmitted status word sync ﬁeld mid-bit crossing.

3. Supplied as a design limit, but not guaranteed or tested.

RTI-31

BIPHASE

DMARQ

XMIT

18a

18b

18c

Figure 18. Transmitted Data Timing

UNITS

PARAMETER

MAXIMUM

SYM-

MINIMUM

17.15

µs

DMARQ active to sync ﬁeld of transmitted

data word

17.18

* t

18a

* t

µs

DMARQ active to DMARQ active

19.2

500

18b

18c

XMITnegationafterlastDMARQactive

460

Note:

Supplied as a design limit but not guaranteed or tested.

RTI-32

DATA/CMD

BIPHASE IN

BIPHASE

19a

SYNC STATUS

19b

COMSTR

19c

STATUS

XMIT

19d

19e

19f

19g

MES ERR

Figure 19. Mode Command Message Processing

MAXIMUM

SYMBOL

PARAMETER

MINIMUM

UNITS

Response time BIPHASE IN to BI-

µs

3.58

3.67

19a

PHASE OUT

Command word parity bit to COMSTR asser-

8.80

9.37

19b

tion

µs

1.24

4.48

1.25

4.98

STATUS active to BIPHASE OUT active

STATUS pulse width

19c

19d

3.58

1.00

6.57

3.67

Command word parity bit to XMIT assertion

XMIT pulse width for mode code reception

19e

19f

6.68

Command word parity bit to MES ERR as-

sertion

19g

Notes:

1. Measured from data or command word mid-bit parity crossing.

2. Measured from transmitted status word sync ﬁeld mid-bit crossing.

Supplied as a design limit but not guaranteed or tested.

RTI-33

DATA

BIPHASE IN

MES ERR

20a

RCV CMD

XMIT CMD

BIPHASE IN

MES ERR

20b

Figure 20. Message Error

MAXIMUM

SYMBOL

PARAMETER

MINIMUM

UNITS

Data word parity bit to MES ERR

assertion

µs

23.50

55.4

23.63

20a

Command word parity bit to MES ERR

µs

55.5

20b

assertion RT to RT transfer

Notes:

1. Measured from last data word mid-bit parity crossing.

2. No response from transmitter.

Supplied as a design limit but not guaranteed or tested.

RTI-34

ADDR IN (10:0)

DATA(15:0)

CONTROL

HOST

SUBSYSTEM

UT1553B

RTI

UT63M125

1553 TRANSCEIVER

1553 BUS A

1553 BUS B

Figure 21. RTI General System Diagram (Idle low interface)

IN O

IN Z

RXOUT

BIPHASE

CHANNEL A

TXIN-

CHANNEL A

TXIN

OUT O

OUT Z

UTMC

63M125

RTI

RXOUT

IN O

IN Z

BIPHASE

CHANNEL B

TXINHB

CHANNEL B

OUT O

OUT Z

TXIN

TIMERON

CH A/B

LOGIC

Figure 22. RTI Transceiver Interface Diagram

RTI-35

MC/SA

MCSA0

MCSA1

MCSA2

MCSA3

MCSA4

ILLEGAL

COMMAND

DECODER

RTI

COMSTR

BRDCST

RCV

XMIT

ILL COMM

Figure 23. Mode Code/Subaddress Illegalization Circuit

BIPHASE IN C

COMSTR

COMMAND

P D

DATA

P D

DATA

DMARQ

MEMCK

RRD/RWR

ADDR OUT BUS

VALID

DATA

BUS

STATUS

SS STATUS WORD

BIPHASE OUT

Figure 24. Receive Command with Two Data Words

RTI-36

BIPHASE IN CS COMMAND

COMSTR

XMIT

DMARQ

MEMCK

RCS

RRD/RWR

ADDR OUT BUS

VALID

DATA

BUS

STATUS

STATUS WORD

DATA WORD

BIPHASE OUT

Figure 25. Transmit Command with Two Data Words

RTI-37

PACKAGE OUTLINE DRAWINGS

F10

ADDR OUT 5

ADDR IN 7

ADDR IN 5

RCS

DMARQ

ADDR OUT 2

ADDR OUT 1

MCSA 3

ADDR OUT 0

MCSA 0

ADDR OUT 9

ADDR OUT 10

DATA I/O 6

TA 0

DATA I/O 0

DATA I/O 2

DATA I/O 3

DATA I/O 5

DATA I/O 8

DATA I/O 9

TA 1

ADOEN

COMSTR

MCSA 2

STATUS

BIPHASE IN B Z

BRDCST

ILL COMM

CH A/B

DATA I/O 10

J10

J11

C10 TALEN/PARITY

C11 CTRL

F11

2MHz

BIPHASE OUT A

EXT TEST

DATA I/O 12

DATA I/O 13

ADDR IN 4

ADDR OUT 4

ADDR IN 3

BIPHASE IN A Z

MRST

ADDR IN 1

D10

D11

ADDR OUT 8

ADDR IN 8

MES ERR

MEMCK

L10 BIPHASE OUT B

L11 BIPHASE OUT B

A10 DATA I/O 14

A11 DATA I/O 15

ADDR IN 0

G10

G11

MCSA 1

B10

ADDR IN 9

ADDR IN 10

DATA I/O 1

DATA I/O 4

DATA I/O 7

DATA I/O 11

TA 2

TIMERON

MCSA 4

ADDR IN 6

ADDR OUT 7

ADDR OUT 6

RD/WR

RRD/RWR

MC/SA

H10

H11

ADDR OUT 3

ADDR IN 2

BIPHASE IN A O

XMIT

BCEN

BIPHASE OUT A Z

EXT TST CH SEl A/B

E10

E11

K10 BIPHASE IN B O

K11 12MHz

TA 3

TA 4

B11 RCV

Figure 26a. UT1553B RTI Pingrid Array Conﬁguration

(Bottom View)

RTI-38

11 10

84 83 82 81 80 79 78 77 76 75

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

ADDR IN 5

MCSA 4

BIPHASE IN A O

XMIT

DATA I/O 14

TA4

DATA I/O 1

ADDR OUT 5

ADDR IN 4

ILL COMM

DATA I/O 0

MC/SA

BIPHASE IN A Z

MRST

DATA I/O 13

TA3

ADDR IN 10

ADDR OUT 10

ADDR IN 9

ADDR OUT 4

ADDR IN 3

COMSTR

STATUS

TIMERON

DATA I/O 12

TA2

ADDR OUT 3

ADDR IN 2

2MHz

ADDR OUT 9

ADDR IN 8

BCEN

DATA I/O 11

TA1

RCS

RRD/RWR

RD/WR

ADDR OUT 2

ADDR IN 1

CH A/B

ADDR OUT 8

ADDR IN 7

BIPHASE OUT A O

BIPHASE OUT A Z

EXT TEST

DATA I/O 10

TA0

ADDR OUT 1

ADDR OUT 0

ADDR OUT 7

ADDR IN 6

DATA I/O 9

DATA I/O 8

DATA I/O 7

DATA I/O 6

DATA I/O 5

DATA I/O 4

DATA I/O 3

DATA I/O 2

DMARQ

MEMCK

MES ERR

CTRL

BIPHASE OUT B Z

EXT TST CH SEL A/B

BIPHASE OUT B O

BIPHASE IN B O

BIPHASE IN B Z

12MHz

ADDR OUT 6

ADDR IN 0

MCSA0

ADOEN

MCSA1

MCSA2

MCSA3

RCV

TALEN/PARITY

DATA I/O 15

BRDCST

Figure 26b. UT1553B RTI Chip Carrier Conﬁguration

(Top View)

RTI-39

Package Selection Guide

Product

RTI RTMP RTR BCRT BCRTM BCRTMP RTS XCVR

24-pin DIP

(single cavity)

36-pin DIP

(dual cavity)

68-pin PGA

84-pin PGA

144-pin PGA

84-lead LCC

36-lead FP

(dual cavity)

(50-mil ctr)

84-lead FP

132-lead FP

NOTE:

1. 84LCC package is not available radiation-hardened.

Packaging-1

0.130 MAX.

1.565 ± 0.025

-A-

0.040 REF.

0.050 ± 0.010

0.080 REF.

(2 Places)

0.130 ±0.010

0.100 REF.

(4 Places)

1.565 ± 0.025

-B-

PIN 1 I.D.

(Geometry Optional)

-C-

(Base Plane)

TOP VIEW

0.100

TYP.

0.018 ± 0.002

0.030 C A

0.010

SIDE VIEW

D1/E1

1.400

4 5 6 7 8 9 10 11 12 13 14 15

PIN 1 I.D.

(Geometry Optional)

0.003 MIN. TYP.

BOTTOM VIEW

Notes:

1. True position applies to pins at base plane (datum C).

2. True position applies at pin tips.

3. All package finishes are per MIL-M-38510.

4. Letter designations are for cross-reference to MIL-M-38510.

144-Pin Pingrid Array

Packaging-2

D/E

0.110

0.006

1.525 ± 0.015 SQ.

D1/E1

0.950 ± 0.015 SQ.

PIN 1 I.D.

(Geometry

Optional)

0.025

SEE DETAIL A

LEAD KOVAR

TOP VIEW

0.005

+ 0.002

- 0.001

0.250

MIN.

REF.

SIDE VIEW

0.005 MIN. TYP.

0.018 MAX. REF.

0.014 MAX. REF.

(At Braze Pads)

DETAIL A

BOTTOM VIEW A-A

Notes:

1. All package finishes are per MIL-M-38510.

2. Letter designations are for cross-reference to MIL-M-38510.

132-Lead Flatpack (25-MIL Lead Spacing)

Packaging-3

0.115 MAX.

D/E

1.150 ± 0.015 SQ.

0.080 ± 0.008

PIN 1 I.D.

(Geometry Optional)

TOP VIEW

SIDE VIEW

L/L1

0.050 ± 0.005 TYP.

0.040 x 45_

REF. (3 Places)

0.025 ± 0.003

0.050

0.015 MIN.

0.020 X 455 REF.

PIN 1 I.D.

(Geometry Optional)

BOTTOM VIEW A-A

Notes:

1. All package finishes are per MIL-M-38510.

2. Letter designations are for cross-reference to MIL-M-38510.

84-LCC

Packaging-4

D/E

1.810 ± 0.015 SQ.

0.110

0.060

D1/E1

1.150 ± 0.012 SQ.

PIN 1 I.D.

(Geometry

Optional)

0.050

0.016 ± 0.002

SEE DETAIL A

LEAD KOVAR

TOP VIEW

0.007 ± 0.001

SIDE VIEW

0.260

MIN.

REF.

0.005 MIN. TYP.

0.018 MAX. REF.

0.014 MAX.

REF.

(At Braze Pads)

DETAIL A

BOTTOM VIEW A-A

Notes:

1. All package finishes are per MIL-M-38510.

2. Letter designations are for cross-reference to MIL-M-38510.

84-Lead Flatpack (50-MIL Lead Spacing)

Packaging-5

0.130 MAX.

-A-

1.100 ± 0.020

0.050 ± 0.010

0.130 ± 0.010

1.100 ± 0.020

PIN 1 I.D.

(Geometry Optional)

-B-

-C-

TOP VIEW

(Base Plane)

0.018 ± 0.002

0.100

TYP.

0.030 C A

0.010

SIDE VIEW

D1/

1.000

8 9 10 11

PIN 1 I.D.

(Geometry Optional)

0.003 MIN.

BOTTOM VIEW A-A

Notes:

1. True position applies to pins at base plane (datum C).

2. True position applies at pin tips.

3. All packages finishes are per MIL-M-38510.

4. Letter designations are for cross-reference to MIL-M-38510.

84-Pin Pingrid Array

Packaging-6

0.130 MAX.

0.050 ± 0.010

-A-

1.100 ± 0.020

0.130 ± 0.010

1.100 ± 0.020

-B-

PIN 1 I.D.

(Geometry Optional)

-C-

(Base Plane)

TOP

0.010 ± 0.002

0.100

0.030

0.010

TYP.

SIDE VIEW

D1/E1

1.00

10 11

PIN 1 I.D.

(Geometry Optional)

0.003 MIN. TYP.

BOTTOM VIEW A-A

Notes:

True position applies to pins at base plane (datum C).

True position applies at pin tips.

3. All packages finishes are per MIL-M-38510.

4. Letterdesignationsareforcross-referencetoMIL-M-38510.

68-Pin Pingrid Array

Packaging-7

0.490

MIN.

0.750 ± 0.015

0.015 ± 0.002

1.800 ± 0.025

0.10

PIN 1 I.D.

(Geometry Optional)

TOP VIEW

+ 0.002

- 0.001

0.008

0.130 MAX.

END VIEW

0.080 ± 0.010

(At Ceramic Body)

Notes:

All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to

aheatremovalraillocatedontheprintedcircuitboard.

A thermally conductive material such as MERECO XLN-589 or

equivalent should be used.

3. Letter designations are for cross-reference to MIL-M-38510.

36-Lead Flatpack, Dual Cavity (100-MIL Lead Spacing)

Packaging-8

0.700 + 0.015

0.330

MIN.

0.016 + 0.002

1.000 ± 0.025

0.050

PIN 1 I.D

(Geometry Optional)

TOP

+ 0.002

- 0.001

0.007

0.100 MAX.

0.070 + 0.010

(At Ceramic Body)

END

Notes:

1. All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to

a heat removal rail located on the printed circuit board.

A thermally conductive material such as MERECO XLN-589

or equivalent should be used.

3. Letter designations are for cross-reference to MIL-M-38510.

36-Lead Flatpack, Dual Cavity (50-MIL Lead Spacing)

Packaging-9

0.005 MIN.

0.590 ± 0.012

0.005 MAX.

0.100

1.800 ± 0.025

0.018 ± 0.002

PIN 1 I.D.

(Geometry Optional)

L/L1

0.150 MIN.

0.155 MAX.

TOP VIEW

SIDE VIEW

Notes:

1. All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to

a heat removal rail located on the printed circuit board.

A thermally conductive material such as MERECO XLN-589

or equivalent should be used.

+ 0.002

0.010

- 0.001

0.600 + 0.010

(At Seating Plane)

3. Letter designations are for cross-reference to MIL-M-38510.

END VIEW

36-Lead Side-Brazed DIP, Dual Cavity

Packaging-10

0.005 MIN.

0.590 ± 0.015

0.005 MAX.

0.100

1.200 ± 0.025

0.018 ± 0.002

L/L1

0.150 MIN.

PIN 1 I.D.

(Geometry Optional)

0.140 MAX.

SIDE VIEW

TOP VIEW

Notes:

1. All package finishes are per MIL-M-38510.

2. It is recommended that package ceramic be mounted to

a heat removal rail located on the printed circuit board.

A thermally conductive material such as MERECO XLN-589 or

equivalent should be used.

+ 0.002

- 0.001

0.010

0.600 + 0.010

(At Seating Plane)

3. Letter designations are for cross-reference to MIL-M-38510.

END VIEW

24-Lead Side-Brazed DIP, Single Cavity

Packaging-11

ORDERING INFORMATION

UT1553B RTI Remote Terminal Interface:

5962

Lead Finish:

(A)

(C)

(X)

Solder

Gold

Optional

Case Outline:

(Z) 84 pin PGA

Class Designator:

(B) Jan Class Q

Device Type

01 = 10% to 35% Clock Duty Cycle

Drawing Number: JM38510/555

Total Dose:

(-)

None

Federal Stock Class Designator: No options

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).

UT1553B RTI Remote Terminal Interface

UT1553B -

Lead Finish:

(A)

(C)

(X)

Solder

Gold

Optional

Screening:

(C)

(P)

Military Temperature

Prototype

Package Type:

(G) 84 pin PGA

Modifier:

RTI = 10% to 35% Clock Duty Cycle

UTMC Core Part Number

Notes:

1. Lead finish (A, C, or X) must be specified.

2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).

3. Mil Temp range flow per UTMC’s manufacturing flows document. Devices are tested at -55°C, room temperature, and 125°C.

4. Prototpe flow per UTMC’s document manufacturing flows and are tested at 25°C only. Lead finish is GOLD only.

5. Prototypes and reduced high-reliability devices are only available with 40% to 60% clock duty cycle.

UT1553BRTIGPX [ETC]

相关型号：

UT1553BRTIGPXA

UT1553BRTIGPXC

UT1553BRTR

UT1553BRTR-GA

UT1553BRTR-GC

UT1553BRTR-GX

UT1553BRTR-GXA

UT1553BRTR-GXC

UT16N10G-K08-3030-R

UT16N10G-TA3-R

UT16N10G-TN3-R

UT16N10L-K08-3030-R