UT62L25616BS-70LI [ETC]
256K X 16 BIT LOW POWER CMOS SRAM; 256K x 16位低功耗CMOS SRAM
| 型号： | UT62L25616BS-70LI |
| 厂家： | 
ETC |
| 描述： | 256K X 16 BIT LOW POWER CMOS SRAM |
| 文件： | 总12页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
FEATURES
GENERAL DESCRIPTION
The UT62L25616(I) is a 4,194,304-bit low power
CMOS static random access memory organized as
262,144 words by 16 bits.
ꢀ Fast access time : 55/70/100 ns
ꢀ CMOS Low operating power
Operating current: 45/35/25mA (Icc max)
Standby current: 20 uA(TYP.) L-version
3 uA(TYP.) LL-version
The UT62L25616(I) operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are fully
TTL compatible.
ꢀ Single 2.7V~3.6V power supply
ꢀ Operating temperature:
℃
℃
Industrial : -40 ~85
The UT62L25616(I) is designed for low power system
applications. It is particularly suited for use in
high-density high-speed system applications.
ꢀ All inputs and outputs TTL compatible
ꢀ Fully static operation
ꢀ Three state outputs
ꢀ Data retention voltage: 1.5V (min)
PIN DESCRIPTION
ꢀ Data byte control :
(I/O1~I/O8)
(I/O9~I/O16)
Ⅱ
LB
UB
SYMBOL
DESCRIPTION
Address Inputs
ꢀ Package : 44-pin 400mil TSOP
A0 - A17
48-pin 6mm × 8mm TFBGA
I/O1 - I/O16
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-Byte Control
High-Byte Control
CE
WE
OE
LB
UB
VCC
VSS
NC
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
Power Supply
A3
.
Ground
V
MEMORY ARRAY
CC
A4
ROW
No Connection
2048 Rows x 128 Columns x 16 bits
.
.
A8
A13
A14
A15
A16
A17
DECODER
V
SS
.
. .
I/O
CONTROL
I/O1
.
.
.
.
.
.
.
.
COLUMN I/O
I/O16
CE
COLUMN DECODER
WE
LOGIC
OE
CONTROL
LB
UB
A9 A10 A11 A12 A5 A6 A7
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80054
1
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
PIN CONFIGURATION
A4
A5
A6
A7
1
44
A
A3
NC
A0
A1
A4
A2
CE
2
43
42
LB
OE
UB
3
A2
B
C
D
E
F
4
41
40
39
I/O9
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
Vcc
A3
I/O1
OE
UB
5
6
I/O10 I/O11
A5
A6 I/O2 I/O3
LB
7
8
9
I/O16
38
37
I/O15
I/O14
I/O12
Vss
Vcc
Vss
A17 A7 I/O4
36
35
34
10
11
I/O13
Vss
Vcc
I/O12
I/O13
Vcc
NC
A16 I/O5
A15 I/O6
12
13
Vss
I/O5
33
32
I/O15 I/O14
A14
I/O7
I/O8
NC
G
H
I/O6
I/O16
I/O11
NC
A8
14
15
31
A12 A13
WE
I/O7
I/O8
WE
30
29
I/O10
I/O9
NC
A9 A10 A11
16
17
28
27
NC
A8
A17
18
A9
A10
A16
A15
19
20
26
25
1
2
3
4
5
6
A14
A13
21
22
A11
A12
24
23
TFBGA
TSOP II
TRUTH TABLE
MODE
I/O OPERATION
SUPPLY CURRENT
CE
OE
WE
LB
UB
I/O1-I/O8
I/O9-I/O16
High – Z
High – Z
High – Z
High – Z
High – Z
DOUT
Standby
H
X
L
L
L
L
L
L
L
L
X
X
H
X
L
X
X
H
X
H
H
H
L
X
H
X
H
L
X
H
X
H
H
L
High – Z
High – Z
High – Z
High – Z
DOUT
ISB, ISB1
ISB, ISB1
Output
Disable
Read
ICC,ICC1,ICC2
ICC,ICC1,ICC2
L
H
L
High – Z
DOUT
L
L
DOUT
Write
X
X
X
L
H
L
DIN
High – Z
DIN
ICC,ICC1,ICC2
L
H
L
High – Z
DIN
L
L
DIN
Note: H = VIH, L=VIL, X = Don't care.
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
P80054
2
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
VTERM
TA
TSTG
PD
IOUT
Tsolder
RATING
-0.5 to 4.6
-40 to 85
-65 to +150
1
50
260
UNIT
V
Terminal Voltage with Respect to VSS
Operating Temperature
Storage Temperature
Power Dissipation
DC Output Current
Soldering Temperature (under 10 secs)
Industrial
℃
℃
W
mA
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
℃
℃
DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, TA = -40 to 85 (I))
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. UNIT
Power Voltage
VCC
VIH
VIL
ILI
2.7 3.0
3.6
V
V
V
Input High Voltage
2.0
-0.2
- 1
- 1
2.2
-
-
-
VCC+0.3
Input Low Voltage
0.6
1
Input Leakage Current
Output Leakage Current
-
A
≦
≦
VSS VIN VCC
µ
µ
ILO
-
1
-
0.4
45
35
25
5
A
≦
≦
VSS VI/O VCC; Output Disabled
Output High Voltage
Output Low Voltage
Operating Power
Supply Current
VOH
VOL
ICC
IOH= -1mA
-
V
V
mA
mA
mA
mA
IOL= 2.1mA
-
Cycle time=min, 100%duty,
55
70
-
30
25
20
4
-
I/O=0mA,
=V ;
CE
IL
100
-
Average Operation
Current
Icc1
Icc2
ISB
-
Cycle time=1 s,100%duty,I/O=0mA,
µ
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
CE
Cycle time=500ns,100%duty,I/O=0mA,
-
-
8
10
mA
mA
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
CE
CE
CE
Standby Current (TTL)
Standby Current (CMOS) ISB1
0.3
0.5
=VIH, other pins =VIL or VIH,
-L
-LL
-
-
20
3
80
25
A
µ
A
µ
=V -0.2V,
CC
other pins at 0.2V or Vcc-0.2V,
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
3
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
℃
CAPACITANCE (TA=25 , f=1.0MHz)
PARAMETER
SYMBOL
MIN.
MAX
UNIT
pF
pF
Input Capacitance
Input/Output Capacitance
CIN
6
8
-
-
CI/O
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
5ns
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
1.5V
CL = 30pF, IOH/IOL = -1mA / 2.1mA
℃
℃
to 85 (I))
AC ELECTRICAL CHARACTERISTICS
(VCC =2.7V~3.6V, TA = -40
(1) READ CYCLE
PARAMETER
SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT
MIN.
MAX.
-
MIN.
MAX.
-
MIN.
MAX.
-
Read Cycle Time
tRC
55
-
70
-
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
55
55
30
-
70
70
35
-
-
-
100
100
50
-
Chip Enable Access Time
tACE
-
-
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
tOE
-
-
-
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
10
5
-
10
5
-
10
5
-
-
-
-
20
20
-
25
25
-
30
30
-
-
-
-
5
5
5
tBA
-
55
-
70
-
100
,
Access Time
LB UB
tHZB
tLZB
-
0
25
-
-
0
30
-
-
0
40
-
ns
ns
,
to High-Z Output
to Low-Z Output
LB UB
,
LB UB
(2) WRITE CYCLE
PARAMETER
SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT
MIN.
55
50
50
0
MAX.
MIN.
70
60
60
0
MAX.
MIN.
100
80
80
0
MAX.
Write Cycle Time
tWC
tAW
tCW
tAS
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
-
-
-
-
-
-
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
tWP
tWR
tDW
tDH
45
0
-
55
0
-
70
0
-
-
-
-
25
0
-
30
0
-
40
0
-
-
-
-
tOW*
tWHZ*
tBW
5
-
5
-
5
-
-
30
-
-
30
-
-
40
-
45
60
80
,
Valid to End of Write
LB UB
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
4
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2,4)
tRC
Address
tAA
tOH
tOH
DOUT
Data Valid
READ CYCLE 2 (
and
Controlled)
(1,3,5,6)
OE
CE
t
RC
Address
CE
t
t
AA
ACE
t
BA
LB , UB
OE
t
BLZ
t
OE
t
CHZ
t
OHZ
t
CLZ
t
OH
t
OLZ
HIGH-Z
HIGH-Z
Dout
Data Valid
t
BHZ
Notes :
1.
2. Device is continuously selected
is HIGH for read cycle.
CE
3. Address must be valid prior to or coincident with
WE
=VIL.
transition; otherwise tAA is the limiting parameter.
CE
4.
is LOW.
OE
±
5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
5
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
WRITE CYCLE 1 (
Controlled)
(1,2,3,5)
WE
t
WC
Address
t
AW
CE
t
CW
t
WR
t
AS
t
t
WP
BW
WE
LB , UB
t
WHZ
t
OW
High-Z
Dout
Din
(4)
(4)
t
DW
t
DH
Data Valid
WRITE CYCLE 2 (
Controlled)
(1,2,5)
CE
t
WC
Address
t
AW
CE
t
AS
t
t
CW
WP
t
WR
WE
LB , UB
Dout
t
BW
t
WHZ
High-Z
t
DH
t
DW
Din
Data Valid
Notes :
1.
or
must be HIGH during all address transitions.
CE
WE
2. A write occurs during the overlap of a low
and a low
.
CE
controlled with write cycle with
WE
3. During a
LOW, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data
OE
WE
to be placed on the bus.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
transition occurs simultaneously with or after
transition, the outputs remain in a
LOW
LOW
CE
WE
high impedance state.
±
6. tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
6
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
℃
℃
DATA RETENTION CHARACTERISTICS (TA =
)
-40 to 85 (I)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX. UNIT
Vcc for Data Retention
VDR
1.5
-
3.6
V
≧
V
CC-0.2V
CE
Data Retention Current
IDR
Vcc=1.5V
- L
- LL
-
-
0
1
0.5
-
50
20
-
A
µ
µ
A
≧
V
CC-0.2V
CE
Chip Disable to Data
Retention Time
Recovery Time
tCDR
tR
See Data Retention
Waveforms (below)
ms
5
-
-
ms
DATA RETENTION WAVEFORM
Data Retention Mode
VCC
2.7V
2.7V
tR
VDR ≧ 1.5V
tCDR
CE
CE ≧ VCC -0.2V
VSS
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
7
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
PACKAGE OUTLINE DIMENSION
Ⅱ
44 pin 400mil TSOP-
Package Outline Dimension
SYMBOLS DIMENSIONS IN MILLMETERS
DIMENSIONS IN INCHS
MIN
1.00
0.05
0.95
0.30
0.12
18.313
11.854
10.058
-
NOM
-
MAX.
1.20
0.15
1.05
0.45
0.21
18.517
11.838
10.282
-
MIN.
0.039
0.002
0.037
0.012
0.0047
0.721
0.460
0.398
-
NOM.
-
MAX.
0.047
0.006
0.041
0.018
0.083
0.728
0.470
0.404
-
A
A1
A2
b
-
-
1.00
0.35
-
0.039
0.014
-
c
D
18.415
11.836
10.180
0.800
0.50
0.805
-
0.725
0.466
0.400
0.0315
0.020
0.0317
-
E
E1
e
L
0.40
-
0.60
-
0.0157
-
0.0236
-
2D
y
0.00
0.076
0.000
0.003
0o
-
5o
0o
-
5o
Θ
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
8
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
48 pin 6mm×8mm TFBGA Outline Dimension
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
9
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
ORDERING INFORMATION
INDUSTRIAL TEMPERATURE
PART NO.
ACCESS TIME
STANDBY CURRENT
PACKAGE
(ns)
(µA) TYP.
UT62L25616MC-55LI
UT62L25616MC-55LLI
UT62L25616MC-70LI
UT62L25616MC-70LLI
UT62L25616BS-55LI
UT62L25616BS-55LLI
UT62L25616BS-70LI
UT62L25616BS-70LLI
55
20
Ⅱ
44 PIN TSOP-
55
70
70
55
55
70
70
3
20
3
Ⅱ
44 PIN TSOP-
Ⅱ
44 PIN TSOP-
Ⅱ
44 PIN TSOP-
20
3
20
3
48 PIN TFBGA
48 PIN TFBGA
48 PIN TFBGA
48 PIN TFBGA
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
10
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
REVISION HISTORY
REVISION
DESCRIPTION
DATE
Preliminary Rev. 0.5 Original.
Mar, 2001
Jul 4,2001
Rev. 1.0
1. The symbols CE# and OE# and WE# are revised as.CE
and OE and WE .
2. Separate Industrial and Consumer SPEC.
3. Add access time 55ns range.
4. The power supply is revised: 3.3Vꢁ3.6V
1. Revised PIN CONFIGURATION :
Rev 1.0 : No A17 pinꢂtyping error
Rev 1.1 : add A17 pin.
Rev. 1.1
Oct 18,2001
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
11
UTRON
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
Rev. 1.1
THIS PAGE IS LEFT BLANK INTENTIONALLY.
UTRON TECHNOLOGY INC.
P80054
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
12
相关型号：
©2020 ICPDF网 联系我们和版权申明