VS1001K [ETC]
MPEG AUDIO CODEC; MPEG音频编解码器
| 型号： | VS1001K |
| 厂家： | 
ETC |
| 描述： | MPEG AUDIO CODEC |
| 文件： | 总39页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VS1001K
DATASHEET
VS1001k - MPEG AUDIO CODEC
Features
Description
• MPEG audio layer 3 decoder (ISO11172-3)
• Supports MPEG 1 & 2, and 2.5 extensions,
VS1001k is a single-chip solution for an MPEG
layer 3 audio decoder. The chip contains a high-
performance low-power DSP processor (VS DSP),
working memory, 4 KiB program RAM and 0.5
KiB data RAM for user applications, serial con-
trol and input data interfaces, and a high-quality
oversampling variable-sample-rate stereo DAC, fol-
lowed by an earphone amplifier and a ground buffer.
all their sample rates and bit rates, in mono
and stereo
• Supports PCM input
• Supports VBR (variable bitrate)
• Can be used as a slave co-processor
• Operates with single clock 12..13 MHz or
24..26 MHz
• Extremely low-power operation
• On-chip high-quality stereo DAC with no
VS1001k receives its input bitstream through a
serial input bus, which it listens to as a system
slave. The input stream is decoded and passed
through a analog/digital hybrid volume control to
an 18-bit oversampling multi-bit sigma-delta DAC.
The decoding is controlled via a serial control bus.
In addition to the basic decoding, it is possible to
add application specific features, like DSP effects,
to the user RAM memory.
phase error between channels
• Internal Op-Amp in BGA-49 and LQFP-48
packages
• Stereo earphone driver capable of driving a
30 load.
• Separate 2.5 .. 3.6V operating voltages for
analog and digital
• 4 KiB On-chip RAM for user code
• Serial control and data interfaces
• New functions may be added with software
VS1001
audio
L
stereo ear−
phone driver
stereo
DAC
R
output
DREQ
serial
DCLK
data
SDATA
BSYNC
x−ROM
x−RAM
y−RAM
y−ROM
SDI
Bus
interface
X Bus
VS_DSP
SCI
Bus
SO
serial
control
interface
SI
SCLK
XCS
Y Bus
I Bus
program
RAM
program
ROM
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CONTENTS
Contents
1
2
License
7
7
Characteristics & Specifications
2.1 Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 DAC Interpolation Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 DAC Interpolation Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
8
8
8
8
9
9
2.8 Switching Characteristics - Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 Switching Characteristics - DREQ Signal . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Switching Characteristics - SPI Interface Output . . . . . . . . . . . . . . . . . . . . . . 10
2.11 Switching Characteristics - Boot Initialization . . . . . . . . . . . . . . . . . . . . . . . 10
3
Packages and Pin Descriptions
11
3.1 SOIC-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 BGA-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 LQFP-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
5
6
Connection Diagram, SOIC-28
Connection Diagram, BGA-49 and LQFP-48
SPI Buses
14
15
16
6.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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CONTENTS
6.2 SPI Bus Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Serial Protocol for Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . 16
6.4 Serial Protocol for Serial Command Interface (SCI) . . . . . . . . . . . . . . . . . . . . 17
6.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4.2 SCI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4.3 SCI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.5 SPI Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
Functional Description
20
7.1 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.2 Data Flow of VS1001k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3 Serial Data Interface (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.4 Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5.1 MODE (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5.2 STATUS (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.5.3 INT FCNTLH (-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.5.4 CLOCKF (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.5.5 DECODE TIME (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.5.6 AUDATA (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5.7 WRAM (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5.8 WRAMADDR (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5.9 HDAT0 and HDAT1 (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5.10 AIADDR (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5.11 VOL (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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CONTENTS
7.5.12 RESERVED (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.5.13 AICTRL[x] (RW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6 Stereo Audio DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Operation
28
8.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.3 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.4 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.5 Play/Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.6 Sanity Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.7 PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.8 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.8.1 Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.8.2 SCI Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.8.3 Sine Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9
Writing Software
32
9.1 When to Write Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.2 The Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.3 User’s Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.4 Hardware Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.4.1 SCI Registers, 0x4000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.4.2 Serial Registers, 0x4100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.4.3 DAC Registers, 0x4200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9.4.4 Interrupt Registers, 0x4300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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CONTENTS
9.5 System Vector Tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5.1 AudioInt, 0x4000..0x4001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5.2 SpiInt, 0x4002..0x4003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5.3 DataInt, 0x4004..0x4005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.5.4 UserCodec, 0x4008..0x4009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.6 System Vector Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.6.1 WriteIRam(), 0x4010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.6.2 ReadIRam(), 0x4011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.6.3 DataWords(), 0x4012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.6.4 GetDataByte(), 0x4013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.6.5 GetDataWords(), 0x4014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10 VS1001 Version Changes
37
10.1 Changes Between VS1001h and Production Version VS1001k, 2001-08 . . . . . . . . . 37
10.2 Changes Between VS1001g and VS1001h, 2001-05 . . . . . . . . . . . . . . . . . . . . 37
10.3 Changes Between VS1001d to VS1001g, 2001-03 . . . . . . . . . . . . . . . . . . . . . 37
11 Document Version Changes
38
11.1 Changes Between Version 4.10 and 4.11 for VS1001k, 2003-09 . . . . . . . . . . . . . 38
11.2 Changes Between Version 4.08 and 4.10 for VS1001k, 2003-07 . . . . . . . . . . . . . 38
11.3 Changes Between Version 4.07 and 4.08 for VS1001k, 2003-03 . . . . . . . . . . . . . 38
11.4 Changes Between Version 4.06 and 4.07 for VS1001k, 2003-03 . . . . . . . . . . . . . 38
11.5 Changes Between Version 4.05 and 4.06 for VS1001k, 2002-09 . . . . . . . . . . . . . 38
11.6 Changes Between Version 4.03 and 4.05 for VS1001k, 2002-08 . . . . . . . . . . . . . 38
12 Contact Information
39
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LIST OF FIGURES
List of Figures
1
2
3
4
5
6
7
8
9
Pin Configuration, SOIC-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Configuration, BGA-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Configuration, LQFP-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical Connection Diagram Using SOIC-28. . . . . . . . . . . . . . . . . . . . . . . . 14
Typical Connection Diagram Using BGA-49. . . . . . . . . . . . . . . . . . . . . . . . 15
BSYNC Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SCI Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SCI Word Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
10 Data Flow of VS1001k. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
11 Built-In Bass/Treble Enhancer Frequency Response at 44.1 kHz. . . . . . . . . . . . . . 23
12 User’s Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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1. LICENSE
1 License
MPEG Layer-3 audio decoding technology licensed from Fraunhofer IIS and THOMSON multimedia.
Supply of this product only conveys a license for private, non-commercial use.
2 Characteristics & Specifications
Unless otherwise noted: AVDD=2.9..3.6V, DVDD=2.3..3.6V, TA=-30..+85◦C, XTALI=24.576MHz, Full-
Scale Output Sinewave at 1.526 kHz, measurement bandwidth 20..20000 Hz, analog output load 30 (no
ground buffer) or 100 (with ground buffer), bitstream 128 kbits/s, local components as shown in Figures
4 and 5.
Note, that some analog values are in practice better than in these tables if chips are used within a limited
temperature range and not too close to lower voltage limits.
2.1 Analog Characteristics
Parameter
Symbol Min Typ Max Unit
DAC Resolution
Total Harmonic Distortion
Dynamic Range (DAC unmuted, A-weighted)
S/N Ratio (full scale signal)
Interchannel Isolation
16
0.1
90
87
75
bits
%
dB
dB
dB
THD
IDR
SNR
0.2
70
50
Interchannel Gain Mismatch
Frequency Response
Frequency Response, AVDD = 2.8V
Full Scale Output Voltage (Peak-to-peak)
Deviation from Linear Phase
Out of Band Energy
Out of Band Energy with Analog Filter
Analog Output Load Resistance, no ground buffer AOLR1
Analog Output Load Resistance, ground buffer
Analog Output Load Capacitance
-0.5
-0.1
-0.3
0.5 dB
0.1 dB
0.3 dB
2.0 Vpp
1.4 1.81
◦
5
-60
-90
302
dB
dB
16
16 1002
AOLR2
1000 pF
1 3.6 volts can be achieved with +-to-+ wiring for mono difference sound.
2 AOLR1/2 may be much lower, but below Typical distortion performance may be compromised.
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2. CHARACTERISTICS & SPECIFICATIONS
2.2 Power Consumption
Parameter
Symbol Min Typ Max Unit
Power Supply Rejection
Power Supply Consumption AVDD, Reset
40
0.6
4.5
5.5
7.5
dB
A
mA
5.0
6.0
Power Supply Consumption AVDD, no load
Power Supply Consumption AVDD, output loaded at 30
Power Supply Consumption AVDD, o. @ 30 + GND-buf.
Power Supply Consumption DVDD, Reset
Power Supply Consumption DVDD
3.0
4.0
6.0
40.0 mA
40.0 mA
3.7 100.0
15.0
A
mA
2.3 DAC Interpolation Filter Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Passband (to -3dB corner)
Passband (Ripple Spec)
Passband Ripple
Transition Band
Stop Band
Stop Band Rejection
Group Delay
0
0
0.459Fs Hz
0.420Fs Hz
±0.056 dB
0.580Fs Hz
Hz
0.420Fs
0.580Fs
90
dB
s
15/Fs
Fs is conversion frequency
2.4 DAC Interpolation Filter Characteristics
Parameter
Symbol Min Typ Max Unit
-3 dB bandwidth
Passband Response at 20 kHz
300
-0.05
kHz
dB
2.5 Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Analog Positive Supply
Digital Positive Supply
AVDD
DVDD
-0.3
-0.3
3.6
3.6
V
V
Current at Any Digital Output
Voltage at Any Digital Input
Operating Temperature
Functional Operating Temperature
Storage Temperature
±50
mA
V
◦C
◦C
◦C
DGND-1.0 DVDD+1.0
-30
-40
-65
+85
+95
+150
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2. CHARACTERISTICS & SPECIFICATIONS
2.6 Recommended Operating Conditions
Parameter
Symbol
Min Typ Max Unit
Analog and Digital Ground
Positive Analog
Ambient Operating Temperature
AGND DGND
AVDD
0.0
2.51 3.0
-30
V
V
3.6
+85 ◦C
1 If AVDD is below 2.8 V, distortion performance may be compromised.
The following values are to be used when the clock doubler is active:
Parameter
Symbol Min
Typ
Max Unit
Positive Digital
Input Clock Frequency
Internal Clock Frequency1
DVDD
XTALI
CLKI
2.3
2.7
12.288
24.576
3.6
13
26
V
MHz
MHz
1 The maximum sample rate that may be decoded with correct speed is CLKI/512.
The following values are to be used when the clock doubler is inactive:
Parameter
Symbol Min
Typ
Max Unit
Positive Digital
Input Clock Frequency
Internal Clock Frequency1
DVDD
XTALI
CLKI
2.3
2.7
24.576
24.576
3.6
26
26
V
MHz
MHz
1 The maximum sample rate that may be decoded with correct speed is CLKI/512.
Note: With higher than typical voltages, VS1001k may operate with CLKI upto 30..32 MHz. However,
the chips are not qualified for this kind of usage. If necessary, VLSI Solution Oy can qualify chips for
higher clock rates for quantity orders.
2.7 Digital Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage at I = -2.0 mA
Low-Level Output Voltage at I = 2.0 mA
Input Leakage Current
0.7DVDD
V
V
V
V
A
0.3DVDD
0.7DVDD
0.3DVDD
1.0
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2. CHARACTERISTICS & SPECIFICATIONS
2.8 Switching Characteristics - Clocks
Parameter
Symbol Min
Typ
Max Unit
Master Clock Frequency 1 XTALI
Master Clock Frequency 2 XTALI
Master Clock Duty Cycle
12.288
24.576
50
MHz
MHz
%
40
60
Clock Output
XTALO
XTALI
MHz
1 Clock doubler active.
2 Clock doubler inactive.
2.9 Switching Characteristics - DREQ Signal
Parameter
Symbol Min Typ Max Unit
200 ns
Data Request Signal DREQ
2.10 Switching Characteristics - SPI Interface Output
Parameter
Symbol Min Typ
Max
0.25×CLKI MHz
100 ns
Unit
SPI Input Clock Frequency
Rise time for SO
2.11 Switching Characteristics - Boot Initialization
Parameter
Symbol Min Max
Unit
XTALI
50000 XTALI
RESET active time
RESET inactive to software ready
2
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3. PACKAGES AND PIN DESCRIPTIONS
3 Packages and Pin Descriptions
3.1 SOIC-28
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VS1001
SOIC − 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Figure 1: Pin Configuration, SOIC-28.
Pin Name
Pin
Pin Type
Function
DREQ
DCLK
SDATA
BSYNC
DVDD1
DGND1
XTALO
XTALI
DVDD2
DGND2
XCS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DO
DIO
DI
data request, input bus
serial input data bus clock
serial data input
byte synchronization signal
digital power supply
digital ground
DI
PWR
PWR
CLK
CLK
PWR
PWR
DI
DI
DI
DO3
DI
DO
crystal output
crystal input
digital power supply
digital ground
chip select input (active low)
clock for serial bus
serial input
SCLK
SI
SO
serial output
TEST0
TEST1
TEST2
AGND1
AVDD1
RIGHT
AGND2
RCAP
AVDD2
LEFT
AGND3
XRESET
DGND3
DVDD3
reserved for test, connect to DVDD
reserved for test, do not connect!
reserved for test, do not connect!
analog ground
analog power supply
right channel output
analog ground
capacitance for reference
analog power supply
left channel output
analog ground
active low asynchronous reset
digital ground
DO
PWR
PWR
AO
PWR
AIO
PWR
AO
PWR
DI
PWR
PWR
digital power supply
Pin types:
Type Description
Type Description
DI
DO
DIO
Digital input, CMOS Input Pad
Digital output, CMOS Input Pad
Digital input/output
AI
AO
AIO
Analog input
Analog output
Analog input/output
DO3 Digital output, CMOS Tri-stated Output Pad
PWR Power supply pin
SOIC-28 package dimensions can be found at http://www.vlsi.fi/vs1001/soic28.pdf .
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3. PACKAGES AND PIN DESCRIPTIONS
3.2 BGA-49
A1 BALL PAD CORNER
4
5
3
6
7
1
2
A
B
C
D
E
F
G
1.10 REF
0.80 TYP
4.80
7.00
TOP VIEW
Figure 2: Pin Configuration, BGA-49.
Pin Name
Ball
Pin Type
Function
BSYNC
DVDD1
DGND1
XTAL0
XTALI
DVDD2
DGND2
XCS
E3
F3
F4
G3
E4
F5
F6
G6
D6
E7
D5
C6
C7
B6
C5
B5
A6
B4
A5
C4
A4
B3
A3
B2
A2
B1
D2
D3
E2
E1
F2
DI
PWR
PWR
CLK
CLK
PWR
PWR
DI
DI
DI
DO3
DI
DO
byte synchronization signal
digital power supply
digital ground
crystal output
crystal input
digital power supply
digital ground
chip select input (active low)
clock for serial bus
serial input
serial output
reserved for test, connect to DVDD
reserved for test, do not connect!
reserved for test, do not connect!
analog ground
analog power supply
right channel output
analog ground
analog ground for ground buffer
ground buffer
analog power supply for ground buffer
capacitance for reference
analog power supply
left channel output
analog ground
active low asynchronous reset
digital ground
digital power supply
data request, input bus
serial input data bus clock
serial data input
SCLK
SI
SO
TEST0
TEST1
TEST2
AGND1
AVDD1
RIGHT
AGND34
GBGND
GBUF
GBVDD
RCAP
AVDD45
LEFT
DO
PWR
PWR
AO
PWR
PWR
AO
PWR
AIO
PWR
AO
PWR
DI
PWR
PWR
DO
DIO
DI
AGND56
XRESET
DGND3
DVDD3
DREQ
DCLK
SDATA
Not connected are: A1, A7, B7, C1, C2, C3, D1, D4, D7, E5, E6, F1, F7, G1, G2, G4, G5 and G7. For
“Pin Types”, see Chapter 3.1. BGA-49 package dimensions are at http://www.vlsi.fi/vs1001/bga49.pdf .
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3. PACKAGES AND PIN DESCRIPTIONS
3.3 LQFP-48
48
1
Figure 3: Pin Configuration, LQFP-48.
Pin Name
Pin
Pin Type
Function
nc
1,2
3
4
-
DI
PWR
-
XRESET
DGND0
nc
active low asynchronous reset
digital ground
5
DVDD0
nc
6
7
PWR
-
digital power supply
DREQ
DCLK
SDATA
nc
BSYNC
DVDD1
nc
DGND1
XTALO
XTALI
DVDD2
DGND2
DGND3
DGND4
XCS
8
9
DO
DI
DI
-
DI
PWR
-
PWR
AO
AI
PWR
PWR
PWR
PWR
DI
data request, input bus
serial input data bus clock
serial data input
10
11,12
13
14
15
16
17
18
19
20
21
22
23
24.. . 27
28
29
30
31
32
32
32
35,36
37
38
39
40
41
42
43
44
45
46
47
48
byte synchronization signal
digital power supply
digital ground
crystal output
crystal input
digital power supply
digital ground
digital ground
digital ground
chip select input (active low)
nc
SCLK
SI
SO
nc
-
DI
DI
DO3
-
clock for serial bus
serial input
serial output
TEST0
TEST1
TEST2
nc
AGND0
AVDD0
RIGHT
AGND1
AGND2
VCM
AVDD1
RCAP
AVDD2
LEFT
AGND3
nc
DI
reserved for test, connect to DVDD
reserved for test, do not connect!
reserved for test, do not connect!
DO
DO
-
PWR
PWR
AO
PWR
PWR
AO
PWR
AIO
PWR
AO
PWR
-
analog ground, low-noise reference
analog power supply
right channel output
analog ground
analog ground
feedback
analog power supply
capacitance for reference
analog power supply
left channel output
analog ground
For “Pin Types”, see Chapter 3.1. LQFP-48 package dimensions are at http://www.vlsi.fi/vs1001/lqfp48.pdf .
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4. CONNECTION DIAGRAM, SOIC-28
4 Connection Diagram, SOIC-28
In this connection diagram, a SOIC-28 -packaged VS1001k is used.
Figure 4: Typical Connection Diagram Using SOIC-28.
Ground buffer is not available for the SOIC-28 package; hence it is not used.
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5. CONNECTION DIAGRAM, BGA-49 AND LQFP-48
5 Connection Diagram, BGA-49 and LQFP-48
In this connection diagram, a BGA-49 or LQFP-48 packaged VS1001k is used. In this picture, ground
buffer is active.
Figure 5: Typical Connection Diagram Using BGA-49.
Ground buffer GBUF can be used for common voltage (1.37 V) for earphones. This will eliminate the
need for large isolation capacitors on line outputs, and thus the audio output pins from VS1001k may be
connected directly to the earphone connector. If GBUF is not used, GBGND and GBVDD should not be
connected.
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6. SPI BUSES
6 SPI Buses
6.1 General
The SPI Bus - that was originally used in some Motorola devices - has been used for both VS1001k’s
Serial Data Interface SDI (Chapters 6.3 and 7.3) and Serial Control Interface SCI (Chapters 6.4 and 7.4).
6.2 SPI Bus Pin Descriptions
SDI Pin SCI Pin Description
-
XCS
Active low chip select input. A high level forces the serial interface into
standby mode, ending the current operation. A high level also forces serial
output (SO) to high impedance state. There is no chip select for SDI, which
is always active.
DCLK
SCK
Serial clock input. The serial clock is also used internally as the master
clock for the register interface.
SCK can be gated or continuous. In either case, the first rising clock edge
after XCS has gone low marks the first bit to be written (clock 0 in the
following figures).
SDATA
-
SI
SO
Serial input. SI is sampled on the rising SCK edge, if XCS is low.
Serial output. In reads, data is shifted out on the falling SCK edge.
In writes SO is at a high impedance state.
6.3 Serial Protocol for Serial Data Interface (SDI)
The serial data interface can operate in either master or slave mode. In master mode, VS1001k generates
the DCLK signal, which can be selected to be either 512 or 1024 kHz. In slave mode, the DCLK signal
is generated by an external circuit.
The data (SDATA signal) can be clocked in at either the rising or falling edge of the DCLK. (Chapter 7.5).
The VS1001k chip assumes its input to be byte-sychronized. I.e. the internal operation of the decoder
does not search for byte synchronization of the frames from the data stream, but instead assumes the
data to be correctly byte-aligned. The bytes can be transmitted either MSB or LSB first, depending of
contents of SCI register MODE (Chapter 7.5).
BSYNC
SDATA
D7
D6
D5
D4
D3
D2
D1
D0
DCLK
Figure 6: BSYNC Signal.
To ensure correct byte-alignment of the input bitstream, the serial data interface has a BSYNC signal.
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6. SPI BUSES
The first DCLK sampling edge (rising or falling, depending on selected polarity), during which the
BSYNC is high, marks the first bit of a byte (LSB, if LSB-first order is used, MSB, if MSB-first order
is used). If BSYNC is not used, it must be tied to VCC externally and the master of the input serial
interface must always sustain the correct byte-alignment. Using BSYNC is strongly recommended. For
more details, look at the Application Notes for VS10XX.
The DREQ signal of the data interface is used in slave mode to signal if VS1001k’s FIFO is capable of
receiving more input data. If DREQ is high, VS1001k can take at least 32 bytes of data. When there is
less than 32 bytes of free space, DREQ is turned low, and the sender should stop transferring new data.
Because of the 32-byte safety area, the sender may send upto 32 bytes of data at a time without checking
the status of DREQ, making controlling VS1001k easier for low-speed microcontrollers.
Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ should
only be used to decide whether to send more bytes. It should not abort a transmission that has already
started.
6.4 Serial Protocol for Serial Command Interface (SCI)
6.4.1 General
The serial bus protocol for the Serial Command Interface SCI (Chapter 7.4) consists of an instruction
byte, address byte and one 16-bit data word. Each read or write operation can read or write a single
register. Data bits are read at the rising edge, so the user should not update data at the rising edge.
The operation is specified by an 8-bit instruction opcode. The supported instructions are read and write.
See table below.
Instruction
Name
Opcode
Operation
READ
0000 0011 Read data
WRITE 0000 0010 Write data
Note: After using the Serial Command Interface, it is not allowed to send SCI or SDI data for 5 mi-
croseconds.
6.4.2 SCI Read
VS1001k registers are read by the following sequence. First, XCS line is pulled low to select the device.
Then the READ opcode (0x3) is transmitted via the SI line followed by an 8-bit word address. After the
address has been read in, any further data on SI is ignored. The 16-bit data corresponding to the received
address will be shifted out onto the SO line.
XCS should be driven high after the data has been shifted out. In that case, the word address will be
incremented and data corresponding to the next address will be shifted out. After the last word has been
shifted out, XCS should be driven high to end the READ sequence.
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6. SPI BUSES
Word read is shown in Figure 7.
XCS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
30 31
SCK
0
0
0
0
0
0
1
1
7
6
5
4
3
2
1
0
don’t care
SI
instruction (READ)
high impedance
address
data out
15 14
1
0
X
SO
Figure 7: SCI Word Read
6.4.3 SCI Write
VS1001k registers are written by the following sequence. First, XCS line is pulled low to select the
device. Then the WRITE opcode (0x2) is transmitted via the SI line followed by an 8-bit word address.
After the word has been shifted in, XCS should be pulled high to end the WRITE sequence. XCS low to
high transition must occur after SCLK high to low transition corresponding to LSB of the last word.
Single word write is shown in Figure 8.
XCS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
29 30 31
SCK
0
0
0
0
0
0
1
0
7
6
5
4
3
2
1
0
15 14
2
1
0
don’t care
SI
instruction (WRITE)
address
data in
Figure 8: SCI Word Write
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6. SPI BUSES
6.5 SPI Timing Diagram
tWL tWH
tXCSH
tXCSS
XCS
tXCS
0
1
14
15
16
SCK
SI
tSU
tH
SO
tZ
tV
tDIS
Figure 9: SPI Timing Diagram.
Symbol Min Max Unit
tXCSS
tSU
tH
5
10
42
ns
ns
ns
tZ
42 ns
ns
ns
42 ns
ns
tWL
tWH
tV
tXCSH
tXCS
tDIS
100
100
10
2
XTALI cycles
XTALI cycles
1
Note: As tXCS must be at least 2 clock cycles, the maximum speed for the SPI bus is 1/4 of VS1001k’s
internal clock speed. For details, see Application Notes for VS10XX.
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7. FUNCTIONAL DESCRIPTION
7 Functional Description
7.1 Main Features
VS1001k is based on a proprietary digital signal processor, VS DSP. It contains all the code and data
memory needed for MPEG audio decoding, together with serial interfaces, a multirate stereo audio DAC
and analog output amplifiers and filters.
VS1001k can play all MPEG 1 and 2 layer 3 files, as well as so-called MPEG 2.5 layer 3 extension
files with all sample rates and bitrates. In addition, variable bitrate (VBR) is also supported. With
VBR, and depending on the song, near-cd quality can be achieved with approximately 100 kbits/s for
stereo music sampled at 44100 Hz, whereas old encoders required 128 kbits/s for the same task. As
both commercial and free (http://www.mp3dev.org/) high-quality VBR encoders are nowadays widely
available, MP3 format is getting better as it is maturing.
7.2 Data Flow of VS1001k
SM_BASS = 0
A1ADDR = 0
L
SDI
Bitstream
FIFO
MP1/2/3
decoding
Bass/treble
enhancer
User
application
Volume
control
Audio
FIFO
S.rate.conv.
and DAC
R
16384 bits
SM_BASS = 1
A1ADDR != 0
VOL
512 stereo
samples
Figure 10: Data Flow of VS1001k.
First, MP3 data is input through the SDI bus.
After decoding, data may be sent to the Bass/treble enhancer depending on SCI register MODE’s bit
SM BASS.
Then, if SCI register AIADDR is non-zero, application code is executed from the address pointed to by
AIADDR. For more details, see Chapters 7.5.10 and Application Notes for VS10XX.
After the optional user application, the signal is fed to the volume control unit, which also copies the
data to the Audio FIFO.
The Audio FIFO holds the data that is read by the Audio interrupt (Chapter 9.5.1) and fed to the sample
rate converter and DACs. The size of the audio FIFO is 512 stereo (2×16-bit) samples
The sample rate converter converts all different sample rates to CLKI/512 and feeds the data to the DAC,
which in order makes a stereo in-phase signal. This signal is then forwarded to the earphone amplifier.
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7. FUNCTIONAL DESCRIPTION
7.3 Serial Data Interface (SDI)
The serial data interface is meant for transferring compressed MPEG audio data.
Also several different tests may be activated through SDI as described in Chapter 8.
7.4 Serial Control Interface (SCI)
The serial control interface is compatible with the SPI bus specification. Data transfers are always 16-
bits. The VS1001k is controlled by writing and reading the registers of the interface.
The main controls of the control interface are:
• control of the operation mode
• uploading user programs
• access to header data
• status information
• access to decoded digital data
• feeding input data
7.5 SCI Registers
Name
Type addr Function
MODE
STATUS
RW
RW
-
RW
R
R
W
W
0
1
2
3
4
5
6
7
mode control
status of VS1001k
internal register, never use
clock freq + doubler
decode time in seconds
misc. audio data
RAM write program
base address for
INT FCTLH
CLOCKF
DECODE TIME
AUDATA
WRAM
WRAMADDR
RAM write
HDAT0
HDAT1
AIADDR
R
R
RW
8
9
read header data
read header data
10 start address of
application
VOL
RESERVED
AICTRL[x]
RW
-
11 volume control
12 reserved for VS1002 use, don’t touch
RW 13+x 2 application control
registers
x = [0 .. 1]
All registers are filled with zeros at hardware reset.
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7. FUNCTIONAL DESCRIPTION
7.5.1 MODE (RW)
MODE is used to control the operation of VS1001k.
Bit Name
Function
Value Description
0
1
2
SM DIFF
differential
0
1
0
1
0
1
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
normal in-phase audio
left channel inverted
normal playback
fast forward on
no reset
reset
Set to 0
power on
powerdown
Set to 0
SM FFWD
SM RESET
fast forward
soft reset
3
4
SM UNUSED1 set to 0
SM PDOWN
powerdown
5
6
7
SM UNUSED2 set to 0
SM UNUSED3 set to 0
SM BASS
Set to 0
off
on
rising
bass/treble enhancer
8
9
SM DACT
DCLK active
edge
falling
SM BYTEORD Byte order on serial input bus
MSB first
MSB last
slave
master
512 kHz
10 SM IBMODE
11 SM IBCLK
input bus mode
input bus clk when VS1001k is master
1024 kHz
When SM DIFF is set, the player inverts the left output. For a stereo input, this creates a virtual surround,
and for a mono input this effectively creates a differential left/right signal.
By setting SM FFWD the player starts to accept SCI data at a high speed, and just decodes the audio
headers silently without playing any data. This can be used to fast-forward data with safe landing.
Register DECODE TIME is updated during a fast-forward just as normal.
By setting SM RESET to 1, the player is reset.
SM UNUSED1 should always be set to 0.
Bit SM PDOWN overrides any other: it turns VS1001k into powerdown mode, where the only opera-
tional part is the control bus.
SM UNUSED2 and SM UNUSED3 should always be set to 0.
Bit SM BASS turns on the built-in Bass and Treble enhancer. The frequency response of the enhancer
when the sample rate is 44.1 kHz is shown in Figure 11. For other sample frequencies the response
frequence axis must be adjusted accordingly. Example: If the sample rate is 48 kHz, the 1 kHz frequency
in the figure is actually 1 kHz × 48 kHz / 44.1 kHz = 1.09 kHz. For details of how much extra processing
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7. FUNCTIONAL DESCRIPTION
power is needed when activating this feature, see Application Notes for VS10XX.
ampl/dB
+3
+2
+1
0
−1
−2
−3
f/Hz
10
20
50
100
200
500
1k
2k
5k
10k
20k
Figure 11: Built-In Bass/Treble Enhancer Frequency Response at 44.1 kHz.
SM DACT defines the active edge of data clock for SDI.
SM BYTEORD defines the data order inside a byte for SDI. Bytes are, however, still sent in the default
order.
SM IBMODE sets input bus to master mode. Master mode has not been tested, and its use is not recom-
mended.
SM IBCLK sets the bus clock speed when VS1001k is the master.
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7. FUNCTIONAL DESCRIPTION
7.5.2 STATUS (RW)
STATUS contains information on the current status of the VS1001k. Bits 1 and 0 are used to control
analog output volume: 0 = -0 dB, 1 = -6 dB, 3 = -12 dB. Bit 2 is analog powerdown bit. When set to 1,
analog is put to powerdown.
Note: writing to register VOL will automatically set the analog output volume, and muting if necessary.
Thus, the user needn’t worry about this register.
7.5.3 INT FCNTLH (-)
INT FCTLH is not a user-accessible register.
7.5.4 CLOCKF (RW)
CLOCKF is used to tell if the input clock XTALI is running at something else than 24.576 MHz. XTALI
is set in 2 kHz steps. Thus, the formula for calculating the correct value for this register is
(XTALI is in Hz). Values may be between 0..32767, although hardware limits the highest allowed speed.
Also, with lower-than 24.576 MHz speeds all sample rates and bit-stream widths are no longer available.
Setting the MSB of CLOCKF to 1 activates internal clock-doubling. A clock of upto 15 MHz may be
doubled depending on the voltage provided to the chip.
Note: CLOCKF must be set before beginning decoding MP3 data; otherwise the sample rate will not be
set correctly.
Example 1: For a 26 MHz clock the value would be
.
Example 2: For a 13 MHz external clock and using internal clock-doubling for a 26 MHz internal
frequency, the value would be
.
Example 3: For a 24.576 MHz clock the value would be either
, or just the
default value . For this clock frequency, CLOCKF doesn’t need to be set at all.
7.5.5 DECODE TIME (R)
When decoding correct data, current decoded time is shown in this register in full seconds.
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7. FUNCTIONAL DESCRIPTION
7.5.6 AUDATA (R)
When decoding correct data, the current bitrate in kbits/s can be found in bits 8..0 of AUDATA. For a
variable bitrate bitstream, the current bitstream width is displayed. Bits 12..9 contains an index to the
sample rate. The indices are shown in the table below. Bits 14..13 are not in use and always set to 0. Bit
15 is 0 for mono data and 1 for stereo.
Bits 12..9 Sample Rate/Hz
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
Unknown
44100
48000
32000
22050
24000
16000
11025
12000
8000
7.5.7 WRAM (W)
WRAM is used to upload application programs to program RAM. The start address must be initialized
by writing to the WRAMADDR register prior to the first call of WRAM. value will be used. As 16 bits of
data can be transferred with one WRAM write, and the program word is 32 bits, two consecutive writes
are needed for each program word. The byte order is big-endian (i.e. MSBs first). After each full-word
write, the internal pointer is autoincremented.
7.5.8 WRAMADDR (W)
WRAMADDR is used to set the program address for following WRAM writes. User program space is
between addresses 0x4000 .. 0x43ff (with addresses 0x4000 .. 0x401f being reserved by the system),
but for writes through the WRAM mechanism, they are visible at addresses 0x4000 higher. Thus, if the
programmer wish to write his application to address 0x4167, he should write 0x4167 + 0x4000 = 0x8167
to WRAMADDR.
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7. FUNCTIONAL DESCRIPTION
7.5.9 HDAT0 and HDAT1 (R)
Bit
Function
Value Explanation
2047 stream valid
HDAT1[15:5]
syncword
ID
HDAT1[4:3]
HDAT1[2:1]
HDAT1[0]
3
2
1
0
3
2
1
0
1
0
ISO 11172-3 1.0
MPG 2.0 (1/2-rate)
MPG 2.5 (1/4-rate)
MPG 2.5 (1/4-rate)
I
II
III
reserved
No CRC
CRC protected
ISO 11172-3
reserved
32/16/8 kHz
48/24/12 kHz
44/22/11 kHz
additional slot
normal frame
not defined
mono
layer
protect bit
HDAT0[15:12] bitrate
HDAT0[11:10] sample rate
3
2
1
0
1
0
HDAT0[9]
pad bit
HDAT0[8]
HDAT0[7:6]
private bit
mode
3
2
1
0
dual channel
joint stereo
stereo
HDAT0[5:4]
HDAT0[3]
extension
copyright
ISO 11172-3
copyrighted
free
original
copy
CCITT J.17
reserved
50/15 microsec
none
1
0
1
0
3
2
1
0
HDAT0[2]
original
HDAT0[1:0]
emphasis
When read, HDAT0 and HDAT1 contain header information that is extracted from MPEG stream being
currently being decoded. Right after resetting VS1001k, 0 is automatically written to both registers,
indicating no data has been found yet.
The “sample rate” field in HDAT0 is interpreted as follows: if the “ID” field in HDAT1 is ’1’, the highest
sample rate is used. If “ID” is ’0’, half sample rate is used. For ’2’ and ’3’, the lowest sample rate is
used.
Note: The sample rate, stereo/mono and bitrate information can more easily be read from register AU-
DATA.
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7. FUNCTIONAL DESCRIPTION
7.5.10 AIADDR (RW)
AIADDR indicates the start address of the application code written earlier through WRAMADDR and
WRAM registers. If no application code is used, this register should not be initialized, or it should be
initialized to zero. For more details, see Application Notes for VS10XX.
7.5.11 VOL (RW)
VOL is a volume control for the player hardware. For each channel, a value in the range of 0 .. 255
may be defined to set its attenuation from the maximum volume level (in 0.5 dB steps). The left channel
value is then multiplied by 256 and the values are added. Thus, maximum volume is 0 and total silence if
65535. Example: for a volume of -2.0 dB for the left channel and -3.5 dB for the right channel: (4*256)
+ 7 = 1031. Note, that at startup volume is set to full volume. Resetting the software does not reset the
volume setting.
Note: Setting the volume to total silence (255 for both left and right channels), will turn analog power
off. This will save power, but also cause a slight snap in the earphones. If you want to turn the volume
off but don’t want this snap, turn the volume only to 254 for both channels (0xFEFE).
7.5.12 RESERVED (RW)
This register has been reserved for future use.
7.5.13 AICTRL[x] (RW)
AICTRL[x] -registers ( x=[0 .. 1] ) can be used to access the user’s application program.
7.6 Stereo Audio DAC
The decoded digital data is transformed into analog format by an 18-bit oversampling multi-bit sigma-
delta DA-converter. The oversampled output is low-pass filtered by an on-chip analog filter. The output
rate of the DA-converter is always 1/4 of the clock rate, or 128 times the highest usable sample rate. For
instance for a 24.576 MHz clock, the DA-converter operates at 128x48 kHz, which is 6.144 MHz. If the
input sample rate is other than 48 kHz, it is internally converted to 48 kHz by the DAC. This removes the
need for complex PLL-based clocking schemes and still allows the use of several sample rates with one
fixed master clock frequency.
The outputs can be separately muted by the user. If the output of the decoder is invalid or input data is
not received fast enough, analog outputs are automatically muted. The analog outputs have buffers that
are capable of driving 30 loads with a maximum of 50nF capacitance.
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8. OPERATION
8 Operation
8.1 Clocking
The VS1001k chip operates typically on a single 24.576 MHz fundamental frequency master clock. This
clock can be generated by external circuitry (connected to pin XTALI) or by the internal clock chrystal
interface (pins XTALI and XTALO). This clock is sufficient to support a high quality audio output for
almost all the standard sample rates and bit-rates (see Application Notes for VS10XX).
Note: Oscillators above 24.576 MHz are usually so-called
harmonic clocks, which have a fundamen-
tal frequency of 1/3 of the nominal clock frequency. With such an oscillator, VS1001 would be running at
the base frequency, if working at all. Thus, for instance, if you run VS1001 with a 32 MHz
clock, you usually end up running the chip at 32 MHz / 3 = 10.67 MHz.
harmonic
8.2 Powerdown
In powerdown mode the chip only monitors the control bus. The analog output drivers are turned off and
the processor remains in hold-state.
8.3 Hardware Reset
When the XRESET -signal is driven low, VS1001k is reset and all the control registers and internal
states are set to the initial values. XRESET-signal is asynchronous to any external clock. The reset mode
doubles as a full-powerdown mode, where both digital and analog parts of VS1001k are in minimum
power consumption stage, and where clocks are stopped. Also XTALO and XTALI are grounded.
After a hardware reset (or at power-up), set the basic software registers such as VOL for volume (and
CLOCKF if the input clock is anything else than 24.576 MHz) before starting decoding.
8.4 Software Reset
Between any two MP3 files, the decoder software has to be reset. This is done by activating bit 2 in SCI’s
MODE register (Chapter 7.5.1). Then wait for at least 2 s, then look at DREQ. DREQ will stay down
for at least 6000 clock cycles, which means an approximate 250 s delay if VS1001k is run at 24.576
MHz. When DREQ goes up, write at least one zero to SDI. After this, you may continue playback as
usual.
If you want to make sure VS1001k doesn’t cut the ending of low-bitrate data streams, it is recommended
to feed 2048 zeros to the SDI bus before activating the reset bit (DREQ must be respected just as with
normal SDI data). This will make sure all frames have been decoded before resetting the chip.
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8. OPERATION
8.5 Play/Decode
This is the normal operation mode of VS1001k. The SDI data is decoded. Decoded samples are converted
to analog domain by the internal DAC, If there are errors in the decoding process, the error flags of SCI’s
HDAT0 and HDAT1 are set accordingly. In case there are serious errors in the input data, decoding is
still continued, but the analog outputs are muted.
When there is no valid input for decoding, VS1001k goes into idle mode (lower power consumption than
during decoding) and actively monitors the serial data input for valid data. The data input does not need
to be clocked (DCLK) when no data is sent.
The software needs to be reset between MPEG audio stream files. See for the Chapter “Testing” to see
how it is done.
8.6 Sanity Checks
Although VS1001k checks extensively for bad MP3 streams, it may happen that it encounters a bitstream
that makes the firmware’s recovery code fail. This may particularly happen during fast forward and fast
backwards operations, where the data where the microcontroller lands the MP3 decoder may not be a
valid header.
The microcontroller should keep a look at the data speeds VS1001k requires. If data input either stops
completely (DREQ always inactive) for a whole second, or if VS1001k requires more than 60 KiB data
in any single second, it is the responsibility of the microcontroller to either reset the software. If that
doesn’t help, a hardware reset should be issued.
8.7 PCM Mode
VS1001k can be used as a Digital-to-Analog converter (DAC) by feeding PCM data. A convenient way
to use VS1001k as a DAC is to load SDI PCM Extension for VS1001k software from VLSI Solution’s
home page at http://www.vlsi.fi/vs1001/software/.
The SDI PCM Extension makes it possible for the user to use SDI to feed 8-bit or 16-bit PCM samples
in mono or stereo at any sample rate upto 48 kHz (with nominal 24.576 MHz operating frequency).
8.8 Testing
There are several test modes in VS1001k, which allow the user to perform memory tests, SCI bus tests,
and several different sine wave tests ranging from 250 Hz to 1500 Hz.
All tests are started in a similar way: VS1001 is hardware reset, and then a test command is sent to the
SDI bus. Each test is started by sending a 4-byte special command sequence, followed by 4 zeros. The
sequences are described below.
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8. OPERATION
8.8.1 Memory Test
Memory test mode is initialized with the 8-byte sequence 0x4D 0xEA 0x6D 0x54 0 0 0 0. After this
command (and its required 4 zeros), wait for 500000 clock cycles. The result can be read from the SCI
register HDAT0, and ’one’ bits are interpreted as follows:
Bit(s) Meaning
0
1
2
3
4
5
6
7
Good X ROM
Good Y ROM (high)
Good Y ROM (low)
Good Y RAM
Good X RAM
Good Instruction RAM (high)
Good Instruction RAM (low)
Unused
All tests are non-destructive and interrupts are disabled during testing. Thus, no user software or data is
harmed by the tests.
Instruction ROM cannot be tested with software.
8.8.2 SCI Test
Sci test is initialized with the 8-byte sequence 0x53 0x70 0xEE 0 0 0 0, where
number to test. The content of the given register is read and copied to HDAT0. If the register to be tested
is HDAT0, the result is copied to HDAT1.
−
is the register
Example: if is 48, contents of SCI register 0 (MODE) is copied to HDAT0.
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8. OPERATION
8.8.3 Sine Test
Sine test is initialized with the 8-byte sequence: 0x53 0xEF 0x6E 0 0 0 0, where (48..119) defines
the sine test to use. If we define
may be used:
−
and
−
, the following tables
FsIdx
Fs
FSin
Length of Sin
0
1
2
3
4
5
6
7
8
44100 Hz
48000 Hz
32000 Hz
22050 Hz
24000 Hz
16000 Hz
11025 Hz
12000 Hz
8000 Hz
0
1
2
3
4
5
6
7
32.000 samples
16.000 samples
10.667 samples
8.000 samples
6.400 samples
5.333 samples
4.571 samples
4.000 samples
Example: Sine test is called with a test value of 62. 62-48 = 14, FsIdx = 5 and FSin = 1. From the tables
we get the sample rate 16000 Hz, and the sine wave length, which is 16 samples. Thus, we’ll get a 1 kHz
voice.
To exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0.
Note: The sine test signals go through the digital volume control, so it is possible to test channels
separately.
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9. WRITING SOFTWARE
9 Writing Software
9.1 When to Write Software
User software is required when a user wishes to add some own functionality like DSP effects or tone
controls to VS1001k. Some tone controls are available from VLSI Solution, but if a user wishes to go
further than that or use VS1001k in some unexpected way, this is how to do it.
However, most of the users of VS1001k don’t need to worry about writing their own code, or this chapter.
9.2 The Processor Core
VS DSP is a 16/32-bit DSP processor core that can very well also be used as an all-purpose processor.
The VLSI Solution’s free VSKIT Software Package contains all the tools and documentation needed to
write, simulate and debug Assembly Language or Extended ANSI C programs for the VS DSP processor
core.
The VSKIT Software Package is available on request from VLSI Solution.
9.3 User’s Memory Map
User’s Memory Map is shown in Figure 12.
9.4 Hardware Registers
All hardware registers are located in X memory.
9.4.1 SCI Registers, 0x4000
All SCI registers described in Chapter 7.5 can be found here between 0x4000..0x40FF.
9.4.2 Serial Registers, 0x4100
SER DATA (0x4100) contains the last data value read from the data bus. The LSB of SER DREQ
(0x4101) defines the status of the DREQ signal.
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9. WRITING SOFTWARE
Instruction (32−bit)
X (16−bit)
Y (16−bit)
Stack
Stack
0000
0000
0097
0097
User
Space
0780
07FF
0780
07FF
User
Space
1380
13FF
1380
13FF
System Vectors
4000
4000
4020
4020
User
Instruction
Space
Hardware
Registers
43FF
43FF
8000
8020
8000
Instruction
Shadow
Memory
Instruction 8020
Shadow
Memory
MSBs
LSBs
83FF
83FF
Figure 12: User’s Memory Map.
9.4.3 DAC Registers, 0x4200
DAC data should be written at each audio interrupt to DAC LEFT (0x4200) and DAC RIGHT (0x4201)
as signed values. INT FCTLL (0x4202) is not a user-serviceable register.
9.4.4 Interrupt Registers, 0x4300
INT ENABLE (0x4300) controls the interrupts. Bit 0 switches the DAC interrupt on (1) and off (0), bit 1
controls the SCI interrupt, and bit 2 controls the DATA interrupt. It may take upto 6 clock cycles before
changing this register has any effect.
By writing any value to INT GLOB DIS (0x4301) adds one to the interrupt counter and effectively
disables all interrupts. It may take upto 6 clock cycles before writing this register has any effect.
Writing any value to INT GLOB ENA (0x4302) subtracts one from the interrupt counter. If the interrupt
counter becomes zero, interrupts selected with INT ENABLE are restored. An interrupt routine should
always write to this register as the last thing it does, because interrupts automatically add one to the
interrupt counter, but subtracting it back to its initial value is on the responsibility of the user. It may take
upto 6 clock cycles before writing this register has any effect.
By reading INT COUNTER (0x4303) the user may check if the interrupt counter is correct or not. If the
register is not 0, interrupts are disabled. This register may not be written to.
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9. WRITING SOFTWARE
9.5 System Vector Tags
The System Vector Tags are tags that may be replaced by the user to take control over several decoder
functions.
9.5.1 AudioInt, 0x4000..0x4001
Normally contains the following VS DSP assembly code:
j dac_int
stx mr1,(i6)+1 ; sty i7,(i6)
The user may, at will, replace the first instruction with either a or
command to gain control over
the audio interrupt. It is not recommended to change the instruction at 0x4001.
9.5.2 SpiInt, 0x4002..0x4003
Normally contains the following VS DSP assembly code:
j spi_int
stx mr1,(i6)+1 ; sty i7,(i6)
The user may, at will, replace the first address with either a j or jmpi command to gain control over the
SCI interrupt. It is not recommended to change the instruction at 0x4003.
9.5.3 DataInt, 0x4004..0x4005
Normally contains the following VS DSP assembly code:
j data_int
stx mr1,(i6)+1 ; sty i7,(i6)
The user may, at will, replace the first address with either a j or jmpi command to gain control over the
MP3 data interrupt. It is not recommended to change the instruction at 0x4005.
9.5.4 UserCodec, 0x4008..0x4009
Normally contains the following VS DSP assembly code:
jr
nop
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9. WRITING SOFTWARE
If the user wants to take control away from the standard decoder, the first instruction should be replaced
with an appropriate jump command to user’s own code.
Unless the user is feeding MP3 data at the same time, the system activates the user program in less than
1 ms. After this, the user should steal interrupt vectors from the system, and then insert user programs.
9.6 System Vector Functions
The System Vector Functions are pointers to some functions that the user may call to help implementing
his own applications.
9.6.1 WriteIRam(), 0x4010
VS DSP C prototype:
void WriteIRam(register i0 u int16 *addr, register a1 u int16 msW, register a0 u int16 lsW);
This is the only supported way to write to the User Instruction RAM. This is because Instruction RAM
cannot be written when program control is in RAM. Thus, the actual implementation of this function is
in ROM, and here is simply a tag to that routine.
Note: Instruction RAM is shadowed 0x4000 addresses higher in the X and Y RAMs. Thus, if you want
to write to instruction address 0x4020,
must be 0x4020 + 0x4000 = 0x8020.
9.6.2 ReadIRam(), 0x4011
VS DSP C prototype:
u int32 ReadIRam(register i0 u int16 *addr);
This is the only supported way to read from the User Instruction RAM. This is because Instruction RAM
cannot be read when program control is in RAM. Thus, the actual implementation of this function is in
ROM, and here is simply a tag to that routine.
A1 contains the MSBs and a0 the LSBs of the result.
Note: Instruction RAM is shadowed 0x4000 addresses higher in the X and Y RAMs. Thus, if you want
to read from instruction address 0x4020,
must be 0x4020 + 0x4000 = 0x8020.
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9. WRITING SOFTWARE
9.6.3 DataWords(), 0x4012
VS DSP C prototype:
u int16 DataWords(void);
If the user has taken over the normal operation of the system by switching the pointer in UserCodec
to point to his own code, he may read data from the Data Interface through this and the following two
functions. This function returns the number of data words (each containing two bytes of data) that can be
read. If there is not enough data available, data acquisition functions GetDataByte() and GetDataWords()
may NOT be called!
9.6.4 GetDataByte(), 0x4013
VS DSP C prototype:
u int16 GetDataByte(void);
Reads and returns one data byte from the Data Interface.
Before calling this function, always check first that there are at least 1 word waiting with function Data-
Words().
9.6.5 GetDataWords(), 0x4014
VS DSP C prototype:
void GetDataWords(register i0 y u int16 *d, register a0 u int16 n);
Read data byte pairs and copy them in big-endian format (first byte to MSBs) to .
Before calling this function, always check first that there are at least 1+ words waiting with function
DataWords().
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10. VS1001 VERSION CHANGES
10 VS1001 Version Changes
This chapter describes changes between different generations of VS1001.
Note: VS1001k is the final, production version of VS1001.
10.1 Changes Between VS1001h and Production Version VS1001k, 2001-08
• When the chip is reset with pin XRESET, XTALO and XTALI are driven to ground.
• Running with normal clock earlier required slightly different clock generation than for clock-
doubled (see Chapters 4 and 5). This is no longer the case.
• Lots of new SCI register MODE bits: SM DIFF, SM FFWD, SM BASS. For details, see Chap-
ter 7.5.1.
• Default is now to only decode MP3.
• 20..60 mV DAC offset corrected.
• A firmware bug made it impossible to decode 320 kbits/s MP3 data. This has been corrected.
• A hardware bug made it practically impossible to load code to RAM. This has been corrected.
10.2 Changes Between VS1001g and VS1001h, 2001-05
• Analog voltage requirements have been lowered. Now full gain can be achieved with a 2.7 V
analog input voltage, whereas 3.4 V was needed before.
10.3 Changes Between VS1001d to VS1001g, 2001-03
• Clock is now adjustable, in VS1001d only 24.576 MHz could be used.
• Clock doubler added.
• VS1001d played 48 kHz instead of 12 or 24 kHz, this is corrected.
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11. DOCUMENT VERSION CHANGES
11 Document Version Changes
This chapter describes the most important changes to this document.
11.1 Changes Between Version 4.10 and 4.11 for VS1001k, 2003-09
• Minor modifications to front page.
• Moved all Application Notes to a separate document, VS10XX Application Notes.
11.2 Changes Between Version 4.08 and 4.10 for VS1001k, 2003-07
• Added LQFP-48 packaging, Chapter 3.3.
• Removed package figure for BGA-49 and provided an URL instead.
11.3 Changes Between Version 4.07 and 4.08 for VS1001k, 2003-03
• Removed MP1 and MP2 functionality due to firmware problems.
• Removed Chapter Errata.
11.4 Changes Between Version 4.06 and 4.07 for VS1001k, 2003-03
• Removed DAC mode. A more efficient and convenient way for PCM playback files is presented
in Chapter 8.7.
11.5 Changes Between Version 4.05 and 4.06 for VS1001k, 2002-09
• Added discussions of fundamental frequency and
harmonic clocks to Chapter 8.1.
11.6 Changes Between Version 4.03 and 4.05 for VS1001k, 2002-08
• Clarified Chapter 8.8, Testing.
• Added Application Note: Quick Startup / Seeing If Analog Works.
• Added comments on how DREQ works with DAC mode to Chapter DAC Mode.
• Replaced A1CTRL with AICTRL and A1ADDR with AIADDR throughout the datasheet.
• Added list of not connected pins, and replaced incorrect “Pin Type” description for GBUF from
PWR to AO in Chapter 3.2, Packages and Pin Descriptions / BGA-49.
• HDAT1[0] polarity was wrong in Chapter 7.5.9, corrected.
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12. CONTACT INFORMATION
12 Contact Information
VLSI Solution Oy
Hermiankatu 6-8 C
FIN-33720 Tampere
FINLAND
Fax: +358-3-316 5220
Phone: +358-3-316 5230
Email: sales@vlsi.fi
URL: http://www.vlsi.fi/
Note: If you have questions, first see http://www.vlsi.fi/vs1001/faq/ .
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