W5360120A [ETC]
;
| 型号： | W5360120A |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总12页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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GENERAL DESCRIPTION
The W536XXXA, a member of ViewTalkTM family, is a high-performance 4-bit micro-controller (uC) with
built-in speech unit, melody unit and 64seg * 16 com LCD driver unit which includes internal regulator
,pump circuit and dedicated two pages LCD RAM. The 4-bit uC core contains dual clock source, 4-bit
ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and
8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with
maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM) , is capable of expanding to
512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be
implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone
output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation.
It is ideal for games, educational toys, remote controllers, watches, clocks and other application
products which incorporate both LCD display and speech.
Body
Voice
W536030A
30 sec
W536060A
60 sec
W536090A
90 sec
W536120A
120 sec
I/O pad
4I/O,8I
8I/O, 8I
8I/O, 8I , 8O
8I/O, 8I, 8O
(RA/RC/RD)
(RA/RB/RC/RD) (RA/RB/RC/RD/RE/RF) (RA/RB/RC/RD/RE/RF
)
WDT
disable/Enable
(Mask Option)
Sub-clock
RC/XTAL mode
(Mask Option)
RD port shared as
serial bus
(Mask Option)
Tri-state serial bus
(Mask Option) ( 3)
Cascaded Voice
ROM through
serial bus (2)
Y
Y
Y
Y
Y
Y
Y
Y
Y(1)
Y
Y(1)
Y
N
N
N
N (2)
N
Y(1)
Y(1)
Y
(1) Share 3 pads of RD port (RD1/RDP, RD2/SPDATA and RD3/WRP)
(2) Dedicate serial bus 3 pads (RDP, SPDATA and WRP) to interface with W55XXX. Cascaded
Voice ROM can help to expand voice up to 512 sec by W55XXX chip.
(3) Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this
mask option is disabled to get minimum power consumption in general.
FEATURESꢀ
•
•
•
Operating voltage: 2.4 volt ~ 5.5 volt
Watch dog disabled/enabled by mask option
Dual clock operating system
− Main clock with RC/Crystal (400 KHz to 4 MHz)
− Sub-clock with 32.768 KHz RC/Crystal by mask option
Publication Release Date: April 2000
Revision A6
- 1 -
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•
•
Memory
− Program ROM (P-ROM): 32K × 20 (ROM Bank0, 1, 2)
− Data RAM (W-RAM): 1.4K × 4 bit
(RAM Bank 0 is 896 nibbles from 0:000 ~0:37F and 0:380~0:3FF are mapped to special register.
RAM Bank F is 512 nibbles from F:200 ~F:3FF either data RAM or dedicated to script kernel )
− LCD RAM (L-RAM): 256× 4 bit × 2 pages (RAM Bank1, 2 from 200~2FF)
Maximum 24 input/output pads
− Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external memory
W55XXX interface @W536030A/060A)
− Ports for output only: 8 pads (RE & RF port; W536090A/120A available only)
− Ports for Input/output: 8 pads (RA and RB port; RB port is available for W536060A/090A/120A
only)
•
•
Power-down mode
− Hold mode (except for 32kHz oscillator)
− Stop mode (including 32kHz oscillator and release by RD or RC port)
Eight types of interrupts
− Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody)
− Three external interrupts (Port RC, RD, RA)
•
•
One built-in 14-bit clock frequency divider circuit
Two built-in 8-bit programmable countdown timers
− Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected
− Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0
Built-in 18/14-bit watchdog timer for system reset.
Powerful instruction sets
•
•
•
•
8-level subroutine (including interrupt) nesting
LCD driver unit capability
− VLCD higher than (VDD-0.5V)
− Built-in voltage regulator to V2 pad
− 64 seg × 16 com
− 1/16 or 1/8 duty, 1/5 or 1/4 bias, internal pump circuit option by special register
− COM 8~ 15 and SEG40~63 can be shared as general input/output by special register
− Either uC ROM or voice ROM used as LCD picture
Speech function
− Provided 1M / 2M/ 3M/ 4M bits Voice ROM for W536030A/060A/090A/120A based on 5 bits
MDPCM algorithm
− Voice ROM (V-ROM) available for uC data or LCD picture data.
− Maximum 8*256 Label/Interrupt vector (voice section number) available
− Provide two types of speech busy flag to either each GO or each trigger
− Maximum up to 16M bits speech address capability interface with external memory W55XXX
through serial bus.
•
•
Melody function
− Provide 1K notes (22bits/note) dedicated melody ROM
− Provide two types of melody busy flag to uC either each note or each song
− Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7
− Tremolo, triple frequency and 3 kinds of percussion available
− Maximum 31 songs available
•
•
•
•
Can mix speech with melody
Multi-engine controller
Direct driving speaker/buzzer or DAC output
Chip On Board available
Publication Release Date:April 2000
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Revision A6
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BLOCK DIAGRAM
DH1,DH2
SEG0~63
COM0~15
V3,V4,V5,V6
V2
VDD
VSS
LCD DRIVER
RAM
VLCD PUMP &
REGULATOR
1.4*4Bit
PORT RA
RA0~3
RB0~3
TONE
ACC
ROM
PORT RB
PORT RC
32K*20Bit
ALU
RC0~3
RD0~3
PORT RD
PORT RE
PORT RF
PC
RE0~3
RF0~3
Special Register
HEF PEF
IEF
EVF
HCF
SPC MLD
FLAG0
STACK
WRP
RDP
SPDATA
FLAG1
LPX0
LPX4
PM0 MR0
LPX1 LPX2
LPX5 LPY0
PSR0
LPX3
LPY1
Parallel
to Serial
(8 Levels)
SPC_busy
SPC_play
LPXY
Speech
MDPCM
core
ROSC
Shared_ROM Data
VSSP
Interrupt ,Hold & Stop
Control
Timer 1
PWM1/DAC
PWM2
Timer 0
Voice ROM
(1M /2M/3M/4M bits)
PWM/DAC
Mix
Block
MLD_busy
MLD_play
VDDP
Dual
Tone
melody
(1K notes)
Watch Dog
Divide
Timing
TEST
RES
Generator
X32I X32O
XIN XOUT
ꢀ
Publication Release Date:April 2000
Revision A6
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PAD DESCRIPTION
SYMBOL
I/O
FUNCTION
XIN/RXIN
I
Input pad for main clock oscillator. It can be connected to crystal when crystal
mode is selected (SCR0.2=1), otherwise connect a resistor to VDD to generate
main system clock while RC mode is selected (SCR0.2=0 and default). Oscillator
can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External
capacitor connects to start oscillation while crystal mode
XOUT
O
I
Output pad for oscillator which is connected to another crystal pad when in crystal
mode. External capacitor connects to start oscillation when in crystal mode.
X32I/RSUB1
32.768 KHz crystal input pad or external resistor node 1 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
X32O/RSUB2
O
32.768 KHz crystal output pad or external resistor node 2 by mask option.
External 15~20pF capacitor connects to get more accurate clock when in crystal
mode.
RA0 ~ RA3/TONE I/O
General Input/Output port specified by PM1 register. If output mode is selected,
PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special
register is set to logic 1. An interrupt source.
RB0 ~ RB3
RC0 ~ RC3
I/O
I
General Input/Output port specified by PM2 register. If output mode is selected,
PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option.
Initial state is input mode (W536060A/090A/120A only.)
4-bit sch
mitter input with internal pull high option specified by PM3 register bit 2. Each pad
has an independent interrupt capability specified by PEFL special register.
Interrupt and STOP mode wake up source. RC0 is also the external event
counter source of Timer1.
RD0
I
4-bit schmitter input port with internal pull high option specified by PM3 register
bit 3. Each pad has an independent interrupt capability specified by PEFH
special register. Interrupt and STOP mode wake up source. RD1~3 will be
shared as the external memory W55XXX interface pads while RD port shared as
serial bus mask option is enabled @W536030A/060A.
RD1/RDP
RD2/SPDATA
RD3/WRP
(4)
For W536030A/060A only, "Tri-state serial bus" mask option can use to float
WRP/RDP/SPDATD while "RD port shared as serial bus" mask option is
enabled.
RE0~RE3
RF0~RF3
O
O
I
Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving
capability option. (W536090A/120A only)
Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving
capability option. (W536090A/120A only)
System reset pad, active low with internal pull-high resistor.
RES
Publication Release Date:April 2000
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Revision A6
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TEST
I
Test pad. Active high with internal pull low resistor.
ROSC
I
Connect resistor to VDD pad to generate speech or melody playing clock source.
PWM1/DAC
O
While speech or melody is active , PWM1/DAC is speaker direct driving output
or DAC output controlled by voice output file.
PWM2
O
While speech or melody is active, PWM2 is another speaker direct driving output.
External serial memory address write clock for voice extension (W536120A only).
External serial memory address read clock for voice extension. (W536120A only).
External serial memory data in/out for voice extension (W536120A only).
Dedicated LCD segment output pads.
WRP (5)
O
RDP (5)
O
SPDATA (5)
SEG0−SEG39
I/O
O
SEG40/PORTN.0 O/O
LCD segment output pads, and can be shared as general output by register
LCDM3 bit 1. Default function is segment pad.
SEG43/PORTN.3
SEG44/PORTM.0 O/I
LCD segment output pads, and can be shared as general input by register
LCDM3 bit 0. Default function is segment pad and PM5.1=0 to inhibit LCD
waveform abnormal.
SEG47/PORTM.3
SEG48/PORTL.0
O/O
LCD segment output pads, and can be shared as general output by register
LCDM2 bit 0. Default function is segment pad.
SEG51/PORTL.3
SEG52/PORTK.0 O/I
SEG55/PORTK.3
LCD segment output pads, and can be shared as general input by register
LCDM2 bit 1. Default function is segment pad and PM5.0=0 to inhibit LCD
waveform abnormal.
SEG56/PORTJ.0
SEG59/PORTJ.3
SEG60/PORTI.0
SEG63/PORTI.3
O/IO LCD segment output pads, and can be shared as general input/output by register
LCDM2 bit 2. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.3=0 to inhibit LCD
waveform abnormal.
O/IO LCD segment output pads, and can be shared as general input/output by register
LCDM2 bit 3. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.2=0 to inhibit LCD
waveform abnormal.
Publication Release Date:April 2000
- 5 -
Revision A6
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O
LCD common signal output pads either 1/16 duty or 1/8 duty. The LCD frame rate
is controlled by LCDM1 register, and default value LCDM1=0111b with 64Hz
frame rate.
COM0−COM7
COM8 / PORTP.0 O/O
LCD common signal output pads, or shared as general output by register
LCDM3.2 when in 1/8 duty mode. Default function is common function.
COM11/PORTP.3
COM12/PORTO.0 O/I
LCD common signal output pads, or shared as general input by register LCDM3.2
when in 1/8 duty mode. Default function is common function and PM5.2=0 to
inhibit LCD waveform abnormal.
COM15/PORTO.3
DH1, DH2 (6)
V3 ~ V6 (6)
V2 (6)
O
Connection terminal for voltage double capacitor with 0.1uF. The DH2 connects
to capacitor positive node and DH1 negative node if polar capacitor is used.
O
LCD COM/SEG output driving voltage. Need an external 0.1uF capacitor to every
pad terminal.
I/O
Voltage regulator output pad. An external capacitor is a must. Output level can
be controlled from 0~Fh by LCDM4 register. If internal pump is enabled
(LCDM3.3=0 and default value), LCD operating voltage (VLCD) will be 4*V2 or
5*V2 depending on 1/4 bias or 1/5 bias. A limitation should be noted that VLCD
must be higher than (VDD-0.5v) to avoid chip leakage current. While external
reference voltage is selected (LCDM3.3=1), V2 pad input voltage can not be over
1.5 Volt to inhibit chip damage.
VSSP (7)
VSS (7)
I
I
I
I
Power ground for PWM or DAC playing output.
Power ground
VDDP (7)
VDD (7)
Power source for PWM or DAC playing output.
Power ground.
(4) RD1~3 are shared as RDP/SPDATA/WRP to interface with W55XXX @W536030A/060A
(5) @W536120A only
(6) 0.1uF is default value, and capacitor value should be larger than 0.1uF if LCD dot size over
0.5mm * 0.5mm.
(7) External application circuit should connect together, please refer to APPLICATION CIRCUIT. To
sure chip operation properly, please bond all VDD, VDDP,VSS and VSSP pads and connect VSS
and VSSP from chip outside PCB circuit.
Publication Release Date:April 2000
- 6 -
Revision A6
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ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNIT
V
V
mW
°C
°C
Supply Voltage to Ground Potential
Applied Input/Output Voltage
Power Dissipation
Ambient Operating Temperature
Storage Temperature
-0.3 to +7.0
-0.3 to +7.0
120
0 to +70
-55 to +150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect
the life and reliability of the device.
DC CHARACTERISTICS
(VDD−VSS = 3.0V, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C, STN LCD
panel on with dot size 0.5mm*0.5mm; unless otherwise specified)
PARAMETER
Op. Voltage
Op. Current
(No Load, no Voice, no )
Melody)
SYM. CONDITIONS
VDD
MIN
2.4
-
TYP
MAX UNIT
5.5
700
700
50
V
uA
IOP1
Dual clock with crystal
600
600
40
70
6
Dual clock with RC type
Sub-clock only, LCD off
Sub-clock only, LCD on
Sub-clock active only
90
Hold Mode Current
(No Load, LCD OFF)
Hold Mode Current
(No load, LCD ON)
Stop Mode Current
IOP2
IOP3
10
uA
uA
Sub-clock active only
70
IOP4
IoH1
LCD auto off
Vout=2.7V
1
uA
RDP/WRP Output High
Current
-0.8
mA
RDP/WRP Output low
Current
IoL1
Vout=0.4V
0.8
mA
Input Low Voltage
Input High Voltage
Port RA, RB Output Low
Voltage
VIL
VIH
VABL
-
-
VSS
0.7
-
-
-
-
0.3
1
0.4
VDD
VDD
V
IOL = 2.0 mA
Port RA, RB Output High
Voltage
VABH IOH = -2.0 mA
2.4
-
-
V
Pull-up Resistor
RCD
RRES
ISPH
Port RC, RD
-
200
50
300
100
-20
-70
400
200
KΩ
KΩ
mA
RES Pull-up Resistor
PWM1/2 Source Current (8)
Volume Option =00
Volume Option =01
(R
=8Ω between PWM1
LOAD
And PWM2 )
Volume Option =10
Volume Option =11
Volume Option =00
Volume Option =01
-110
-135
20
PWM1/2 Sink Current (8)
ISPL
mA
70
(R
=8Ω between PWM1
LOAD
And PWM2 )
Volume Option =10
Volume Option =11
110
135
Publication Release Date:April 2000
Revision A6
- 7 -
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DAC output Current
LCD Supply Current
COM/SEG On Resistor
V2 Pad Output Voltage
IDAC
ILCD
RON
VDD=3v, RL=100ohm
No Load, All Seg. ON
-4
-
-5
50
-6
-
mA
µA
Ω
5K
10K
1.45
IOH = ± 50 µA
Depended on LCDM4
0.7
V
V
RR
V
D1
V
R2
V2 Pad Output Deviation (9)
V2 Pad Voltage Step
No Load
%
± 5
LCDM4 increased 1
50
mV
V
V6 Pad Output Voltage
(LCD's VLCD depended on
LCDM4 register) (9)
VLCD 1/4 Bias & no load
3.8
3.85
* V2
4.8
* V2 * V2
1.5
3.9
* V2
4.85
* V2
4.75
* V2
1/5 Bias & no load
V2 input voltage
VEXT
LCDM3.3=1
V
(8)
(9)
PWM current deviation will be ±20%.
Deviation is governed by LCD dot size. More larger LCD dot will get larger deviation..
AC CHARATERISTICS
(VDD−VSS = 3.0V, FM = 4 MHz with RC mode, Fs = 32.768 KHz, with Xtal mode, TA = 25° C, STN LCD
on with dot size 0.5mm*0.5mm; unless otherwise specified)
PARAMETER
SYM.
CONDITIONS
MIN. TYP.
MAX. UNIT
Sub-clock Frequency
FSUB
Crystal type and X32IN
and X32O with 17pF
external cap.
32768
Hz
Main-clock Frequency
Chip Operation Frequency
FM
FOSC
RC type/Crystal type
SCR0.0=1,FSYS=FSUB
400K
-
4M
Hz
Hz
32768
SCR0.0=0;FSYS= FMAIN 400K
-
4M
Instruction Cycle Time
Reset Active Width
Interrupt Active Width
Main clock RC frequency
(10)
TCYC
TRAW
TIAW
One machine cycle
FOSC = 32.768 KHz
FOSC = 32.768 KHz
RXIN =680KΩ
RXIN =330K Ω
RXIN =200KΩ
RXIN =130KΩ
RSUB=680KΩ
RSUB=680KΩ
-
1
1
4/FOSC
-
-
1M
2M
3M
4M
32
-
-
-
S
µS
µS
Hz
FRXIN
Sub-Clock Ring Oscillator
Sub-Clock Oscillation
FRSUB
FSTOP
KHz
S
0.8
1
Stable Time @ Cold Start
Frequency Deviation of
main-clock FRXIN ≤ 2MHz
10
%
%
%
f(3V) − f(2.4V)
f(3V)
∆f
f
Frequency Deviation of
main-clock FRXIN = 3 MHz
15
20
f(3V) − f(2.4V)
f(3V)
∆f
f
Frequency Deviation of
main-clock FRXIN =4 MHz
f(3V) − f(2.4V)
f(3V)
∆f
f
ROSC Frequency
Frequency Deviation of
FROSC = 3MHz
FROSC
3
MHz
%
ROSC=680KΩ
f(3V) − f(2.4V)
7.5
∆f
f
f(3V)
Frame frequency
FLCD
LCDM1=0111 b(default)
64
Hz
(10)The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor
Publication Release Date:April 2000
Revision A6
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Iop Vs. Main clock RC mode
1000
800
600
400
200
0
3V
4.5V
Iop (uA)
1
2
3
4
Freq (MhZ)
Oscillation Freq Vs. Sub-Clock
44
40
36
32
28
24
20
3V
4.5V
Fsub (KhZ)
560 620 680 750 820
1K
Rsub (Kohm)
Publication Release Date:April 2000
Revision A6
- 9 -
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ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢁꢂꢃꢄꢅꢃꢅꢆꢇꢅꢄꢅꢆꢇꢅꢈꢅꢆꢇꢉꢊꢅꢆꢀ
Main Freq Vs. Rxin
6
5
4
3
2
1
0
2.4V
3v
Fmain
(MhZ)
4.5V
5.5V
130 150 160 200 330 680 2K 3K
RXIN (Kohm)
Voice Operating Freq. Vs. ROSC
4.5
4
3.5
3
3V
Freq (MhZ)
4.5V
2.5
2
470
560
680
910
ROSC (Kohm)
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢁꢂꢃꢄꢅꢃꢅꢆꢇꢅꢄꢅꢆꢇꢅꢈꢅꢆꢇꢉꢊꢅꢆꢀ
APPLICATION CIRCUIT--1: Sub clock with RC mode
VLCD> (VDD-0.5v)
Panel
VDDP
RA0~3
RB0~3
RC0~3
RD0~3
RE0~3
RF0~3
470
VDD
*
R5
( 2)
(*3)
RES
C9
PWMP/DAC
Battery
PWMN
DH1
VDDP
W536xxxA
C11
R4
C1
-
DH2
+
VDD
C10
C6
V6
V5
V4
V3
V2
R1
R3
(*1)
ROSC
XIN
C5
C4
X32IN
C3
C2
R2
X32O
Component C1~C6 C7,C8 C9,C10 C11 R1
R2
R3
R4
Value
0.1uF
-
0.1uF
1uF 680K 680K 680Kohm/1Mhz 100
330Kohm/2Mhz
200Kohm/3Mhz
130Kohm/4Mhz
Note:
(1) C1~C6 depends on LCD panel dot size.
(2) Option R5 equals to 100Ω if high noise immunity is needed.
(3) For DAC option application.
(4) To sure chip operation properly, please bond all VDDP, VDD, VSSP and VSS .
Publication Release Date:April 2000
Revision A6
- 11 -
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢁꢂꢃꢄꢅꢃꢅꢆꢇꢅꢄꢅꢆꢇꢅꢈꢅꢆꢇꢉꢊꢅꢆꢀ
APPLICATION CIRCUIT---2 : Sub clock with Crystal mode
VLCD> (VDD-0.5v)
Panel
VDDP
RA0~3
RB0~3
RC0~3
RD0~3
RE0~3
RF0~3
470
VDD
*
( 2)
(*3)
R5
RES
PWMP/DAC
C9
Battery
PWMN
DH1
VDDP
W536xxxA
R4
C11
C10
C1
+
-
DH2
VDD
C6
V6
V5
V4
V3
V2
R1
R3
(*1)
ROSC
XIN
C5
C4
C3
C2
C7
X32IN
32.768kHz
C8
X32O
Component
Value
C1~C6
0.1uF
C7,C8
15~20pF 0.1uF
C9,C10 C11 R1
R2 R3
R4
1uF 680K
-
680Kohm/1Mhz 100
330Kohm/2Mhz
200Kohm/3Mhz
130Kohm/4Mhz
Note:
(1) C1~C6 depends on LCD panel dot size.
(2) Option R5 equals to 100Ω if high noise immunity is needed.
(3) For DAC option application.
(4) To sure chip operation properly, please bond all VDDP, VDD, VSSP and VSS .
Publication Release Date:April 2000
- 12 -
Revision A6
相关型号：
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