XR16L2751_05_技术文档

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XR16L2751

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

OCTOBER 2005

REV. 1.2.2

FEATURES

GENERAL DESCRIPTION

• 2.25 to 5.5 Volt Operation

• 5 Volt Tolerant Inputs

• Functionally Compatible to ST16C2550 and

XR16C2850 with 4 additional inputs

1

The XR16L2751 (2751) is a low voltage dual

universal asynchronous receiver and transmitter

(UART) with 5 Volt tolerant inputs. The device

includes

2

additional capabilities over the

XR16L2750: Intel and Motorola data bus selection

and a “PowerSave” mode to further reduce sleep

current to a minimum during sleep mode. The 2751’s

register set is compatible to the ST16C2550 and

XR16C2850 but with added functions. It supports the

Exar’s enhanced features of 64 bytes of TX and RX

FIFOs, programmable FIFO trigger level, FIFO level

counters, automatic hardware and software flow

control, automatic RS-485 half duplex direction

control with programmable turn-around delay, and a

complete modem interface. Onboard registers

provide the user with operational status and data

error tags. An internal loopback capability allows

onboard diagnostics. Independent programmable

baud rate generator is provided in each UART

channel to support data rates up to 6.25 Mbps.

• Intel or Motorola Data Bus Interface Select

• Two Independent UARTs

■ Up to 6.25 Mbps at 5 Volt, 4 Mbps at 3.3 Volt,

and 3 Mbps at 2.5 Volt with 8X sampling rate

■ 64 bytes of Transmit and Receive FIFOs

■ Transmit and Receive FIFO Level Counters

■ Programmable TX and RX FIFO Trigger Levels

■ Automatic Hardware (RTS/CTS) Flow Control

■ Selectable RTS Flow Control Hysteresis.

■ Automatic Software (Xoff/Xon) Flow Control

■ Automatic RS-485 2-wire Half-duplex Direction

Control to the Transceiver via RTS#

■ Full Modem Interface

■ Infrared Receive and Transmit Encoder/

NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787

decoder

APPLICATIONS

• PowerSave Feature reduces sleep current to 15

µA at 3.3 Volt

• Portable and Battery Operated Appliances

• Wireless Access Servers

• Ethernet Network Routers

• Cellular Data Devices

• Telecommunication Network Routers

• Factory Automation and Process Controls

• Device Identification

• Crystal or external clock input

• Industrial and Commercial Temperature ranges

• 48 TQFP Package (7 x 7 x 1.0 mm)

FIGURE 1. XR16L2751 BLOCK DIAGRAM

*5 Volt Tolerant Inputs

(Except XTAL1)

2.25 to 5.5 Volt VCC

GND

PwrSave

A2:A0

D7:D0

UART Channel A

IOR# (VCC)

TXA, RXA, DTRA#,

DSRA#, RTSA#,

DTSA#, CDA#, RIA#,

OP2A#

IOW# (R/W#)

64 Byte TX FIFO

UART

CSA# (CS#)

CSB# (A3)

Regs

IR

ENDEC

TX & RX

BRG

INTA (IRQ#)

INTB (logic 0)

64 Byte RX FIFO

TXB, RXB, DTRB#,

DSRB#, RTSB#,

CTSB#, CDB#, RIB#,

OP2B#

TXRDYA#

TXRDYB#

RXRDYA#

RXRDYB#

Intel or

Motorola

Data Bus

Interface

UART Channel B

(same as Channel A)

XTAL1

XTAL2

Reset (Reset#)

16/68#

Crystal Osc/Buffer

CLKSEL

HDCNTL#

2751BLK

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XR16L2751

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

FIGURE 2. PIN OUT ASSIGNMENT

RESET

DTRB#

DTRA#

RTSA#

OP2A#

RXRDYA#

INTA

D5

D6

1

2

36

35

34

33

32

31

30

29

28

27

26

25

D7

3

RXB

4

RXA

5

XR16L2751

48-pin TQFP

(16 Mode )

TXRDYB#

TXA

6

7

INTB

TXB

8

A0

OP2B#

CSA#

CSB#

9

A1

10

11

A2

CLKSEL

PWRSAVE 12

VCC

RESET#

DTRB#

DTRA#

RTSA#

OP2A#

RXRDYA#

IRQ#

D5

D6

1

2

36

35

34

33

32

31

30

29

28

27

26

25

D7

3

RXB

4

RXA

5

XR16L2751

48-pin TQFP

(68 Mode )

TXRDYB#

TXA

6

7

INTB

TXB

8

A0

OP2B#

CS#

9

A1

10

11

A2

A3

CLKSEL

PWRSAVE 12

GND

ORDERING INFORMATION

PART NUMBER

PACKAGE

OPERATING TEMPERATURE RANGE

0°C to +70°C

DEVICE STATUS

Active

XR16L2751CM

48-Lead TQFP

XR16L2751IM

-40°C to +85°C

Active

2

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

PIN DESCRIPTIONS

Pin Description

48-TQFP

NAME

PIN #

TYPE

DESCRIPTION

DATA BUS INTERFACE

A2

A1

A0

26

27

28

I

Address data lines [2:0]. These 3 address lines select one of the internal registers in

UART channel A/B during a data bus transaction.

D7

D6

D5

D4

D3

D2

D1

D0

3

I/O Data bus lines [7:0] (bidirectional).

2

1

48

47

46

45

44

IOR#

19

15

I

When 16/68# pin is HIGH, the Intel bus interface is selected and this input becomes

read strobe (active low). The falling edge instigates an internal read cycle and

retrieves the data byte from an internal register pointed by the address lines [A2:A0],

puts the data byte on the data bus to allow the host processor to read it on the rising

edge.

(VCC)

When 16/68# pin is LOW, the Motorola bus interface is selected and this input is not

used and should be connected to VCC.

IOW#

When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write

strobe (active low). The falling edge instigates the internal write cycle and the rising

edge transfers the data byte on the data bus to an internal register pointed by the

address lines.

(R/W#)

When 16/68# pin is LOW, the Motorola bus interface is selected and this input

becomes read (HIGH) and write (LOW) signal.

CSA#

(CS#)

10

11

I

When 16/68# pin is HIGH, this input is chip select A (active low) to enable channel A

in the device.

When 16/68# pin is LOW, this input becomes the chip select (active low) for the

Motorola bus interface.

CSB#

(A3)

When 16/68# pin is HIGH, this input is chip select B (active low) to enable channel B

in the device.

When 16/68# pin is LOW, this input becomes address line A3 which is used for chan-

nel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1

selects channel B.

INTA

30

O

When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A inter-

rupt output. The output state is defined by the user through the software setting of

MCR[3]. INTA is set to the active mode and OP2A# output to a logic 0 when MCR[3]

is set to a logic 1. INTA is set to the three state mode and OP2A# to a logic 1 when

MCR[3] is set to a logic 0. See MCR[3].

(IRQ#)

When 16/68# pin is LOW for Motorola bus interface, this output becomes device

interrupt output (active low, open drain). An external pull-up resistor is required for

proper operation.

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XR16L2751

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

Pin Description

48-TQFP

NAME

TYPE

DESCRIPTION

PIN #

INTB

29

O

When 16/68# pin is HIGH for Intel bus interface, this output becomes channel B inter-

rupt output. The output state is defined by the user and through the software setting

of MCR[3]. INTB is set to the active mode and OP2B# output to a logic 0 when

MCR[3] is set to a logic 1. INTB is set to the three state mode and OP2B# to a logic 1

when MCR[3] is set to a logic 0. See MCR[3].

When 16/68# pin is LOW for Motorola bus interface, this output is not used and will

stay at logic zero level. Leave this output unconnected.

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

43

31

6

O

UART channel A Transmitter Ready (active low). The output provides the TX FIFO/

THR status for transmit channel A.

UART channel A Receiver Ready (active low). This output provides the RX FIFO/

RHR status for receive channel A.

UART channel B Transmitter Ready (active low). The output provides the TX FIFO/

THR status for transmit channel B.

18

UART channel B Receiver Ready (active low). This output provides the RX FIFO/

RHR status for receive channel B.

MODEM OR SERIAL I/O INTERFACE

TXA

7

O

UART channel A Transmit Data or infrared encoder data. Standard transmit and

receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be

HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is

enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the

Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.

RXA

5

I

UART channel A Receive Data or infrared receive data. Normal receive data input

must idle HIGH. The infrared receiver pulses typically idles at logic 0 but can be

inverted by software control prior going to the decoder, see MCR[6] and FCTR[2].

RTSA#

33

O

UART channel A Request-to-Send (active low) or general purpose output. This out-

put must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],

FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see

FCTR[3] and EMSR[3].

CTSA#

38

I

UART channel A Clear-to-Send (active low) or general purpose input. It can be used

for auto CTS flow control, see EFR[7], MSR[4] and IER[7]. This input should be con-

nected to VCC when not used.

DTRA#

DSRA#

34

39

O

I

UART channel A Data-Terminal-Ready (active low) or general purpose output.

UART channel A Data-Set-Ready (active low) or general purpose input. This input

should be connected to VCC when not used. This input has no effect on the UART.

CDA#

RIA#

40

41

32

I

UART channel A Carrier-Detect (active low) or general purpose input. This input

should be connected to VCC when not used. This input has no effect on the UART.

UART channel A Ring-Indicator (active low) or general purpose input. This input

should be connected to VCC when not used. This input has no effect on the UART.

OP2A#

O

Output Port 2 Channel A - The output state is defined by the user and through the

software setting of MCR[3]. When MCR[3] is set to a logic 1, INTA is set to the level

mode and OP2A# output LOW. When MCR[3] is set to a logic 0, INTA is set to the

three state mode and OP2A# is HIGH. See MCR[3]. This output must not be used as

a general output when the interrupt output is used else it will disturb the INTA output

functionality.

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

Pin Description

48-TQFP

NAME

TYPE

DESCRIPTION

PIN #

TXB

8

O

UART channel B Transmit Data or infrared encoder data. Standard transmit and

receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be

HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is

enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the

Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected.

RXB

4

I

UART channel B Receive Data or infrared receive data. Normal receive data input

must idle HIGH. The infrared receiver pulses typically idles LOW but can be inverted

by software control prior going in to the decoder, see MCR[6] and FCTR[2].

RTSB#

22

O

UART channel B Request-to-Send (active low) or general purpose output. This port

must be asserted prior to using auto RTS flow control, see EFR[6], MCR[1],

FCTR[1:0], EMSR[5:4] and IER[6]. For auto RS485 half-duplex direction control, see

FCTR[3] and EMSR[3].

CTSB#

23

I

UART channel B Clear-to-Send (active low) or general purpose input. It can be used

for auto CTS flow control, see EFR[7], and IER[7]. This input should be connected to

VCC when not used.

DTRB#

DSRB#

35

20

O

I

UART channel B Data-Terminal-Ready (active low) or general purpose output.

UART channel B Data-Set-Ready (active low) or general purpose input. This input

should be connected to VCC when not used. This input has no effect on the UART

CDB#

RIB#

16

21

9

I

UART channel B Carrier-Detect (active low) or general purpose input. This input

should be connected to VCC when not used. This input has no effect on the UART

UART channel B Ring-Indicator (active low) or general purpose input. This input

should be connected to VCC when not used. This input has no effect on the UART.

OP2B#

O

Output Port 2 Channel B - The output state is defined by the user and through the

software setting of MCR[3]. When MCR[3] is set to a logic 1, INTB is set to the level

mode and OP2B# output LOW. When MCR[3] is set to a logic 0, INTB is set to the

three state mode and OP2B# is HIGH. See MCR[3]. This output must not be used as

a general output when the interrupt output is used else it will disturb the INTB output

functionality.

ANCILLARY SIGNALS

XTAL1

XTAL2

13

14

I

Crystal or external clock input. This input is not 5V tolerant.

O

Crystal or buffered clock output. This output may be use to drive a clock buffer which

can drive other device(s).

PwrSave

16/68#

12

24

I

PowerSave (active high). This feature isolates the 2751’s data bus interface from the

host preventing other bus activities that cause higher power drain during sleep mode.

See Sleep Mode with Auto Wake-up and PowerSave Feature section for details.

Intel or Motorola Bus Select.

When 16/68# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus

type of interface.

When 16/68# pin is LOW, 68 or Motorola mode, the device will operate in the Motor-

ola bus type of interface.

CLKSEL

25

I

Baud-Rate-Generator Input Clock Prescaler Select for channel A and B. This input is

only sampled during power up or a reset. Connect to VCC for divide by 1 and GND

for divide by 4. MCR[7] can override the state of this pin following a reset or initializa-

tion. See MCR bit-7 and Figure 6 in the Baud Rate Generator section.

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XR16L2751

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

Pin Description

48-TQFP

NAME

TYPE

DESCRIPTION

PIN #

HDCNTL#

37

I

Auto RS-485 half-duplex direction output enable for channel A and B (active low).

Connect this pin to VCC for normal RTS# A/B function and to GND for auto RS-485

half-duplex direction output via the RTS# A/B pins. RTS# output goes low for transmit

and high for receive (polarity inversion is available via EMSR[3]). FCTR[3] in channel

A and B have control only if this input is disabled or at VCC.

RESET

36

I

When 16/68# pin is HIGH for Intel bus interface, this input becomes RESET (active

high). When 16/68# pin is LOW for Motorola bus interface, this input becomes

RESET# (active low).

(RESET#)

A 40 ns minimum active pulse on this pin will reset the internal registers and all out-

puts of channel A and B. The UART transmitter output will be held HIGH, the receiver

input will be ignored and outputs are reset during reset period (see UART Reset Con-

ditions).

VCC

GND

42

17

Pwr 2.25V to 5.5V power supply. All input pins, except XTAL1, are 5V tolerant.

Pwr Power supply common, ground.

Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.

1.0 PRODUCT DESCRIPTION

The XR16L2751 (2751) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and

Transmitter (UART). Its features set is compatible to the XR16L2750 and XR16C2850 devices but offers Intel

or Motorola data bus interface and PowerSave to isolate the data bus interface during Sleep mode. Hence, the

2751 adds 4 more inputs: 16/68#, PwrSave, HDCNTl# and CLKSEL pins. Each UART is independently

controlled having its own set of device configuration registers. The configuration registers set is 16550 UART

compatible for control, status and data transfer. Additionally, each UART channel has 64-bytes of transmit and

receive FIFOs, automatic RTS/CTS hardware flow control with hysteresis control, automatic Xon/Xoff and

special character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level

counters, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of

divide by 1 or 4. The XR16L2751 can operate from 2.25V to 5.5V with 5 volt tolerant inputs. The 2751 is

fabricated with an advanced CMOS process.

Enhanced Features

The 2751 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of

16 bytes in the ST16C2550, or one byte in the ST16C2450. The 2751 is designed to work with low supply

voltage and high performance data communication systems, that require fast data processing time. Increased

performance is realized in the 2751 by the larger transmit and receive FIFOs, FIFO trigger level control, FIFO

level counters and automatic flow control mechanism. This allows the external processor to handle more

networking tasks within a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of

receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at 115.2

Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However with

the 64 byte FIFO in the 2751, the data buffer will not require unloading/loading for 6.1 ms. This increases the

service interval giving the external CPU additional time for other applications and reducing the overall UART

interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic hardware/

software flow control is uniquely provided for maximum data throughput performance especially when

operating in a multi-channel system. The combination of the above greatly reduces the CPU’s bandwidth

requirement, increases performance, and reduces power consumption.

The 2751 supports a half-duplex output direction control signaling pin, RTS# A/B, to enable and disable the

external RS-485 transceiver operation. It automatically switches the logic state of the output pin to the receive

state after the last stop-bit of the last character has been shifted out of the transmitter. After receiving, the logic

state of the output pin switches back to the transmit state when a data byte is loaded in the transmitter. The

6

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

auto RS-485 direction control pin is not activated after reset. To activate the direction control function, user has

to set FCTR[3] = 1. This pin is normally high for receive state, low for transmit state.

Data Bus Interface, Intel or Motorola Type

The 2751 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor

(CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type

of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible

interface instead uses the R/W#, CS# and A3 signals for data bus transactions. Few data bus interface signals

change their functions depending on user’s selection, see pin description for details. The Intel and Motorola

bus interface selection is made through the pin, 16/68#, pin 24.

Data Rate

Each channel in the 2751 is capable of operation up to 3.125 Mbps at 5V, 2 Mbps at 3.3V and 1 Mbps at 2.5V

supply with 16X internal sampling clock rate, and 6.25 Mbps at 5V, 4 Mbps at 3.3V and 2 Mbps at 2.5V with 8X

sampling clock rate. The device can operate with an external 24 MHz crystal on pins XTAL1 and XTAL2, or

external clock source of up to 50 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a

software option, the user can set the prescaler bit for data rates of up to 1.84 Mbps.

Internal Enhanced Register Sets

Each UART has a set of enhanced registers providing control and monitoring functions for interrupt enable/

disable and status, FIFO enable/disable, programmable TX and RX FIFO trigger level, TX and RX FIFO level

counters, automatic hardware/software flow control enable/disable with selectable hysteresis, automatic RS-

485 half-duplex direction control output enable/disable, programmable baud rates, infrared encoder/decoder

enable/disable, modem interface controls and status, and sleep mode are all standard features. Following a

power on reset or an external reset (and operating in 16 or Intel Mode), the registers defaults to the reset

condition and its is compatible with previous generation of UARTs, 16C450, 16C550, 16C650A and 16C850.

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XR16L2751

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

2.0 FUNCTIONAL DESCRIPTIONS

2.1

CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The 2751 data interface supports the Intel compatible types of CPUs and it is compatible to

the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus

transaction. Each bus cycle is asynchronous using CSA/B#, IOR# and IOW# or CS#, R/W# and A3 inputs.

Both UART channels share the same data bus for host operations. A typical data bus interconnection for Intel

and Motorola mode is shown in Figure 3.

FIGURE 3. XR16L2751 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS

VCC

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

UART

Channel A

Serial Interface of

RS-232, RS-485

A0

A1

A0

A1

A2

RIA#

OP2A#

(no connect)

IOR#

IOW#

TXB

RXB

CSA#

CSB#

UART_CSA#

UART_CSB#

DTRB#

RTSB#

CTSB#

DSRB#

CDB#

UART_INTA

UART_INTB

INTA

INTB

UART

Channel B

Serial Interface of

RS-232, RS-485

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

RIB#

OP2B#

(no connect)

UART_RESET

RESET

GND

Intel Data Bus Interconnections

2750_int

D0

D1

D2

D3

D4

D5

D6

D7

D0

2.25 to 5.5 Volt VCC

VCC

D1

D2

D3

TXA

RXA

D4

D5

D6

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

D7

UART

Channel A

RS-232 Serial Interface

A0

A1

A2

A0

A1

A2

A3

CSB#

RIA#

OP2A#

(no connect)

VCC

IOR#

IOW#

R/W#

TXB

RXB

CSA#

UART_CS#

VCC

DTRB#

RTSB#

CTSB#

DSRB#

CDB#

UART

Channel B

UART_IRQ#

INTA

INTB

RS-232 Serial Interface

(no connect)

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

RIB#

OP2B#

GND

UART_RESET#

RESET#

Motorola Data Bus Interconnections

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

2.2

5-Volt Tolerant Inputs

The 2751 can accept up to 5V inputs when operating at 3.3V or 2.5V. But note that if the 2751 is operating at

2.5V, its V may not be high enough to meet the requirements of the V of a CPU or a serial transceiver that

OH

IH

is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.

2.3

Device Hardware Reset

The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to

their default state (see Table 17). An active pulse of longer than 40 ns duration will be required to activate the

reset function in the device.

2.4

Device Identification and Revision

The XR16L2751 provides a Device Identification code and a Device Revision code to distinguish the part from

other devices and revisions. To read the identification code from the part, it is required to set the baud rate

generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x0A for the

XR16L2751 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01

means revision A.

2.5

Channel A and B Selection

The UART provides the user with the capability to bi-directionally transfer information between an external

CPU and an external serial communication device. During Intel Bus Mode (16/68# pin connected to VCC), a

logic 0 on chip select pins, CSA# or CSB#, allows the user to select UART channel A or B to configure, send

transmit data and/or unload receive data to/from the UART. Selecting both UARTs can be useful during power

up initialization to write to the same internal registers, but do not attempt to read from both UARTs

simultaneously. Individual channel select functions are shown in Table 1.

TABLE 1: CHANNEL A AND B SELECT IN 16 MODE

CSA#

CSB#

FUNCTION

1

0

1

0

1

0

UART de-selected

Channel A selected

Channel B selected

Channel A and B selected

During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for

connection with Motorola, and other popular microprocessor bus types. In this mode the 2751 decodes an

additional address, A3, to select one of the UART ports. The A3 address decode function is used only when in

the Motorola Bus Mode. See Table 2.

TABLE 2: CHANNEL A AND B SELECT IN 68 MODE

CS#

A3

N/A

0

FUNCTION

1

0

UART de-selected

Channel A selected

Channel B selected

1

2.6

Channel A and B Internal Registers

Each UART channel in the 2751 has a set of enhanced registers for control, monitoring and data loading and

unloading. The configuration register set is compatible to those already available in the standard single

16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status

and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers, (LSR/

LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/

DLM), and an user accessible Scratchpad register (SPR).

9

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

Beyond the general 16C2550 features and capabilities, the 2751 offers enhanced feature registers (EFR, Xon/

Xoff 1, Xon/Xoff 2, FCTR, TRG, EMSR, FC) that provide automatic RTS and CTS hardware flow control, Xon/

Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger level

control and FIFO level counters. All the register functions are discussed in full detail later in “Section 3.0,

UART INTERNAL REGISTERS” on page 22.

2.7

DMA Mode

The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t

mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of

the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional

flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is

empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive

FIFO in the DMA mode (FCR bit-3 = 1). When the transmit and receive FIFO are enabled and the DMA mode

is disabled (FCR bit-3 = 0), the 2751 is placed in single-character mode for data transmit or receive operation.

When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or

unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the 2751

sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO

becomes empty. The following table shows their behavior. Also see Figures 20 through 25.

TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE

FCR BIT-0=0

PINS

FCR BIT-0=1 (FIFO ENABLED)

(FIFO DISABLED)

FCR BIT-3 = 0

(DMA MODE DISABLED)

FCR BIT-3 = 1

(DMA MODE ENABLED)

RXRDY# A/B LOW = 1 byte.

HIGH = no data.

LOW = at least 1 byte in FIFO. HIGH to LOW transition when FIFO reaches the

trigger level, or time-out occurs.

HIGH = FIFO empty.

LOW to HIGH transition when FIFO empties.

TXRDY# A/B LOW = THR empty. LOW = FIFO empty.

LOW = FIFO has at least 1 empty location.

HIGH = byte in THR. HIGH = at least 1 byte in FIFO. HIGH = FIFO is full.

2.8

INTA and INTB Outputs

The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.

Table 4 and 5 summarize the operating behavior for the transmitter and receiver. Also see Figures 20

through 25.

TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER

FCR BIT-0 = 0

AUTO RS485

MODE

FCR BIT-0 = 1 (FIFO ENABLED)

LOW = FIFO above trigger level

(FIFO DISABLED)

INTA/B Pin

NO

LOW = a byte in THR

HIGH = THR empty

HIGH = FIFO below trigger level or FIFO empty

YES

LOW = a byte in THR

LOW = FIFO above trigger level

HIGH = transmitter empty

HIGH = FIFO below trigger level or transmitter empty

TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER

FCR BIT-0 = 0

FCR BIT-0 = 1

(FIFO DISABLED)

(FIFO ENABLED)

INTA/B Pin

LOW = no data

HIGH = 1 byte

LOW = FIFO below trigger level

HIGH = FIFO above trigger level

10

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

2.9

Crystal Oscillator or External Clock Input

The 2751 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the

device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a

system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the

oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not

5V tolerant and so the maximum voltage at the pin should be VCC. For programming details, see

“Programmable Baud Rate Generator.”

FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS

XTAL1

XTAL2

R1

0-120

(Optional)

R2

500K - 1M

1.8432 MHz

to

Y1

24 MHz

C1

C2

22-47pF

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,

fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency

tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 5). The programmable Baud

Rate Generator is capable of operating with a crystal oscillator frequency of up to 24 MHz. However, with an

external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as shown in Figure 5) it can

extend its operation up to 50 MHz (6.25 Mbps serial data rate) at 5V with an 8X sampling rate.

FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE

E xternal C lock

vcc

XTA L1

gnd

V C C

R 1

2K

XTA L2

For further reading on the oscillator circuit please see the Application Note DAN108 on the EXAR web site at

http://www.exar.com.

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

2.10

Programmable Baud Rate Generator

Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by CLKSEL

hardware pin or a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input

crystal or external clock by 1 or 4 and can override the CLKSEL pin following reset. The clock output of the

16

prescaler goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (2

-

1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter

for data bit shifting and receiver for data sampling. The BRG divisor defaults to the maximum baud rate (DLL =

0x01 and DLM = 0x00) upon power up.

FIGURE 6. BAUD RATE GENERATOR AND PRESCALER

DLL and DLM

Registers

MCR Bit-7=0

(default)

Prescaler

Divide by 1

16X

Crystal

Osc/

Buffer

XTAL1

XTAL2

Sampling

Rate Clock to

Transmitter

Baud Rate

Generator

Logic

Prescaler

Divide by 4

MCR Bit-7=1

Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the

operating data rate. Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external

clock at 16X sampling rate clock rate. A 16X sampling clock is typically used. However, user can select the 8X

sampling clock rate mode (EMSR bit-7=0) to double the operating data rate. When using a non-standard data

rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation.

divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit-7] = 1

divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR bit-7] = 0

TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK

OUTPUT Data Rate OUTPUT Data Rate

DLM

PROGRAM

VALUE (HEX) VALUE (HEX)

DLL

PROGRAM

DATA RATE

ERROR (%)

DIVISOR FOR 16x DIVISOR FOR 16x

Clock (Decimal) Clock (HEX)

MCR Bit-7=1

MCR Bit-7=0

(DEFAULT)

100

600

400

2304

384

192

96

48

24

12

6

900

180

C0

60

09

01

00

80

C0

60

30

18

0C

06

04

02

01

0

2400

1200

2400

4800

9600

19.2k

38.4k

57.6k

115.2k

230.4k

4800

9600

19.2k

38.4k

76.8k

153.6k

230.4k

460.8k

921.6k

30

18

0C

06

4

04

2

02

1

01

12

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

2.11 Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which

includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X internal

clock. A bit time is 16 (8) clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the

number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and

TSR are reported in the Line Status Register (LSR bit-5 and bit-6).

2.11.1 Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input

register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write

operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

2.11.2 Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE

Transmit

Holding

Register

(THR)

Data

Byte

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

16X or 8X

Clock

(EMSR Bit-7)

M

S

B

L

S

B

Transmit Shift Register (TSR)

TXNOFIFO1

2.11.3 Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set

whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the

amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by

IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

Transmit

FIFO

Transmit

Data Byte

THR Interrupt (ISR bit-1) falls

below the programmed Trigger

Level and then when becomes

empty. FIFO is Enabled by FCR

bit-0=1

Auto CTS Flow Control (CTS# pin)

Flow Control Characters

(Xoff1/2 and Xon1/2 Reg.

Auto Software Flow Control

16X or 8X Clock

(EMSR bit-7)

Transmit Data Shift Register

(TSR)

TXFIFO1

2.12 RECEIVER

The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a

byte-wide Receive Holding Register (RHR). The RSR uses the 16X/8X clock (EMSR bit-7) for timing. It verifies

and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or

false start bit, an internal receiver counter starts counting at the 16X/8X clock rate. After 8 clocks (or 4 if 8X) the

start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic

0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character.

The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing.

If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte

from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status

of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character

or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a

receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus

12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.

2.12.1 Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift

Register. It provides the receive data interface to the host processor. The RHR register is part of the receive

FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When

the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the

RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data

byte are immediately updated in the LSR bits 2-4.

14

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE

16X or 8X Clock

(EMSR bit-7)

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Error

Receive

Data Byte

and Errors

Receive Data

Holding Register

(RHR)

Tags in

LSR bits

4:2

RHR Interrupt (ISR bit-2)

RXFIFO1

FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE

16X Clock

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Example:

- RX FIFO trigger level selected at 16 bytes

64 bytes by 11-bit

wide FIFO

(See Note below)

RTS# re-asserts when data falls below the flow

control trigger level to restart remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

Data falls to 8

FIFO Trigger=16

Data fills to 24

Receive

Data FIFO

RHR Interrupt (ISR bit-2) programmed for

desired FIFO trigger level.

FIFO is Enabled by FCR bit-0=1

RTS# de-asserts when data fills above the flow

control trigger level to suspend remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

Receive

Data

Receive Data

Byte and Errors

RXFIFO1

NOTE: Table-B selected as Trigger Table for Figure 10 (Table 11).

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

2.13

Auto RTS (Hardware) Flow Control

Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#

output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control

features is enabled to fit specific application requirement (see Figure 11):

• Enable auto RTS flow control using EFR bit-6.

• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).

If using the Auto RTS interrupt:

• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the

RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.

2.14

Auto RTS Hysteresis

The 2751 has a new feature that provides flow control trigger hysteresis while maintaining compatibility with

the XR16C850, ST16C650A and ST16C550 family of UARTs. With the Auto RTS function enabled, an interrupt

is generated when the receive FIFO reaches the programmed RX trigger level. The RTS# pin will not be forced

HIGH (RTS off) until the receive FIFO reaches the upper limit of the hysteresis level. The RTS# pin will return

LOW after the RX FIFO is unloaded to the lower limit of the hysteresis level. Under the above described

conditions, the 2751 will continue to accept data until the receive FIFO gets full. The Auto RTS function is

initiated when the RTS# output pin is asserted LOW (RTS On). Table 14 shows the complete details for the

Auto RTS# Hysteresis levels. Please note that this table is for programmable trigger levels only (Table D). The

hysteresis values for Tables A-C are the next higher and next lower trigger levels in the corresponding table.

2.15

Auto CTS Flow Control

Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is

monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific

application requirement (see Figure 11):

• Enable auto CTS flow control using EFR bit-7.

If using the Auto CTS interrupt:

• Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the

CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as

the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-

asserted (LOW), indicating more data may be sent.

16

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION

Local UART

UARTA

Remote UART

UARTB

RXA

TXB

Receiver FIFO

Trigger Reached

Transmitter

RTSA#

TXA

CTSB#

RXB

Auto RTS

Trigger Level

Auto CTS

Monitor

Receiver FIFO

Trigger Reached

Transmitter

CTSA#

RTSB#

Auto CTS

Monitor

Auto RTS

Trigger Level

Assert RTS# to Begin

Transmission

1

10

11

ON

RTSA#

OFF

7

2

ON

3

CTSB#

TXB

8

Restart

9

Data Starts

6

Suspend

4

RXA FIFO

Receive

Data

RX FIFO

12

RTS High

Threshold

RTS Low

Threshold

5

RX FIFO

Trigger Level

INTA

(RXA FIFO

Interrupt)

RTSCTS1

The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of

remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO

(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-

tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA

monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows

(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-

mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),

UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until

next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB

with RTSB# and CTSA# controlling the data flow.

17

XR16L2751

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

2.16

Auto Xon/Xoff (Software) Flow Control

When software flow control is enabled (See Table 16), the 2751 compares one or two sequential receive data

characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the

programmed values, the 2751 will halt transmission (TX) as soon as the current character has completed

transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output

pin will be activated. Following a suspension due to a match of the Xoff character, the 2751 will monitor the

receive data stream for a match to the Xon-1,2 character. If a match is found, the 2751 will resume operation

and clear the flags (ISR bit-4).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user

can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/

Xoff characters (See Table 16) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters

are selected, the 2751 compares two consecutive receive characters with two software flow control 8-bit

values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow

control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or

FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the 2751 automatically

sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 2751 sends the

Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)

after the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition,

the 2751 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger

level below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the

trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto

RTS Hysteresis value in Table 14. Table 7 below explains this when Trigger Table-B (See Table 11) is

selected.

TABLE 7: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL

XOFF CHARACTER(S) SENT

(CHARACTERS IN RX FIFO)

XON CHARACTER(S) SENT

(CHARACTERS IN RX FIFO)

RX TRIGGER LEVEL

INT PIN ACTIVATION

8

8*

0

8

16

24

28

16

24

28

16*

24*

28*

16

24

* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2

characters); for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit

setting.

2.17

Special Character Detect

A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced

Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal

incoming RX data.

The 2751 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will

be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal

Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is

dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of

character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also

determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff

Registers corresponds with the LSB bit for the receive character.

18

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

2.18

Auto RS485 Half-duplex Control

The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR

bit-3. By default, it de-asserts RTS# (HIGH) output following the last stop bit of the last character that has been

transmitted. This helps in turning around the transceiver to receive the remote station’s response. When the

host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit FIFO. The

transmitter automatically re-asserts RTS# (LOW) output prior to sending the data. The RS485 half-duplex

direction control output can be inverted by enabling EMSR bit-3.

2.19

Infrared Mode

The 2751 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)

version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-

pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,

hence reduces the power consumption. See Figure 12 below.

The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature

is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level

of logic zero from a reset and power up, see Figure 12.

Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.

Each time it senses a light pulse, it returns a logic 1 to the data bit stream. However, this is not true with some

infrared modules on the market which indicate a logic 0 by a light pulse. So the 2751 has a provision to invert

the input polarity to accommodate this. In this case user can enable FCTR bit-2 to invert the input signal.

FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING

Character

Data Bits

1

0

TX Data

Transmit

IR Pulse

(TX Pin)

1/2 Bit Time

Bit Time

3/16 Bit Time

IrEncoder-1

Receive

IR Pulse

(RX pin)

Bit Time

1/16 Clock Delay

1

1 1

1

0

RX Data

Data Bits

Character

IRdecoder-

19

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

2.20

Sleep Mode with Wake-Up Indicator and PowerSave Feature

The 2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave

feature is included to reduce power consumption when the device is not actively used.

2.20.1 Sleep Mode

All of these conditions must be satisfied for the 2751 to enter sleep mode:

■ no interrupts pending for both channels of the 2751 (ISR bit-0 = 1)

■ sleep mode of both channels are enabled (IER bit-4 = 1)

■ modem inputs are not toggling (MSR bits 0-3 = 0)

■ RX input pins are idling HIGH

The 2751 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for

no clock output as an indication that the device has entered the sleep mode.

The 2751 resumes normal operation by any of the following when PowerSave mode is disabled (pin 12 at

ground):

■ a receive data start bit transition (HIGH to LOW)

■ a data byte is loaded to the transmitter, THR or FIFO

■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

If the sleep mode is enabled and the 2751 is awakened by one of the conditions described above, an interrupt

is issued by the 2751 to signal to the CPU that it is awake. The lower nibble of the interrupt source register

(ISR) will read a value of 0x1 for this interrupt and reading the ISR clears this interrupt. Since the same value

(0x1) is also used to indicate no pending interrupt, users should exercise caution while using the sleep mode.

The 2751 will return to the sleep mode automatically after all interrupting conditions have been serviced and

cleared. If the 2751 is awakened by the modem inputs, a read to the MSR is required to reset the modem

inputs. In any case, the sleep mode will not be entered while an interrupt is pending from channel A or B. The

2751 will stay in the sleep mode of operation until it is disabled by setting IER bit-4 to a logic 0.

A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the

first few receive characters may be lost. The number of characters lost during the restart also depends on your

operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep

RX A/B inputs idling HIGH or “marking” condition during sleep mode to avoid receiving a “break” condition

upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)

are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a

47k-100k ohm pull-up resistor on the RXA and RXB pins.

2.20.2 PowerSave Feature

If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the

2751 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical

Characteristics on page 40. If the input lines are floating or are toggling while the 2751 is in sleep mode, the

current can be up to 100 times more. If not using the PowerSave feature, then an external buffer would be

required to keep the address and data bus lines from toggling or floating to achieve the low current. But if the

PowerSave feature is enabled (pin 12 connected to VCC), this will eliminate the need for an external buffer by

internally isolating the address, data and control signals (see Figure 1 on page 1) from other bus activities that

could cause wasteful power drain. The 2751 enters PowerSave mode when pin 12 is connected to VCC and

the 2751 is in sleep mode (see Sleep Mode section above).

Since PowerSave mode isolates the address, data and control signals, the device will wake-up by:

■ a receive data start bit transition (HIGH to LOW)

■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

The 2751 will return to the PowerSave mode automatically after a read to the MSR (to reset the modem inputs)

and all interrupting conditions have been serviced and cleared. The 2751 will stay in the PowerSave mode of

operation until it is disabled by setting IER bit-4 to a logic 0 and/or the PowerSave pin is connected to GND.

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

2.21

Internal Loopback

The 2751 UART provides an internal loopback capability for system diagnostic purposes. The internal

loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it

was sending. The TX, RTS# and DTR# pins are held HIGH or mark condition while the CTS#, DSR# CD# and

RI# inputs are ignored. Caution: the RX input pins must be held to a logic 1 during loopback test else upon

exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto RTS/CTS hardware

flow control is not supported during internal loopback.

FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B

VCC

TXA/TXB

Transmit Shift Register

(THR/FIFO)

MCR bit-4=1

Receive Shift Register

(RHR/FIFO)

RXA/RXB

VCC

RTSA#/RTSB#

RTS#

CTS#

CTSA#/CTSB#

VCC

DTRA#/DTRB#

DTR#

DSR#

DSRA#/DSRB#

OP1#

RI#

RIA#/RIB#

VCC

OP2A#/OP2B#

OP2#

CD#

CDA#/CDB#

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REV. 1.2.2

3.0 UART INTERNAL REGISTERS

Each of the UART channel in the 2751 has its own set of configuration registers selected by address lines A0,

A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 8 and

Table 9.

TABLE 8: UART CHANNEL A AND B UART INTERNAL REGISTERS

ADDRESSES

REGISTER

READ/WRITE

COMMENTS

A2 A1 A0

16C550 COMPATIBLE REGISTERS

0

0 0

RHR - Receive Holding Register

Read-only

Write-only

LCR[7] = 0

THR - Transmit Holding Register

0

0 0

0 1

0 0

0 1

1 0

DLL - Div Latch Low Byte

Read/Write

Read-only

Read/Write

LCR[7] = 1, LCR ≠ 0xBF

0

DLM - Div Latch High Byte

DREV - Device Revision Code

DVID - Device Identification Code

IER - Interrupt Enable Register

DLL, DLM = 0x00,

LCR[7] = 1, LCR ≠ 0xBF

LCR[7] = 0

ISR - Interrupt Status Register

FCR - FIFO Control Register

Read-only

Write-only

LCR ≠ 0xBF

0

1

1 1

0 0

0 1

LCR - Line Control Register

Read/Write

MCR - Modem Control Register

LCR ≠ 0xBF

LSR - Line Status Register

Reserved

Read-only

Write-only

1

1 0

MSR - Modem Status Register

Reserved

Read-only

Write-only

1

1 1

SPR - Scratchpad Register

Read/Write

Read-only

Write-only

LCR ≠ 0xBF, FCTR[6] = 0

LCR ≠ 0xBF, FCTR[6] = 1

FLVL - RX/TX FIFO Level Counter Register

EMSR - Enhanced Mode Select Register

ENHANCED REGISTERS

0

0 0

TRG - RX/TX FIFO Trigger Level Register

FC - RX/TX FIFO Level Counter Register

Write-only

Read-only

LCR = 0xBF

0

1

0 1

1 0

0 0

0 1

1 0

1 1

FCTR - Feature Control Register

EFR - Enhanced Function Register

Xon-1 - Xon Character 1

Read/Write

Xon-2 - Xon Character 2

Xoff-1 - Xoff Character 1

Xoff-2 - Xoff Character 2

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

.

TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

ADDRESS

REG

READ/

WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

A2-A0

NAME

16C550 Compatible Registers

0 0 0

0 0 1

RHR

THR

RD

Bit-7

0/

Bit-6

0/

Bit-5

0/

Bit-4

0/

Bit-3

Bit-2

Bit-1

Bit-0

WR

IER RD/WR

Modem RXLine

Stat. Int.

Enable

TX

Empty

Int

RX

Data

Int.

LCR[7]=0

Stat.

Int.

CTS Int. RTS Int. Xoff Int.

Enable Enable Enable

Sleep

Mode

Enable

Enable Enable Enable

0 1 0

ISR

RD

FIFOs

0/

INT

Enabled Enabled

Source Source Source Source

INT

Bit-3

Bit-2

Bit-1

Bit-0

Source Source

Bit-5

Bit-4

LCR ≠ 0XBF

0 1 0

FCR

WR RXFIFO RXFIFO

Trigger Trigger

0/

DMA

Mode

Enable

TX

FIFO

Reset Reset

RX

FIFOs

FIFO Enable

TXFIFO TXFIFO

Trigger Trigger

0 1 1

1 0 0

LCR RD/WR Divisor Set TX Set Par-

Even

Parity

Enable

Stop

Bits

Word

Length Length

Bit-1 Bit-0

Word

Enable

Break

ity

MCR RD/WR

0/

Internal OP2#/INT Rsrvd RTS# DTR#

Lopback Output

Output Output

Control Control

(OP1#)

BRG

Pres-

caler

IR Mode XonAny

ENable

Enable

1 0 1

LSR

RD

RX FIFO THR &

THR

Empty

RX

Break

RX Fram-

ing Error Parity Over-

RX

Data

Ready

LCR ≠ 0XBF

Global

Error

TSR

Empty

Error

run

Error

1 1 0

1 1 1

MSR

CD#

RI#

DSR#

Input

CTS#

Input

Delta

CD#

Delta

RI#

Delta

DSR# CTS#

Delta

Input

SPR RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0 LCR ≠ 0xBF

FCTR[6]=0

1 1 1

EMSR

FLVL

WR

RD

16X

LSR

Error

Inter-

rupt.

Imd/Dly#

Auto

RS485

Output

Inversion

Rsrvd

Rx/Tx Rx/Tx

FIFO FIFO

Count Count

Sam-

pling

Rate

RTS

Hyst.

RTS

Hyst.

LCR ≠ 0XBF

FCTR[6]=1

bit-1

bit-0

bit-3

bit-2

Mode

1 1 1

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

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TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

ADDRESS

REG

READ/

WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

A2-A0

NAME

Baud Rate Generator Divisor

0 0 0

0 0 1

0 0 0

0 0 1

DLL RD/WR

DLM RD/WR

Bit-7

0

Bit-6

0

Bit-5

0

Bit-4

0

Bit-3

1

Bit-2

0

Bit-1

1

Bit-0

0

LCR[7]=1

LCR ≠ 0xBF

DREV

DVID

RD

LCR[7]=1

LCR≠ 0xBF

DLL=0x00

DLM=0x00

Enhanced Registers

0 0 0

0 0 1

TRG

FC

WR

RD

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Auto

Bit-2

Bit-1

Bit-0

FCTR RD/WR RX/TX SCPAD

Trig

Table

Bit-1

Trig

Table

Bit-0

RX IR

Input

Inv.

Auto

RTS

Hyst

Bit-1

Auto

RTS

Hyst

Bit-0

Mode

Swap

RS485

Direction

Control

0 1 0

EFR RD/WR

Auto

CTS

Enable Enable

Auto

RTS

Special Enable

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Char

Select

IER

[7:4],

ISR

LCR=0XBF

[5:4],

FCR[5:4]

,

Bit-2

Bit-1

Bit-0

Bit-3

MCR[7:5

]

1 0 0

1 0 1

1 1 0

1 1 1

XON1 RD/WR

XON2 RD/WR

XOFF1 RD/WR

XOFF2 RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

4.0 INTERNAL REGISTER DESCRIPTIONS

4.1 Receive Holding Register (RHR) - Read- Only

SEE”RECEIVER” ON PAGE 14.

4.2 Transmit Holding Register (THR) - Write-Only

SEE”TRANSMITTER” ON PAGE 13.

4.3 Interrupt Enable Register (IER) - Read/Write

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status

and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).

4.3.1

IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts

(see ISR bits 2 and 3) status will reflect the following:

A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed

trigger level. It will be cleared when the FIFO drops below the programmed trigger level.

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B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to

the receive FIFO. It is reset when the FIFO is empty.

4.3.2

IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L2751 in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can

be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR or RX FIFO.

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when

the receive FIFO has reached the programmed trigger level in the FIFO mode.

• Logic 0 = Disable the receive data ready interrupt (default).

• Logic 1 = Enable the receiver data ready interrupt.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-

FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is

empty when this bit is enabled, an interrupt will be generated.

• Logic 0 = Disable Transmit Ready interrupt (default).

• Logic 1 = Enable Transmit Ready interrupt.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller

about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the

character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of

the FIFO (default). Instead, LSR bits 2-4 can be programmed to generate an interrupt immediately, by setting

EMSR bit-6 to a logic 1.

• Logic 0 = Disable the receiver line status interrupt (default).

• Logic 1 = Enable the receiver line status interrupt.

IER[3]: Modem Status Interrupt Enable

• Logic 0 = Disable the modem status register interrupt (default).

• Logic 1 = Enable the modem status register interrupt.

IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)

• Logic 0 = Disable Sleep Mode (default).

• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.

IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)

• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for

details.

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IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the RTS# interrupt (default).

• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition

from low to high.

IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the CTS# interrupt (default).

• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from

low to high.

4.4

Interrupt Status Register (ISR) - Read-Only

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The

Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the

ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be

serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt

Source Table, Table 10, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources

associated with each of these interrupt levels.

4.4.1

Interrupt Generation:

• LSR is by any of the LSR bits 1, 2, 3 and 4.

• RXRDY is by RX trigger level.

• RXRDY Time-out is by a 4-char plus 12 bits delay timer.

• TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).

• MSR is by any of the MSR bits 0, 1, 2 and 3.

• Receive Xoff/Special character is by detection of a Xoff or Special character.

• CTS# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control.

• RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control.

• Wake-up Indicator is when the UART comes out of sleep mode.

4.4.2

Interrupt Clearing:

• LSR interrupt is cleared by a read to the LSR register.

• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

• RXRDY Time-out interrupt is cleared by reading RHR.

• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

• MSR interrupt is cleared by a read to the MSR register.

• Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.

• Special character interrupt is cleared by a read to ISR or after the next character is received.

• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

• Wake-up Indicator is cleared by a read to the ISR register.

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]

TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL

PRIORITY

ISR REGISTER STATUS BITS

SOURCE OF INTERRUPT

LEVEL

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

1

2

3

4

5

6

7

-

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LSR (Receiver Line Status Register)

RXRDY (Receive Data Time-out)

RXRDY (Received Data Ready)

TXRDY (Transmit Ready)

MSR (Modem Status Register)

RXRDY (Received Xoff or Special character)

CTS#, RTS# change of state

None (default) or Wake-up Indicator

ISR[0]: Interrupt Status

• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine.

• Logic 1 = No interrupt pending (default condition) or the device has come out of sleep mode.

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source

Table 10).

ISR[5:4]: Interrupt Status

These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data

match of the Xoff character(s). Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon

character is received. ISR bit-5 indicates that CTS# or RTS# has changed state.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are

enabled.

4.5

FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and

select the DMA mode. The DMA, and FIFO modes are defined as follows:

FCR[0]: TX and RX FIFO Enable

• Logic 0 = Disable the transmit and receive FIFO (default).

• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

written or they will not be programmed.

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No receive FIFO reset (default)

• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

Logic 0 = No transmit FIFO reset (default).

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Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: DMA Mode Select

Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.

• Logic 0 = Normal Operation (default).

• Logic 1 = DMA Mode.

FCR[5:4]: Transmit FIFO Trigger Select

(logic 0 = default, TX trigger level = one)

These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the

number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the

FIFO did not get filled over the trigger level on last re-load. Table 11 below shows the selections. EFR bit-4

must be set to ‘1’ before these bits can be accessed.Note that the receiver and the transmitter cannot use

different trigger tables. Whichever selection is made last applies to both the RX and TX side.

FCR[7:6]: Receive FIFO Trigger Select

(logic 0 = default, RX trigger level =1)

The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive

FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the

trigger level. Table 11 shows the complete selections. Note that the receiver and the transmitter cannot use

different trigger tables. Whichever selection is made last applies to both the RX and TX side.

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TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION

TRANSMIT

TRIGGER FCTR FCTR

FCR

BIT-7

FCR

BIT-6

FCR

BIT-5

FCR

BIT-4

RECEIVE

TRIGGER LEVEL

TRIGGER

LEVEL

COMPATIBILITY

TABLE

BIT-5

BIT-4

Table-A

0

1 (default)

16C550, 16C2550,

16C2552, 16C554,

16C580

0

1

0

1

0

1

1 (default)

4

8

14

Table-B

Table-C

Table-D

0

1

0

1

0

1

0

1

0

1

16

8

16C650A

24

30

0

1

0

1

0

1

8

16

24

28

0

1

0

1

0

1

8

16C654

16

32

56

0

1

0

1

0

1

8

16

56

60

X

Programmable Programmable 16L2752, 16C2850,

16C2852, 16C850,

16C854, 16C864

via TRG

register.

FCTR[7] = 0.

FCTR[7] = 1.

4.6

Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or

character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this

register.

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

BIT-1

BIT-0

WORD LENGTH

0

1

0

1

0

1

5 (default)

6

7

8

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LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

STOP BIT LENGTH

(BIT TIME(S))

WORD

LENGTH

BIT-2

0

1

5,6,7,8

5

1 (default)

1-1/2

2

6,7,8

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data

integrity check. See Table 12 for parity selection summary below.

• Logic 0 = No parity.

• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

data character received.

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.

• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format (default).

• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format.

LCR[5]: TX and RX Parity Select

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

• LCR BIT-5 = logic 0, parity is not forced (default).

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive

data.

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive

data.

TABLE 12: PARITY SELECTION

LCR BIT-5 LCR BIT-4 LCR BIT-3

PARITY SELECTION

No parity

X

0

1

X

0

1

0

1

Odd parity

Even parity

Force parity to mark,

“1”

1

Forced parity to

space, “0”

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LCR[6]: Transmit Break Enable

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a

“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

• Logic 0 = No TX break condition. (default)

• Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line

break condition.

LCR[7]: Baud Rate Divisors Enable

Baud rate generator divisor (DLL/DLM) enable.

• Logic 0 = Data registers are selected. (default)

• Logic 1 = Divisor latch registers are selected.

4.7

Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a

general purpose output.

• Logic 0 = Force DTR# output HIGH (default).

• Logic 1 = Force DTR# output LOW.

MCR[1]: RTS# Output

The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by

EFR bit-6 or auto RS-485 half-duplex direction control output enabled by FCTR bit-3. If the modem interface is

not used, this output may be used as a general purpose output.

• Logic 0 = Force RTS# output HIGH (default).

• Logic 1 = Force RTS# output LOW.

MCR[2]: Reserved

OP1# is not available as an output pin on the 2751. But it is available for use during Internal Loopback Mode.

In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.

MCR[3]: OP2# Output / INT Output Enable

This bit enables and disables the operation of INT/IRQ#, interrupt output. If INT/IRQ# output is not used, OP2#

can be used as a general purpose output. Also, if 16/68# pin selects Motorola bus interface mode, this bit must

be set to logic 0.

• Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH (default).

• Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.

MCR[4]: Internal Loopback Enable

• Logic 0 = Disable loopback mode (default).

• Logic 1 = Enable local loopback mode, see loopback section and Figure 13.

MCR[5]: Xon-Any Enable

• Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).

• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.

The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and

the 2751 is programmed to use the Xon/Xoff flow control.

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MCR[6]: Infrared Encoder/Decoder Enable

• Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)

• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the

infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface

requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions.

MCR[7]: BRG Clock Prescaler Select

The 2751 has a hardware pin (pin 25) to select this function upon power up or reset. After the power up or

reset, this register bit will have control and can alter the logic state.

• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable

Baud Rate Generator without further modification, i.e., divide by one (default).

• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and

feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.

4.8

Line Status Register (LSR) - Read Only

This register provides the status of data transfers between the UART and the host.

LSR[0]: Receive Data Ready Indicator

• Logic 0 = No data in receive holding register or FIFO (default).

• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

LSR[1]: Receiver Overrun Flag

• Logic 0 = No overrun error. (default)

• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens

when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register

is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error.

LSR[2]: Receive Data Parity Error Flag

• Logic 0 = No parity error (default).

• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.

This error is associated with the character available for reading in RHR.

LSR[3]: Receive Data Framing Error Flag

• Logic 0 = No framing error (default).

• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with

the character available for reading in RHR.

LSR[4]: Receive Break Flag

• Logic 0 = No break condition (default).

• Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the

FIFO mode, only one break character is loaded into the FIFO.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte

is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0

concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set

when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or

TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and

transmit shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

• Logic 0 = No FIFO error (default).

• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error

or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the

RX FIFO.

4.9

Modem Status Register (MSR) - Read Only

This register provides the current state of the modem interface input signals. Lower four bits of this register are

used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem

changes state. These bits may be used for general purpose inputs when they are not used with modem

signals.

MSR[0]: Delta CTS# Input Flag

• Logic 0 = No change on CTS# input (default).

• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

• Logic 0 = No change on DSR# input (default).

• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[2]: Delta RI# Input Flag

• Logic 0 = No change on RI# input (default).

• Logic 1 = The RI# input has changed from LOW to HIGH, ending of the ringing signal. A modem status

interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[3]: Delta CD# Input Flag

• Logic 0 = No change on CD# input (default).

• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem

status interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[4]: CTS Input Status

CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto

CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the

modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has

finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of

the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The

CTS# input may be used as a general purpose input when the modem interface is not used.

MSR[5]: DSR Input Status

Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#

bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is

not used.

MSR[6]: RI Input Status

Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the

MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.

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REV. 1.2.2

MSR[7]: CD Input Status

Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the

MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.

4.10 Scratchpad Register (SPR) - Read/Write

This is a 8-bit general purpose register for the user to store temporary data. The content of this register is

preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.

4.11 Enhanced Mode Select Register (EMSR)

This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.

EMSR[1:0]: Receive/Transmit FIFO Count (Write-Only)

When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is

operating in.

TABLE 13: SCRATCHPAD SWAP SELECTION

FCTR[6] EMSR[1] EMSR[0] Scratchpad is

0

1

X

0

1

X

0

1

0

1

Scratchpad

RX FIFO Counter Mode

TX FIFO Counter Mode

RX FIFO Counter Mode

Alternate RX/TX FIFO

Counter Mode

During Alternate RX/TX FIFO Counter Mode, the first value read after EMSR bits 1-0 have been asserted will

always be the RX FIFO Counter. The second value read will correspond with the TX FIFO Counter. The next

value will be the RX FIFO Counter again, then the TX FIFO Counter and so on and so forth.

EMSR[2]: Reserved

EMSR[3]: Automatic RS485 Half-Duplex Control Output Inversion

• Logic 0 = RTS# output is LOW during TX and HIGH during RX (default, compatible with 16C2850).

• Logic 1 = RTS# output is HIGH during TX and LOW during RX.

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

EMSR[5:4]: Extended RTS Hysteresis

TABLE 14: AUTO RTS HYSTERESIS

EMSR

BIT-5

EMSR

BIT-4

FCTR

BIT-1

FCTR

BIT-0

RTS# HYSTERESIS

(CHARACTERS)

0

1

0

1

0

1

0

±4

±6

±8

0

1

0

1

0

1

0

1

±8

±16

±24

±32

1

0

1

0

1

0

1

±40

±44

±48

±52

1

0

1

0

1

0

1

±12

±20

±28

±36

EMSR[6]: LSR Interrupt Mode

• Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an

interrupt when the character with the error is in the RHR.

• Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is

received into the FIFO.

EMSR[7]: 16X Sampling Rate Mode

Logic 0 = 8X Sampling Rate.

Logic 1 = 16X Sampling Rate (for 16C2550 compatibility, default).

4.12 FIFO Level Register (FLVL) - Read-Only

The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this is

not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.

FLVL[7:0]: FIFO Level Register

This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].

See Table 13 for details.

4.13 Baud Rate Generator Registers (DLL and DLM) - Read/Write

The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the

baud rate:

• Baud Rate = (Clock Frequency / 16) / Divisor

See MCR bit-7 and the baud rate table also.

4.14 Device Identification Register (DVID) - Read Only

This register contains the device ID (0x0A for XR16L2751). Prior to reading this register, DLL and DLM should

be set to 0x00.

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

4.15 Device Revision Register (DREV) - Read Only

This register contains the device revision information. For example, 0x01 means revision A. Prior to reading

this register, DLL and DLM should be set to 0x00.

4.16 Trigger Level (TRG) - Write-Only

User Programmable Transmit/Receive Trigger Level Register.

TRG[7:0]: Trigger Level Register

These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects

between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).

4.17 FIFO Data Count Register (FC) - Read-Only

This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count

Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is

suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.

See Table 13.

FC[7:0]: RX/TX FIFO Level Count

Receive/Transmit FIFO Level Count. Number of characters in Receiver FIFO (FCTR[7] = 0) or Transmitter

FIFO (FCTR[7] = 1) can be read via this register.

4.18

Feature Control Register (FCTR) - Read/Write

This register controls the XR16L2751 new functions.

FCTR[1:0]: RTS Hysteresis

User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to

“0”. See Table 14 for more details.

FCTR[2]: IrDa RX Inversion

• Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).

• Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).

FCTR[3]: Auto RS-485 Direction Control

The 2751 has hardware pin 37 to enable this auto RS-485 direction control function from power up, however,

pin 37 must be tied to VCC for this bit to gain control else auto RS-485 is always active.

• Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register

becomes empty and transmit shift register is shifting data out.

• Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its

output logic state from LOW to HIGH one bit time after the last stop bit of the last character is shifted out.

Also, the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The

RTS# output pin will automatically return to a LOW when a data byte is loaded into the TX FIFO. However,

RTS# behavior can be inverted by setting EMSR[3] = 1.

FCTR[5:4]: Transmit/Receive Trigger Table Select

See Table 11.

TABLE 15: TRIGGER TABLE SELECT

FCTR

BIT-5

FCTR

BIT-4

TABLE

0

1

0

1

0

1

Table-A (TX/RX)

Table-B (TX/RX)

Table-C (TX/RX)

Table-D (TX/RX)

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

FCTR[6]: Scratchpad Swap

• Logic 0 = Scratchpad register is selected as general read and write register. ST16C550 compatible mode.

• Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of

characters in transmit or receive FIFO can be read via Scratchpad register when this bit is set. Enhanced

Mode Select Register is selected when it is written into.

FCTR[7]: Programmable Trigger Register Select

• Logic 0 = Registers TRG and FC selected for RX.

• Logic 1 = Registers TRG and FC selected for TX.

4.19

Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive

character software flow control selection (see Table 16). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes

are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that

whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before

programming a new setting.

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters software flow control is supported. Combinations of software

flow control can be selected by programming these bits.

TABLE 16: SOFTWARE FLOW CONTROL FUNCTIONS

EFR BIT-3

CONT-3

EFR BIT-2

CONT-2

EFR BIT-1

CONT-1

EFR BIT-0

CONT-0

TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

0

X

0

No TX and RX flow control (default and reset)

No transmit flow control

Transmit Xon1, Xoff1

Transmit Xon2, Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2

No receive flow control

0

Receiver compares Xon1, Xoff1

Receiver compares Xon2, Xoff2

1

Transmit Xon1, Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0

1

0

1

0

1

Transmit Xon2, Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

No transmit flow control,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

EFR[4]: Enhanced Function Bits Enable

Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be

modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This

feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is

recommended to leave it enabled, logic 1.

• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR

bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and

MCR bits 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).

• Logic 1 = Enables the above-mentioned register bits to be modified by the user.

EFR[5]: Special Character Detect Enable

• Logic 0 = Special Character Detect Disabled (default).

• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with

data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set

to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If

flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work

normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works

normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character

interrupt, if enabled via IER bit-5.

EFR[6]: Auto RTS Flow Control Enable

RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is

selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and

RTS de-asserts HIGH at the next upper trigger level. RTS# will return LOW when FIFO data falls below the

next lower trigger level. The RTS# output must be asserted (LOW) before the auto RTS can take effect. RTS#

pin will function as a general purpose output when hardware flow control is disabled.

• Logic 0 = Automatic RTS flow control is disabled (default).

• Logic 1 = Enable Automatic RTS flow control.

EFR[7]: Auto CTS Flow Control Enable

Automatic CTS Flow Control.

• Logic 0 = Automatic CTS flow control is disabled (default).

• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts HIGH.

Data transmission resumes when CTS# returns LOW.

4.20 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write

These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.

For more details, see Table 7.

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

TABLE 17: UART RESET CONDITIONS FOR CHANNEL A AND B

REGISTERS

RESET STATE

DLM and DLL

Bits 15-0 = 0x0001. Only resets during a power up. It doesn’t reset

when the Reset Pin is asserted.

RHR

THR

IER

Bits 7-0 = 0xXX

Bits 7-0 = 0x00

Bits 7-0 = 0x01

Bits 7-0 = 0x00

Bits 7-0 = 0x60

FCR

ISR

LCR

MCR

LSR

MSR

Bits 3-0 = Logic 0

Bits 7-4 = Logic levels of the inputs inverted

SPR

EMSR

FLVL

Bits 7-0 = 0xFF

Bits 7-0 = 0x80

Bits 7-0 = 0x00

RESET STATE

HIGH

EFR

XON1

XON2

XOFF1

XOFF2

FC

I/O SIGNALS

TX

OP2#

HIGH

RTS#

HIGH

DTR#

HIGH

RXRDY#

TXRDY#

INT

HIGH

LOW

Three-State Condition

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

ABSOLUTE MAXIMUM RATINGS

Power Supply Range

Voltage at Any Pin

7 Volts

GND-0.3 V to 7 V

-40^oto +85^oC

Operating Temperature

-65^oto +150^oC

500 mW

Storage Temperature

Package Dissipation

ELECTRICAL CHARACTERISTICS

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)

theta-ja =59^oC/W, theta-jc = 16^oC/W

Thermal Resistance (48-TQFP)

DC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=0^OTO 70^OC (-40^OTO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25- 5.5V

LIMITS

2.5V

LIMITS

3.3V

LIMITS

5.0V

SYMBOL

PARAMETER

UNITS

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

V_ILCK

V_IHCK

V_IL

Clock Input Low Level

Clock Input High Level

Input Low Voltage

-0.3

2.0

0.6

-0.3

2.4

0.6

-0.5

3.0

0.6

V

VCC

0.8

VCC

0.8

VCC

0.8

-0.3

2.0

-0.3

2.0

-0.5

2.2

V_IH

Input High Voltage

Output Low Voltage

5.5

V_OL

0.4

V

I_OL= 6 mA

I_OL= 4 mA

0.4

I_OL= 2 mA

0.4

V_OH

Output High Voltage

2.4

V

I_OH= -6 mA

I_OH= -1 mA

2.0

I_OH= -400 uA

1.8

I_IL

I_IH

Input Low Leakage Current

Input High Leakage Current

Input Pin Capacitance

±10

5

±10

5

±10

5

uA

pF

C_IN

I_CC

Power Supply Current

1.2

6

2

5

mA

uA

I_SLEEP

Sleep Current/

15

30

See Test 1

Powersave Current

I_PWRSV

Test 1: The following inputs must remain steady at VCC or GND state to minimize sleep current: A0-A2, D0-D7,

IOR#, IOW# (R/W#), CSA# (CS#), CSB# (A3) and all modem inputs. Also, RXA and RXB inputs must idle at

logic 1 state while asleep. Floating inputs may result in sleep currents in the mA range.

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

For PowerSave, the UART internally isolates all of these inputs (except the modem inputs) therefore

eliminating any unnecessary external buffers to keep the inputs steady. SEE”POWERSAVE FEATURE” ON

PAGE 20.

AC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=0^OTO 70^OC (-40^OTO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25 - 5.5V,

70 PF LOAD WHERE APPLICABLE

LIMITS

2.5

LIMITS

3.3

LIMITS

5.0

SYMBOL

PARAMETER

UNIT

MIN

MAX

MIN

MAX MIN

MAX

-

Crystal Frequency

16

20

24

MHz

ns

CLK

OSC

T_AS

External Clock Low/High Time

External Clock Frequency

20

15

10

24

33

50

MHz

ns

Address Setup Time (16 Mode)

10

75

10

50

T_AH

T_CS

Address Hold Time (16 Mode)

Chip Select Width (16 Mode)

IOR# Strobe Width (16 Mode)

Read Cycle Delay (16 Mode)

Data Access Time (16 Mode)

Data Disable Time (16 Mode)

IOW# Strobe Width (16 Mode)

Write Cycle Delay (16 Mode)

Data Setup Time (16 Mode)

Data Hold Time (16 Mode)

Address Setup (68 Mode)

ns

150

T_RD

T_DY

T_RDV

T_DD

135

45

70

30

45

30

0

T_WR

T_DY

150

25

75

20

10

50

15

10

T_DS

T_DH

15

T_ADS

T_ADH

T_RWS

T_RDA

T_RDH

T_WDS

T_WDH

T_RWH

10

Address Hold (68 Mode)

10

R/W# Setup to CS# (68 Mode)

Read Data Access (68 mode)

Read Data Disable (68 mode)

Write Data Setup (68 mode)

Write Data Hold (68 Mode)

10

135

45

70

30

45

30

25

15

20

10

15

10

CS# De-asserted to R/W# De-asserted (68

Mode)

T_CSL

T_CSD

CS# Width (68 Mode)

150

75

50

ns

CS# Cycle Delay (68 Mode)

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2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

AC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=0^OTO 70^OC (-40^OTO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC=2.25 - 5.5V,

70 PF LOAD WHERE APPLICABLE

LIMITS

2.5

LIMITS

3.3

LIMITS

5.0

SYMBOL

PARAMETER

UNIT

MIN

MAX

MIN

MAX MIN

MAX

T_WDO

T_MOD

T_RSI

T_SSI

T_RRI

T_SI

Delay From IOW# To Output

150

1

75

50

ns

Delay To Set Interrupt From MODEM Input

Delay To Reset Interrupt From IOR#

Delay From Stop To Set Interrupt

Delay From IOR# To Reset Interrupt

Delay From Stop To Interrupt

75

1

50

1

ns

Bclk

ns

150

24

75

50

24

50

1

ns

T_INT

T_WRI

T_SSR

T_RR

Delay From Initial INT Reset To Transmit Start

Delay From IOW# To Reset Interrupt

Delay From Stop To Set RXRDY#

Delay From IOR# To Reset RXRDY#

Delay From IOW# To Set TXRDY#

Delay From Center of Start To Reset TXRDY#

Reset Pulse Width

8

24

75

1

8

Bclk

ns

150

1

Bclk

ns

150

8

75

8

50

8

T_WT

T_SRT

T_RST

N

ns

Bclk

ns

40

1

40

1

40

1

2¹⁶-1

Baud Rate Divisor

-

Bclk

Baud Clock

16X or 8X of data rate

Hz

FIGURE 14. CLOCK TIMING

CLK

EXTERNAL

CLOCK

OSC

42

xr

XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B

IOW#

Active

IOW

T_WDO

Change of state

RTS#

DTR#

Change of state

CD#

CTS#

DSR#

Change of state

T_MOD

INT

Active

T_RSI

IOR#

Active

T_MOD

Change of state

RI#

FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING

A0-A2

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

CSA#/

CSB#

T_DY

T_RD

IOR#

T_DD

T_RDV

D0-D7

Valid Data

RDTm

43

XR16L2751

xr

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING

A0-A2

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

CSA#/

CSB#

T_DY

T_WR

IOW#

T_DH

T_DS

Valid Data

T_DS

Valid Data

D0-D7

16Write

FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING

A0-A2

CS#

Valid Address

TCSL

Valid Address

TADS

TADH

TCSD

TRWS

TRWH

R/W#

D0-D7

TRDH

TRDA

Valid Data

68Read

44

xr

XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING

A0-A2

CS#

Valid Address

TCSL

Valid Address

TADS

TADH

TCSD

TRWS

TRWH

R/W#

D0-D7

T

WDH

TWDS

Valid Data

68Write

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

RX

Stop

Bit

Start

Bit

D0:D7

T_SSR

1 Byte

in RHR

INT

T_SSR

Active

Data

Active

Data

Active

Data

RXRDY#

Ready

T_RR

IOR#

(Reading data

out of RHR)

RXNFM

45

XR16L2751

xr

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

TX

(Unloading)

Stop

Bit

Start

Bit

D0:D7

IER[1]

enabled

ISR is read

INT*

T_WRI

T_SRT

TXRDY#

T_WT

IOW#

(Loading data

into THR)

*INT is cleared when the ISR is read or when data is loaded into the THR.

TXNonFIFO

FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B

Start

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

Stop

Bit

RX FIFO drops

below RX

Trigger Level

INT

T_SSR

FIFO

Empties

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

RXRDY#

First Byte is

Received in

RX FIFO

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXINTDMA#

46

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XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B

Start

Bit

Stop

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

RX FIFO drops

below RX

Trigger Level

INT

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

T_SSR

FIFO

Empties

RXRDY#

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXFIFODMA

FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX FIFO

Empty

TX

T

S

T

S

T

S

D0:D7

T

S D0:D7

T

D0:D7

T

D0:D7

T

ISR is read

T_SI

IER[1]

enabled

ISR is read

T_SRT

INT*

TX FIFO

Empty

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

Data in

TX FIFO

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.

TXDMA#

47

XR16L2751

xr

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX

(Unloading)

S

D0:D7

S

D0:D7

S

D0:D7

T

D0:D7

S

D0:D7

T

S D0:D7

T

IER[1]

enabled

ISR Read

T_SI

T_SRT

INT*

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

At least 1

empty location

in FIFO

TX FIFO

Full

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.

TXDMA

48

xr

XR16L2751

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)

D

1

36

25

37

24

D

1

D

48

13

1

2

B

e

A

2

C

A

Seating

Plane

α

A

1

L

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

MAX

1.20

0.15

A

0.039

0.002

0.047

0.006

1.00

0.05

A

1

0.037

0.041

0.95

1.05

2

B

0.007

0.004

0.346

0.272

0.011

0.008

0.362

0.280

0.17

0.09

8.80

6.90

0.27

0.20

9.20

7.10

C

D

1

e

L

a

0.020 BSC

0.50 BSC

0.018

0.030

0.45

0.75

0°

7°

0°

7°

49

XR16L2751

xr

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

REV. 1.2.2

REVISION HISTORY

DATE

REVISION

Rev P1.0.0

Rev P1.1.0

DESCRIPTION

November 2001

March 2002

Prelim data sheet.

Corrected INT output descriptions and reset state. Clarified MCR bit-3 description.

Added 68 Mode (Motorola) Data bus timing specs. Renamed Sclk to Bclk. Changed

A0-A7 in Figures 16 through 19 to A0-A2.

September 2002

Rev 1.0.0

Release into production. Clarified RTS# pin descriptions, XTAL1 pin description,

external clock description, auto RS485 half-duplex control description, EMSR bit-3

description and updated 2.5 V, I and I

DC Electrical Characteristics.

CC

SLEEP

March 2003

August 2004

Rev 1.1.0

Rev 1.2.0

Updated AC Electrical Characteristics.

Added Device Status to Ordering Information. Clarified pin descriptions- changed

from using logic 1 and logic 0 to HIGH (VCC) and LOW (GND) for input and output

pin descriptions.

April 2005

Rev 1.2.1

Rev 1.2.2

Updated the Data Access Times (T

and T

) in AC Electrical Characteristics.

RDV

RDA

October 2005

Clarified Wake-up Indicator interrupt in Sleep Mode description in “Section 2.20,

Sleep Mode with Wake-Up Indicator and PowerSave Feature” on

page 20 and “Section 4.4, Interrupt Status Register (ISR) - Read-Only”

on page 26.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or

to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected under the circumstances.

Datasheet October 2005.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

50

xr

REV. 1.2.2

XR16L2751

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

TABLE OF CONTENTS

GENERAL DESCRIPTION................................................................................................. 1

APPLICATIONS............................................................................................................................................. 1

FEATURES .................................................................................................................................................. 1

FIGURE 1. XR16L2751 BLOCK DIAGRAM................................................................................................................................................. 1

FIGURE 2. PIN OUT ASSIGNMENT............................................................................................................................................................. 2

ORDERING INFORMATION ............................................................................................................................. 2

PIN DESCRIPTIONS ......................................................................................................... 3

1.0 PRODUCT DESCRIPTION ....................................................................................................... 6

2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................... 8

2.1 CPU INTERFACE ................................................................................................................................. 8

FIGURE 3. XR16L2751 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS .................................................................................. 8

2.2 5-VOLT TOLERANT INPUTS .................................................................................................................. 9

2.3 DEVICE HARDWARE RESET ................................................................................................................. 9

2.4 DEVICE IDENTIFICATION AND REVISION ................................................................................................ 9

2.5 CHANNEL A AND B SELECTION ............................................................................................................ 9

TABLE 1: CHANNEL A AND B SELECT IN 16 MODE.................................................................................................................................... 9

TABLE 2: CHANNEL A AND B SELECT IN 68 MODE.................................................................................................................................... 9

2.6 CHANNEL A AND B INTERNAL REGISTERS ............................................................................................ 9

2.7 DMA MODE ...................................................................................................................................... 10

TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE .................................................................................................. 10

2.8 INTA AND INTB OUTPUTS ................................................................................................................ 10

TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER.............................................................................................................. 10

TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER..................................................................................................................... 10

2.9 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 11

FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS ...................................................................................................................................... 11

FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE ................................................................................................. 11

2.10 PROGRAMMABLE BAUD RATE GENERATOR ...................................................................................... 12

FIGURE 6. BAUD RATE GENERATOR AND PRESCALER ............................................................................................................................ 12

TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK.............................................................................. 12

2.11 TRANSMITTER ................................................................................................................................. 13

2.11.1 Transmit Holding Register (THR) - Write Only....................................................................................... 13

2.11.2 Transmitter Operation in non-FIFO Mode .............................................................................................. 13

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE...................................................................................................................... 13

2.11.3 Transmitter Operation in FIFO Mode ..................................................................................................... 13

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE............................................................................................. 14

2.12 RECEIVER .................................................................................................................................... 14

2.12.1 Receive Holding Register (RHR) - Read-Only ....................................................................................... 14

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE ........................................................................................................................... 15

FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE............................................................................... 15

2.13 AUTO RTS (HARDWARE) FLOW CONTROL ...................................................................................... 16

2.14 AUTO RTS HYSTERESIS ................................................................................................................. 16

2.15 AUTO CTS FLOW CONTROL ........................................................................................................... 16

FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION .............................................................................................................. 17

2.16 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL .............................................................................. 18

TABLE 7: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL....................................................................................................................... 18

2.17 SPECIAL CHARACTER DETECT ........................................................................................................ 18

2.18 AUTO RS485 HALF-DUPLEX CONTROL ........................................................................................... 19

2.19 INFRARED MODE ............................................................................................................................ 19

FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING ................................................................................. 19

2.20 SLEEP MODE WITH WAKE-UP INDICATOR AND POWERSAVE FEATURE ............................................. 20

2.20.1 Sleep Mode............................................................................................................................................ 20

2.20.2 PowerSave Feature ............................................................................................................................... 20

2.21 INTERNAL LOOPBACK ..................................................................................................................... 21

FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B........................................................................................................................ 21

3.0 UART INTERNAL REGISTERS ............................................................................................. 22

TABLE 8: UART CHANNEL A AND B UART INTERNAL REGISTERS.............................................................................................. 22

TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1................................................. 23

I

XR16L2751

xr

REV. 1.2.2

2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE

4.0 INTERNAL Register descriptions ........................................................................................ 24

4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ........................................................................... 24

4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ......................................................................... 24

4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ........................................................................... 24

4.3.1 IER versus Receive FIFO Interrupt Mode Operation................................................................................ 24

4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 25

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................ 26

4.4.1 Interrupt Generation: ................................................................................................................................ 26

4.4.2 Interrupt Clearing:..................................................................................................................................... 26

TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL............................................................................................................................. 27

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ............................................................................... 27

TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION.................................................................................. 29

4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ................................................................................. 29

TABLE 12: PARITY SELECTION................................................................................................................................................................ 30

4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE ........ 31

4.8 LINE STATUS REGISTER (LSR) - READ ONLY ..................................................................................... 32

4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ............................................................................... 33

4.10 SCRATCHPAD REGISTER (SPR) - READ/WRITE ................................................................................. 34

4.11 ENHANCED MODE SELECT REGISTER (EMSR) ................................................................................. 34

TABLE 13: SCRATCHPAD SWAP SELECTION............................................................................................................................................ 34

TABLE 14: AUTO RTS HYSTERESIS ....................................................................................................................................................... 35

4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY ................................................................................... 35

4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE ............................................... 35

4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................. 35

4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY ......................................................................... 36

4.16 TRIGGER LEVEL (TRG) - WRITE-ONLY ............................................................................................. 36

4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY ............................................................................ 36

4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE .................................................................... 36

TABLE 15: TRIGGER TABLE SELECT ....................................................................................................................................................... 36

4.19 ENHANCED FEATURE REGISTER (EFR) ........................................................................................... 37

TABLE 16: SOFTWARE FLOW CONTROL FUNCTIONS ............................................................................................................................... 37

4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ............... 38

TABLE 17: UART RESET CONDITIONS FOR CHANNEL A AND B ................................................................................................... 39

ABSOLUTE MAXIMUM RATINGS...................................................................................40

ELECTRICAL CHARACTERISTICS ................................................................................40

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)40

DC ELECTRICAL CHARACTERISTICS ...........................................................................................................40

AC ELECTRICAL CHARACTERISTICS............................................................................................................41

Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=2.25 - 5.5V, 70 pF load

where applicable41

FIGURE 14. CLOCK TIMING .................................................................................................................................................................... 42

FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B......................................................................................................... 43

FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING .......................................................................................................................... 43

FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING ......................................................................................................................... 44

FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING.................................................................................................................. 44

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B................................................................. 45

FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING ................................................................................................................ 45

FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B............................................................... 46

FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B ............................................... 46

FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B ................................................ 47

FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B................................... 47

FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B.................................... 48

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)...............................................49

REVISION HISTORY ....................................................................................................................................50

TABLE OF CONTENTS ................................................................................................................................. I

II


型号：	XR16L2751_05
厂家：	EXAR CORPORATION
描述：	2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE 具有64字节FIFO和省电2.25V至5.5V DUART 先进先出芯片
文件：	总52页 (文件大小：936K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XR16L2751_05 [EXAR]

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