XRT4500 [EXAR]
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC; 多协议串行网络接口IC
| 型号： | XRT4500 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | MULTIPROTOCOL SERIAL NETWORK INTERFACE IC |
| 文件： | 总99页 (文件大小：1311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
SEPTEMBER 2002
REV. 1.0.7
FEATURES
GENERAL DESCRIPTION
• Pin Programmable Multiprotocol Serial Interface
The XRT4500 is a fully integrated multiprotocol serial
interface. It supports all of the popular serial commu-
nication interface standards such as ITU-T V.35, ITU-
T V.36, EIA530A, RS232 (ITU-T V.28), ITU-T X.21
and RS449. It can easily be interfaced with most
common types of Serial Communications Controllers
(SCCs). This device contains eight receivers and
eight transmitters, in groups of six or seven. It is a
complete solution containing all of the required
source and load termination resistors in one 80-pin
TQFP package. The XRT4500 operates at higher
speeds (20MHz for V.35 and 256kbps for V.28).
• V.35, V.36, EIA-530 A, RS232 (V.28), V.10, V.11, X.21
and RS449 Communication Interface Standards
• V.28, V.10, V.11 and V.35 Electrical Interfaces are
‘CTR2’ Compliant
• Contains On-Chip Source and Load Termination
Resistors
• Contains Eight Receivers and Eight Transmitters
with Switchable DTE and DCE Modes
• Glitch Filters on the Control Signals (Selectable)
• +5V Single Power Supply with internal DC-DC
The XRT4500 can be configured to operate in one of
the seven interface standards in either DTE, or DCE
modes of operation and power down mode. It fully
supports echoed clock as well as clock and data in-
version. Loopbacks are supported in DTE and DCE
modes of operation. This feature eliminates the need
for external circuitry for loopback implementation.
Converter
• Full Support of Loopbacks, Data & Clock Inversion,
and Echoed Clock in DTE and DCE Modes
• Full Support of Most Popular Types of HDLC Control-
lers (Single, Double, and Triple Clocks supported)
• High-speed V.28 Driver: 256KHz
• Internal Oscillator for Standalone DTE Loopback
Testing
Control signals such as RI, RL, DCD, DTR, DSR are
protected against glitches by internal filters. These fil-
ters can be turned off. The XRT4500 provides an in-
ternal oscillator (clock signal) which can be used to
conduct standalone diagnostics of DTE equipment.
• Control Signals Can Be Registered and Non-regis-
tered
• Control Signals Can Be Tri-stated for Bus-based
Designs
BLOCK DIAGRAM
• “Cable Safe” Operation Supported
• ESD Protection Over ± 1KV Range
• TTL Level Digital Inputs
Electrical Interfaces
Signals
High Speed Transceiver
TXD, RXD
High Speed Data
and Clock
V.10, V.11, V.35, V.28
RX1
TX1
TX2
TX3
TXC, RXC
High Speed Data
and Clock
V.10, V.11, V.35, V.28
V.10, V.11, V.35, V.28
RX2
RX3
• TTL/CMOS Digital Outputs
SCTE Signals:
DCE Transmitter,
DTE Receiver
APPLICATIONS
• Data Service Units (DSU)
• Channel Service Units (CSU)
• Routers
Handshaking/Control Transceivers
V.10, V.11, ---- , V.28
RX4
TX4
TX5
TX6
RTS, CTS
DTR, DSR
• Bridges
V.10, V.11, ---- , V.28
V.10, V.11, ---- , V.28
RX5
RX6
• Access Equipment
DCD Signals:
DCE Transmitter,
DTE Receiver
Diagnostic Transceivers
RX7
TX7
TX8
LL, RL, RI (TM)
LL, RL, RI (TM)
V.10, ---- , ---- , V.28
V.10, ---- , ---- , V.28
RX8
Mode and Configuration
Control
Switching Regulator
DC-DC Converter
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
BLOCK DIAGRAM
47 H
µ
1N5819
0.5
Ω
2.2 F
µ
-6V
+
26
7
41
56
52
42
Isense
43
G N D _ R E G
21
22
-
+
47µ
Low ESR
F
C P P
VSS
V SS
SR_OUT
C P M
Vsense
V SS_T123
47
51
V D D
16
-6V
+12V
Charge Pump
V PP
µ
10 F
+
Switching Regulator
V D D _ R E G
-
Mode Select
4
31
34
M0
M1
M2
DEC/DTE
E C
5
6
Decoder
Latch
Echo Clock
44
2 or 3 Clock Select 50
LATCH
2CK/3CK
LP
XRT4500
Loopback
18
54
55
53
24
49
500 KHz
C L O C K
45
Invert Clock
Invert Data
MODE & CONFIGURATION
CONTROL LOGIC
CLK INV
CLKFS
DT INV
O S C E N
R E G
32
- 64 KHz
Register
Mode Control
S L E W _ C N T L
Rslew
S L E W R A T E
C O N T R O L
39
Register Mode
Clock Input
R E G _ C L K
46
2
E_232H
V D D
High Speed RS232 Enable
RX1,2,3
58
60
VDD_T123
TX1D
TX1,2,3
Digital MUX 1
78
63
61
RX1A
TX1A
CM_TX1
T
T
T
RX1
TX1
79
1
0.1
TX1B
G N D
62
57
RX1B
RX1D
TX1,2,3
67
TX2D
77
RX2A
64
66
TX2A
CM_TX2
T
RX2
TX2
TX3
0.1
GND_T12
76
74
65
59
TX2B
RX2B
RX2D
TX1,2
68
TX3D
TR3A
CM_TR3
0.1
70
69
RX3
T
71 TR3B
72
G N D
73
3
RX4,5,6,7,8
RX3D
G N D
RX1,2,3
8
TX4D
TX4A
20
37
Digital MUX 2
RX4,5,6,7
V D D
RX4A
11
TX4
TX5
Filter
RX4
10
TX4B
38
40
RX4B
RX4D
15
12
TX5D
TX5A
36
RX5A
RX5
Filter
13
9
35
33
TX5B
V D D
RX5B
RX5D
TX4,5,6,7,8
29
TR6A
RX6
Filter
TX6
TX7
30
28
TR6B
TX76D
M U X
32
M U X
RX67D
27
17
Filter
RX7
TR7
48
25
TX8D
EN_OUT
RX8I
19
14
Filter
RX8
TX8O
G N D
TX8
TX4,5,6,7,8
23
75
RX8D
V.11 (RX1,2,3) Termination 80
Glitch Filter
EN_TERM
EN_FLTR
2
XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN OUT OF THE DEVICE
RX1D
V D D
G N D
M0
M1
M2
BIAS
TX4D
V D D
TX4B
TX4A
TX5A
TX5B
G N D
TX5D
VPP
TX1D
G N D
V D D
G N D
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VSS
DTINV
CKINV
O S C E N
SR_OUT
V D D
9
XRT4500
80 Lead TQFP
10
11
12
13
14
15
16
17
18
19
20
2CK/3CK
REG_CLK
EN_OUT
V D D
E-232
CLKFS
LATCH
G N D
TX8D
LP
TX8O
I_SENSE
V_SENSE
V D D
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
XRT4500CV
80 Pin TQFP
0°C to +70°C
3
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
Block Diagram........................................................................................................................................... 1
FEATURES...................................................................................................................................... 1
APPLICATIONS ................................................................................................................................ 1
Block Diagram........................................................................................................................................... 2
Pin Out of the Device ................................................................................................................................ 3
Ordering Information ................................................................................................................................. 3
TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS.......................................................................................................... 4
ELECTRICAL CHARACTERISTICS .................................................................................................... 26
TA = 25°C, VDD = 5V, VSS = -6V, VPP = 12V, Maximum Operating Frequency Unless Otherwise Specified
28
Power Supply Consumption.................................................................................................................... 29
FIGURE 1. SUPPLY CURRENT VERSUS TEMPERATURE AND SUPPLY VOLTAGE, WITHOUT LOAD OR SIGNAL IN EIA-530 (V.11)
MODE......................................................................................................................................................... 29
FIGURE 2. SUPPLY CURRENT VERSUS TEMPERATURE AND SUPPLY VOLTAGE, WITH LOAD IN EIA-530 (V.11) MODE ... 30
FIGURE 3. RS422 DRIVER TEST CIRCUIT................................................................................................................. 33
FIGURE 4. RS422 DRIVER/RECEIVER AC TEST CIRCUIT........................................................................................... 33
FIGURE 5. V.35 DRIVER/RECEIVER AC TEST CIRCUIT (TX1/RX1, TX2/RX2 ONLY) .................................................. 34
FIGURE 6. V.10/V.28 DRIVER TEST CIRCUIT ............................................................................................................ 34
FIGURE 7. V.10 (RS-423) V.28 (RS-232) RECEIVER TEST CIRCUIT ......................................................................... 34
FIGURE 8. V.11, V.35 DRIVER PROPAGATION DELAYS.............................................................................................. 34
FIGURE 9. V.11, V.35 RECEIVER PROPAGATION DELAYS.......................................................................................... 34
FIGURE 10. V.10 (RS-423) V.28 (RS-232) DRIVER PROPAGATION DELAYS ............................................................. 35
FIGURE 11. V.10, V.28 RECEIVER PROPAGATION DELAYS........................................................................................ 35
TABLE 1: RECEIVER SPECIFICATIONS ....................................................................................................................... 35
TABLE 2: TRANSMITTER SPECIFICATION.................................................................................................................... 36
1.0 SYSTEM DESCRIPTION ..................................................................................................................... 37
1.1 THE DIFFERENCE BETWEEN AN ELECTRICAL INTERFACE AND A COMMUNICATIONS INTERFACE 37
TABLE 3: DTE MODE - CONTROL PROGRAMMING FOR DRIVER AND RECEIVER MODE SELECTION .............................. 38
TABLE 4: DCE MODE - CONTROL PROGRAMMING FOR DRIVER AND RECEIVER MODE SELECTION.............................. 38
1.2 THE SYSTEM ARCHITECTURE .................................................................................................................... 39
1.2.1 THE “HIGH -SPEED TRANSCEIVER” BLOCK ......................................................................................................... 40
FIGURE 12. HIGH-SPEED TRANSCEIVER BLOCK ........................................................................................................ 40
1.2.2 THE “HANDSHAKING/CONTROL SIGNAL TRANSCEIVER” BLOCK .................................................................... 41
FIGURE 13. HANDSHAKING/CONTROL TRANSCEIVER BLOCK...................................................................................... 41
1.2.3 THE “DIAGNOSTIC OPERATION INDICATOR TRANSCEIVER” BLOCK............................................................... 42
FIGURE 14. DIAGNOSTIC OPERATION INDICATOR TRANSCEIVER BLOCK ..................................................................... 42
1.3 THE CONTROL BLOCK ................................................................................................................................. 43
FIGURE 15. DIAGRAM OF THE XRT4500 CONTROL BLOCK........................................................................................ 43
1.3.1 M[2:0] - THE (COMMUNICATION INTERFACE) MODE CONTROL SELECT PINS. ............................................... 44
TABLE 5: THE RELATIONSHIP BETWEEN THE SETTINGS FOR THE M[2:0] BIT-FIELDS AND THE CORRESPONDING COMMUNICA-
TION INTERFACE THAT IS SUPPORTED.......................................................................................................... 44
1.3.2 DCE/DTE - THE DCE/DTE MODE SELECT PIN........................................................................................................ 45
FIGURE 16. A SIMPLE ILLUSTRATION OF THE DCE/DTE INTERFACE .......................................................................... 45
1.3.3 THE LP - LOOP-BACK ENABLE/DISABLE SELECT PIN ........................................................................................ 46
FIGURE 17. ILLUSTRATION OF BOTH THE DTE AND DCE MODE XRT4500 OPERATING, WHEN THE LOOP-BACK MODE IS DIS-
ABLED........................................................................................................................................................ 46
FIGURE 18. ILLUSTRATION OF THE BEHAVIOR THE DTE MODE XRT4500, WHEN IT IS CONFIGURED TO OPERATE IN THE LOOP-
BACK MODE............................................................................................................................................... 47
FIGURE 19. ILLUSTRATION OF THE BEHAVIOR OF THE DCE MODE XRT4500, WHEN IT IS CONFIGURED TO OPERATE IN THE
LOOP-BACK MODE...................................................................................................................................... 48
1.3.4 THE EC* (ECHO CLOCK MODE - ENABLE/DISABLE SELECT INPUT PIN) .......................................................... 49
FIGURE 20. ILLUSTRATION OF A TYPICAL “3-CLOCK DCE/DTE” INTERFACE ............................................................... 49
FIGURE 21. ILLUSTRATION OF THE WAVE-FORMS OF THE SIGNALS THAT ARE TRANSPORTED ACROSS A “3-CLOCK DTE/DCE”
INTERFACE................................................................................................................................................. 50
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XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
FIGURE 22. ILLUSTRATION OF A “2-CLOCK DTE/DCE” INTERFACE ............................................................................51
FIGURE 23. THE BEHAVIOR OF THE TXC AND TXD SIGNALS AT THE DCE AND DTE SCCS, (DATA RATE = 1.0MBPS, “DCE-
TO-DTE” PROPAGATION DELAY = 160NS, “DTE-TO-DCE” PROPAGATION DELAY = 160NS)............................52
FIGURE 24. THE BEHAVIOR OF THE TXC AND TXD SIGNALS AT THE DCE AND DTE SCCS (DATA RATE = 1.544MBPS, DCE-
TO-DTE PROPAGATION DELAY = 160NS, DTE-TO-DCE PROPAGATION DELAY = 160NS) .............................52
FIGURE 25. ILLUSTRATION OF THE “ECHO-CLOCK” FEATURE WITHIN THE XRT4500...................................................53
FIGURE 26. ILLUSTRATION OF THE WAVE-FORMS, ACROSS A DCE/DTE INTERFACE, WHEN THE ECHO-CLOCK FEATURE
(WITHIN THE XRT4500) IS USED AS DEPICTED IN FIGURE 25........................................................................54
1.3.5 THE “2CK/3CK” (2-CLOCK/3-CLOCK MODE - ENABLE/DISABLE SELECT INPUT PIN)..................................... 54
FIGURE 27. ILLUSTRATION OF THE DCE/DTE INTERFACE, WITH THE DCE MODE XRT4500 OPERATING IN THE “2-CLOCK”
MODE ........................................................................................................................................................55
1.3.6 THE “CLOCK INVERSION” (CK_INV) FEATURE..................................................................................................... 55
FIGURE 28. ILLUSTRATION OF THE DCE MODE XRT4500 BEING CONFIGURED TO INVERT THE TXC SIGNAL................56
FIGURE 29. ILLUSTRATION OF THE DTE MODE XRT4500 BEING CONFIGURED TO INVERT THE TXC SIGNAL................56
FIGURE 30. ILLUSTRATION OF THE DCE MODE XRT4500, WHICH IS OPERATING IN THE “2-CLOCK” MODE, AND INVERTING
THE “TXC” SIGNAL .....................................................................................................................................57
1.3.7 THE LATCH MODE OF OPERATION ........................................................................................................................ 58
1.3.8 THE REGISTERED MODE OF OPERATION ............................................................................................................. 58
FIGURE 31. AN ILLUSTRATION OF THE EFFECTIVE INTERFACE BETWEEN THE XRT4500 AND THE SCC/MICROPROCESSOR
WHEN THE “REGISTERED” MODE IS ENABLED...............................................................................................58
FIGURE 32. AN ILLUSTRATION OF THE NECESSARY GLUE LOGIC REQUIRED TO DESIGN A FEATURE SIMILAR TO THAT OFFERED
BY THE “REGISTERED” MODE, WHEN USING A DIFFERENT MULTI-PROTOCOL SERIAL NETWORK INTERFACE IC59
1.3.9 THE INTERNAL OSCILLATOR .................................................................................................................................. 59
FIGURE 33. ILLUSTRATION OF THE INTERNAL OSCILLATORS WITHIN THE XRT4500.....................................................60
1.3.10 GLITCH FILTERS...................................................................................................................................................... 60
1.3.11 DATA INVERSION .................................................................................................................................................... 60
1.3.12 DATA INTERLUDE ................................................................................................................................................... 60
2.0 RECEIVER AND TRANSMITTER SPECIFICATIONS .........................................................................60
3.0 V.10\V.28 OUTPUT PULSE RISE AND FALL TIME CONTROL .........................................................60
FIGURE 34. V.10 RISE/FALL TIME AS A FUNCTION OF RSLEW .................................................................................61
FIGURE 35. V.28 SLEW RATE OVER ± 3 V OUTPUT RANGE WITH 3 KW IN PARALLEL WITH 2500 PF LOAD AS A FUNCTION
OF RSLEW................................................................................................................................................61
4.0 THE HIGH-SPEED RS232 MODE ........................................................................................................61
5.0 INTERNAL CABLE TERMINATIONS ..................................................................................................62
6.0 OPERATIONAL SCENARIOS ..............................................................................................................62
7.0 APPLICATIONS INFORMATION .........................................................................................................62
FIGURE 36. RECEIVER TERMINATION........................................................................................................................63
TABLE 6: RECEIVER SWITCHES ................................................................................................................................63
FIGURE 37. TRANSMITTER TERMINATION ..................................................................................................................64
TABLE 7: TRANSMITTER SWITCHES...........................................................................................................................64
FIGURE 38. TYPICAL V.10 OR V.28 INTERFACE (R1 = 10 KW IN V.10 AND 5 KW IN V.28) ........................................64
FIGURE 39. TYPICAL V.11 INTERFACE (TERMINATION RESISTOR, R1, IS OPTIONAL.)..................................................64
FIGURE 40. TYPICAL V.35 INTERFACE ......................................................................................................................65
TABLE 8: MUX1 CONNECTION TABLE.......................................................................................................................65
TABLE 9: MUX2 CONNECTION TABLE (RX4-RX7, TX4-TX7), OUTPUT VERSUS INPUT ..............................................67
FIGURE 41. SCENARIO A, MUX2, (DCE/DTE = 0, LP = 0).......................................................................................68
FIGURE 42. SCENARIO B, MUX2, (DCE/DTE = 0, LP = 1), LOOP BACK NOT ENABLED .............................................69
FIGURE 43. SCENARIO C, MUX2, (DCE/DTE = 1, LP = 0).......................................................................................70
FIGURE 44. SCENARIO D, MUX2, (DCE/DTE = 1, LP = 1), LOOP BACK NOT ENABLED.............................................71
FIGURE 45. SERIAL INTERFACE SIGNALS AND CONNECTOR PIN-OUT .........................................................................72
FIGURE 46. SERIAL INTERFACE CONNECTOR DRAWINGS...........................................................................................73
FIGURE 47. EIA-530 CONNECTION DIAGRAM FOR XRT4500 ....................................................................................74
FIGURE 48. RS-232 CONNECTION DIAGRAM FOR XRT4500 .....................................................................................75
Scenarios 1 & 2 Normal: ‘3-clock’ DCE/DTE Interface Operation...........................................................76
Input Pin Settings ....................................................................................................................................76
Scenario 3 &2 DTE Loop-Back Mode......................................................................................................77
Input Pin Settings ....................................................................................................................................77
Scenario 4 ...............................................................................................................................................78
Comments: DCE Loop-Back Mode .........................................................................................................78
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
Input Pin Settings.................................................................................................................................... 78
Scenario 5 & 2......................................................................................................................................... 79
Comments: TXC Clock Inversion in DTE Mode...................................................................................... 79
Input Pin Settings.................................................................................................................................... 79
Scenario 6............................................................................................................................................... 80
Comments: TXC Clock Inversion in DCE Mode...................................................................................... 80
Input Pin Settings.................................................................................................................................... 80
Scenario 7 & 2......................................................................................................................................... 81
Input Pin Settings.................................................................................................................................... 81
Scenario 8............................................................................................................................................... 82
Input Pin Settings.................................................................................................................................... 82
Scenario 9 & 10....................................................................................................................................... 83
Comments: 2 Clock Mode Operation Within the ‘DCE Mode’. This feature is Useful For Applications .. 83
That Interface to a Device Which Does Not Supply ‘SCTE’ Clock Signal............................................... 83
Input Pin Settings.................................................................................................................................... 83
Scenario 12............................................................................................................................................. 84
Input Pin Settings.................................................................................................................................... 84
Scenario 13 & 10..................................................................................................................................... 85
Input Pin Settings.................................................................................................................................... 85
Scenario 14............................................................................................................................................. 86
Comments: TXC Clock Inversion and 2 Clock Mode Operation Within The DCE Mode. This Scenario Can
be Used to Resolve the 2 Clock Propagation Delay Timing Violation Issue........................................... 86
Input Pin Settings.................................................................................................................................... 86
Scenario 16............................................................................................................................................. 87
Input Pin Settings.................................................................................................................................... 87
Scenario 17 & 18..................................................................................................................................... 88
Comments: X:21 Mode Operation........................................................................................................... 88
Input Pin Settings (1 clock mode) ........................................................................................................... 88
Scenario 20............................................................................................................................................. 89
Input Pin Settings (1 clock mode) ........................................................................................................... 89
Scenario 21............................................................................................................................................. 90
Input Pin Settings (1 clock mode) ........................................................................................................... 90
Scenario 22............................................................................................................................................. 91
Input Pin Settings (1 clock mode) ........................................................................................................... 91
Scenario 23............................................................................................................................................. 92
Input Pin Settings (1 clock mode) ........................................................................................................... 92
Scenario 48............................................................................................................................................. 93
Input Pin Settings (1 clock mode) ........................................................................................................... 93
REVISIONS ................................................................................................................................... 96
III
XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
1
RX1D
D_RXD
D_TXD
O
Receiver 1 Digital Output – Digital Data Output to terminal
equipment
This output pin is the digital (TTL/CMOS level) representation of
the line signal that has been received via the RX1A (pin 78) and
RX1B (pin 79) input pins.
The exact role that this pin plays depends upon whether the
XRT4500 is operating in the DCE or DTE Mode.
DCE Mode – TXD Digital Output Signal
This output pin functions as the TXD Digital Output signal (which
should be input to the Terminal Equipment).
DTE Mode – RXD Digital Output Signal
This output pin functions as the RXD Digital Output signal (which
should be input to the Terminal Equipment).
2
3
4
VDD
GND
M0
Analog VDD for Receiver 1, 2, 3
I
I
Analog GND for Receiver 1, 2, 3 and Transmitter 3
Mode Control – Mode Select Input 0
This input pin, along with M1 and M2 are used to configure the
XRT4500 to operate in the desired “Communication Interface”
Mode. Table 3 and Table 4 present the relationship between
the states of the M2, M1 and M0 input pins and the correspond-
ing communication interface modes selected.
This input pin (along with M1 and M2) is internally latched into
the XRT4500, upon the rising edge of the “LATCH” signal. At this
point, changes in this input pin will not effect the “internally
latched” state of this pin.
This input pin contains an Internal 20KΩ pull-up to VDD.
5
M1
I
Mode Control – Mode Select Input 1
This input pin, along with M0 and M2 are used to configure the
XRT4500 to operate in the desired “Communication Interface”
Mode. Table 3 and Table 4 present the relationship between the
states of the M2, M1 and M0 input pins and the corresponding
communication interface modes selected.
This input pin (along with M0 and M2) is internally latched into the
XRT4500 device, upon the rising edge of the “LATCH” signal. At
this point, changes in this input pin will not effect the “internally
latched” state of this pin.
This input pin contains an Internal 20KΩ pull-up to VDD.
4
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE MODE
DCE
TYPE FUNCTION
6
M2
I
Mode Control – Mode Select Input 2
This input pin, along with M0 and M1 are used to configure the
XRT4500 to operate in the desired “Communication Interface”
Mode. Table 3 and Table 4 present the relationship between
the states of the M2, M1 and M0 input pins and the correspond-
ing communication interface modes selected.
This input pin (along with M0 and M1) is internally latched into
the XRT4500 device, upon the rising edge of the “LATCH” sig-
nal. At this point, changes in this input pin will not effect the
“internally latched” state of this pin.
This input pin contains an Internal 20KΩ pull-up to VDD.
7
8
VSS
-6V Power: This supply voltage is internally generated by the
Switching Regulator Circuit within the XRT4500. The -6V is used
by TX 4, 5, 6, 7, 8.
TX4D
D_RTS
D_CTS
I
Transmitter 4 – Digital Data Input from Terminal Equipment
The XRT4500 accepts binary TTL Level data stream, via this
input pin, converts it into either a V.10, V.11 or V.28 format and
outputs it via the TX4A and TX4B output pins.
The exact role that this pin plays depends upon whether the
XRT4500 is operating in the DCE or DTE Mode.
DCE Mode – CTS (Clear to Send) Input
If the XRT4500 is operating in the DCE Mode, then this input pin
should be tied to the CTS Output pin of the Terminal Equipment.
DTE Mode – RTS (Request to Send) Input
If the XRT4500 is operating in the DTE Mode, then this input pin
should be tied to the RTS output pin of the Terminal Equipment.
9
VDD
Analog VDD – For Transmitters 4, 5, 6, 7 and 8
10
TX4B
RTSB
CTSB
O
Transmitter 4 – Positive Data Differential Output to Line
The XRT4500 accepts a TTL binary data stream from the Termi-
nal Equipment via the TX4D (pin 8) input pin. The XRT4500 will
convert this data into either the V.10, V.11 or V.28 modes, and
will output it via this pin and TX4A (pin 11).
The exact role that this pin plays depends upon whether the
XRT4500 is operating in the DTE or DCE mode.
DTE Mode – Positive Polarity portion of RTS Line Signal.
DCE Mode – Positive Polarity portion of CTS Line Signal.
Note: This output pin is not used if the XRT4500 has been con-
figured to operate in either the V.28/EIA-232 or V.10 Modes.
5
XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
11
TX4A
RTSA
CTSA
O
Transmitter 4 – Negative Data Differential Output to Line
The XRT4500 accepts a TTL binary data stream from the Terminal
Equipment via the TX4D (pin 8) input pin. The XRT4500 will convert
this data into either the V.10, V.11 or V.28 modes, and will output it
via this pin and TX4B (pin 10). The exact function of this output pin
depends upon whether the XRT4500 device is operating in the
DTE or DCE mode.
DTE Mode – Negative Polarity portion of the RTS Line Signal.
DCE Mode – Negative Polarity portion of the CTS Line Signal.
Note: If the XRT4500 has been configured to operate in either
the V.28/EIA-232 or V.10 Modes, then all of the data will be out-
put (to the line) in a single-rail manner via this output pin.
12
TX5A
DTRA
DSRA
O
Transmitter 5 – Negative Data Differential Output to Line
The XRT4500 accepts a TTL binary data stream via the TX5D (pin
15) input pin. The XRT4500 will convert this data into either the
V.10, V.11 or V.28 modes, and will output it via this pin and TX5B
(pin 13). The exact function of this output pin depends upon
whether the XRT4500 device is operating in the DTE or DCE mode.
DTE Mode – Negative Polarity portion of the DTR Line Signal.
Transmitter 5 accepts a TTL level binary data stream (as the
Data Terminal Read – DTR) from the terminal equipment.
DCE Mode – Negative Polarity portion of the DSR Line Signal.
Note: If the XRT4500 has been configured to operate in either
the V.28/EIA-232 or V.10 Modes, then all of the data will be out-
put (to the line) in a single-rail manner via this output pin.
13
TX5B
DTRB
DSRB
O
Transmitter 5 – Positive Data Differential Output to Line
The XRT4500 accepts a TTL binary data stream via the TX5D (pin
15) input pin. The XRT4500 will convert this data into either the
V.10, V.11 or V.28 modes, and will output it via this pin and TX5A
(pin 12). The exact function of this output pin depends upon
whether the XRT4500 device is operating in the DTE or DCE mode.
DTE Mode – Positive Polarity portion of DTR Line signal.
DCE Mode – Positive Polarity portion of DSR Line signal.
Note: This output pin is not used if the XRT4500 has been con-
figured to operate in either the V.28/EIA-232 or V.10 Modes.
14
GND
Analog GND – For Transmitters 4, 5, 6, 7, and 8.
6
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
15
TX5D
D_DTR
D_DSR
I
Transmitter 5 – Digital Data Input from Terminal Equipment
This input pin accepts a TTL level binary data stream, from the
local terminal equipment, and outputs it, in either a V.10, V.11 or
V.28 manner, via the TX5A (pin 12) and TX5B (pin 13) output
pins. The exact role that this input pin plays depends upon
whether the XRT4500 is operating in the DTE or DCE Modes.
DTE Mode – Data Terminal Ready (DTR) Input Pin
If the XRT4500 is operating in the DTE mode, then this input pin
should be tied to the DTR output pin of the terminal equipment.
DCE Mode – Data Set Ready (DSR) Input Pin
If the XRT4500 is operating in the DCE mode, then this input pin
should be tied to the DSR output pin of the terminal equipment.
Note: If the XRT4500 has been configured to operate in the
“Registered” Mode, then data applied to this input pin will be
latched (into the XRT4500) upon the rising edge of the
REG_CLK input signal.
16
17
VPP
+12V Power: This supply voltage is internally generated by the
Charge Pump Circuit within the XRT4500 device. If +12V is
available, then the external components can be eliminated.
TX8D
D_RL
D_RI
I
Transmitter 8 – Digital Data Input from Terminal Equipment
This input accepts a TTL level binary data stream, from the local
terminal equipment, and outputs it, in either a V.10 or V.28 man-
ner via the TX8O (pin 19) output pin.
DCE Mode – Ring Indicator (or Test Mode) Input Pin
If the XRT4500 has been configured to operate in the
DCE Mode – This input pin should be connected to either the
“RI” (Ring Indicator) or the “TM” (Test Mode) indicator output pin
of the Terminal Equipment.
DTE Mode – Remote Loop-back Indicator Input Pin
If the XRT4500 has been configured to operate in the
DTE Mode – This input pin should be connected to the “RL”
(Remote Loop-back) indicator output pin of the Terminal Equip-
ment.
Note: If the XRT4500 has been configured to operate in the
“Registered” Mode, then data applied to this input pin will be
latched (into the XRT4500) upon the rising edge of the
REG_CLK input signal.
7
XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
18
LP
I
Loopback Command Input Pin – Active Low:
This active-low input pin permits the user to configure the
XRT4500 into a “Loop-Back” Mode. The exact loop-back will
depend upon whether the XRT4500 is operating in the DTE or
DCE Modes.
Setting this input pin to “LOW” enables the Loop-back Operation.
Setting this input pin to “HIGH” disables the Loop-back Operation.
This input pin contains an Internal 20KΩ pull-up to VDD.
19
TX8O
RLA
RIA
O
Transmitter 8 – Single Ended Data Output to Line
The XRT4500 accepts a TTL level binary data stream, from the
local terminal equipment via the “TX8D” input pin (pin 17), and
outputs it, in either a V.10 or V.28 manner via this output pin. The
exact role that this output pin plays depends upon whether the
XRT4500 is operating in the DTE or DCE Modes.
If the XRT4500 is configured to operate in the DCE Mode:
This output pin will typically drive the state of either the “RI”
(Ring Indicator) or “TM” (Test Mode) signals to the Remote
Terminal Equipment.
If the XRT4500 is configured to operate in the DTE Mode:
This output pin will typically drive the state of the “RL” (Remote
Loop-back) signal to the Remote Terminal Equipment.
20
21
VDD
CPP
Analog VDD – For Receivers 4, 5, 6, 7 and 8.
Charge Pump Capacitor Pin: A 2.2µF tantalum capacitor must
be connected between pin 21 and pin 22.
22
CPM
Charge Pump Capacitor Pin: A 2.2µF tantalum capacitor must
be connected between pin 21 and pin 22.
NOTE: Signal names beginning with D_ are digital signals.
NOTE: Signal names ending with B and A are the positive
and negative polarities of differential signals respectively.
8
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
23
RX8D
D_RI
D_RL
O
Receiver 8 – Digital Data Output to Terminal Equipment
The XRT4500 receives a line signal (in either the V.10 or V.28
manner) via the RX8I input pin (Pin 25). The XRT4500 then con-
verts this data into a digital format (e.g., a CMOS level binary
data stream) and outputs it via this pin. The exact functionality of
this output pin depends upon whether the XRT4500 is operating
in the DCE or DTE Modes.
DCE Mode – Remote Loop-back Indicator Output
If the XRT4500 has been configured to operate in the DCE
Mode – This output pin should be connected to the “RL” (Remote
Loop-back) indicator input pin (of the Terminal Equipment).
DTE Mode – Ring Indicator (or Test Mode Indicator) Output
If the XRT4500 has been configured to operate in the DTE
Mode – This output pin should be connected to either the “RI”
(Ring Indicator) or “TM” (Test Mode) input pin of the Terminal
Equipment.
Notes: This output pin is tri-stated if the EN_OUT* input pin (pin
48) is “HIGH”. If the XRT4500 has been configured to operate in
the “Registered” Mode, then data will be outputted via this pin,
upon the rising edge of the REG_CLK clock signal.
24
REG
I
Register Mode Control Select Input Pin:
This input pin permits the user to configure the XRT4500 to
operate in either the “Registered” Mode or in the “non-Regis-
tered” Mode. If the XRT4500 has been configured to operate in
the “Registered” Mode, then the following will happen.
• Data at the “TX5D” and “TX8D” input pins (Pins 15 & 17) will
be latched into the XRT4500 circuitry upon the rising edge of
the clock signal applied at the “REG_CLK” input pin.
• Data will be output via the “RX5D” and “RX8D” pins, upon the
rising edge of the clock signal applied at the “REG_CLK” input
pin.
If the XRT4500 has been configured to operate in the “Non-Reg-
istered” Mode, then the “REG_CLK” clock signal will have no
effect on the processing of signals via the “TX5D”, “TX8D”,
“RX5D” and “RX8D” pins.
Setting the “REG” input to “HIGH” configures the XRT4500 to
operate in the “Registered” Mode.
Setting the “REG” input to “LOW” configures the XRT4500 to
operate in the “Non-Registered” Mode.
This pin contains an internal 20KΩ pull-down to ground.
9
XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
25
RX8I
RIA
RLA
I
Receiver 8 – Line Input Pin:
This input pin accepts either a V.10 or V.28 type signal from the
line. Receiver 8 will then convert this signal into a “CMOS” level
(digital) signal and output this signal to the Terminal Equipment
via the RX8D output pin (Pin 23). The exact function of this out-
put pin depends upon whether the XRT4500 device is operating
in the DTE or DCE mode.
DTE Mode – The RI line signal
DCE Mode – The RL line signal
Notes:
1. For some DTE applications, this input pin would accept
the “RI” (Ring Indicator) line signal (in either the V.10 or
V.28 format) form the DCE Terminal Equipment.
2. For some DCE applications, this input pin would accept the
“RL” (Remote Loop-back”) line signal (in either the V.10 or
the V.28 format) from the DTE Terminal Equipment.
26
27
VSS
TR7
-6V Power: This supply voltage is internally generated by the
Switching Regulator Circuit within the XRT4500. The -6V is used
by receivers 4, 5, 6, 7 and 8. If a -6V supply is available, then the
external components can be eliminated.
LLA
LLA
I/0
Transceiver # 7 I/O Pins
The exact function of this pin depends upon whether the
XRT4500 is operating in the DCE or DTE Modes.
DTE Mode – Transmitter 7 – Single Ended Data Output to Line
Transceiver 7 accepts a CMOS level signal via the “TX76D” input
pin (pin 28). This digital data is converted into either a V.10 or
V.28 electrical signal; which is then output (via this pin), on the
line to the Remote Terminal Equipment.
DCE Mode – Receiver 7 – Single Ended Data Input from Line
This input pin accepts the line signal, from the Remote Terminal
Equipment, in a “single-ended” manner. This line signal is con-
verted into a CMOS level signal and is output (to the local Termi-
nal Equipment) via the “RX67D” output pin (Pin 32).
28
TX76D
D_LL
D_DCD
I
Digital Input – Refer to Mode Control Tables, Table 3 & Table 4 .
10
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
29
TR6A
DCDA
DCDA
I/O
Transceiver # 6 Line Signal I/O Pin:
The exact function of this pin depends upon whether the
XRT4500 has been configured to operate in the DCE or DTE
Mode.
DTE Mode: Negative Polarity Input of DCD (Data Carrier
Detect) Signal:
This input pin (along with TR6B, pin 30) accepts the line signal,
from the remote terminal equipment, in either a Single-Ended or
Differential manner. This line signal is converted to CMOS level
signals and is outputted (to the local terminal equipment) via the
RX67D output pin (Pin 32).
DCE Mode: Negative Polarity Output Signal (of DCD-Data
Carrier Detect) to the Line:
Transceiver 6 accepts TTL level binary data stream, via the
“TX67D” (pin 28) input pin. This output pin, along with “TR6B”
(pin 30) will output this data to the Remote Terminal Equipment).
via an Analog Line Signal.
30
TR6B
DCDB
DCDB
I/O
Transceiver #6 Line Signal I/O Pin
The exact function of this pin, depends upon whether the
XRT4500 has been configured to operate in the DCE or DTE
Mode.
DTE Mode: Receiver 6 – Positive Polarity Input of DCD (Data
Carrier Detect) Signal:
This input pin (along with TR6A, pin 29) accepts the line signal,
from the remote terminal equipment, in a Differential manner.
This line is converted to CMOS signal levels and is output (to the
local terminal equipment) via the RX67D output pin (Pin 32).
DCE Mode: Transmitter 6 – Positive Polarity Output of DCD
(Data Carrier Data Signal) Pin:
Transceiver 6 accepts a TTL level binary data stream, via the
TX67D (pin 28) input pin. This output pin (along with TR6A, pin
29) will output this data (to the remote terminal equipment) via
an Analog line signal.
NOTE: This I/O pin is not used if the XRT4500 has been config-
ured to operate in the V.28/EIA-232 Communications Interface
Mode.
11
XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
31
DCE/DTE
LOW
HIGH
I
DCE/DTE Mode Select:
This input pin permits the user to configure the XRT4500 to
operate in either the DCE Mode or in the DTE Mode.
Logic 0: DTE Mode Operation
When the XRT4500 is configured to operate in the “DTE” Mode,
then “Transceiver # 3” will be configured to function as a
Receiver.
Logic 1: DCE Mode Operation
When the XRT4500 is configured to operate in the “DCE” Mode,
then “Transceiver # 3” will be configured to function as a Trans-
mitter. This input pin contains an internal 20KΩ pull-up to VDD.
32
RX67D
D_DCD
D_LL
O
Transceiver 6/7 Digital Output Pin:
The exact function of this pin depends upon whether the
XRT4500 has been configured to operate in the DCE or DTE
Mode.
DTE Mode – Data Carrier Detect (DCD) Output Pin
When the XRT4500 is operating in the DTE Mode, this trans-
ceiver functions as a “line receiver”. This line receiver accepts
either a V.10, V.28 or V.11 line signal via the TR6A and TR6B
pins (pins 29 and 30) and converts this line signal into a CMOS
level binary data stream. This binary data stream is output via
this pin. For DTE applications, this output pin should be con-
nected to the “DCD” input pin of the “Terminal Equipment”.
DCE Mode – Local Loop-back (LL) Indicator Output Pin
When the XRT4500 is operating in the DCE Mode, this trans-
ceiver functions as a “line receiver”. This line receiver accepts
either a V.10, or V.28 line signal via the TR7 input pin (pin 27)
and converts this line signal into a CMOS level binary data
stream. This binary data stream is output via this pin. For DCE
applications, this input pin should be connected to the “LL” input
pin of the “Terminal Equipment”.
NOTE: Signal names beginning with D_ are digital signals.
NOTE: Signal names ending with B and A are the positive
and negative polarities of differential signals respectively.
12
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
33
RX5D
D_DSR
D_DTR
O
Receiver 5 – Digital Data Output to Terminal Equipment
The XRT4500 accepts a line signal (in either the V.10, V.11 or
V.28 manner) via the RX5A and RX5B input pins (Pins 35 & 36).
The XRT4500 then converts this data into digital format (e.g., a
CMOS level binary data stream) and outputs it to the Terminal
Equipment via this pin.
The exact role that this pin plays depends upon whether the
XRT4500 device is operating in the DCE or DTE modes.
DTE Mode – Data Set Ready (DSR) Output Pin
For DTE applications, this output pin should be connected to the
“DSR” input of the Terminal Equipment.
DCE Mode – Data Terminal Ready (DTR) Output Pin
For DCE applications, this output pin should be connected to the
“DTR” input pin of the Terminal Equipment.
Note:
1. This output pin is tri-stated if the EN_OUT input pin (pin 48)
is “HIGH”.
2. If the XRT4500 has been configured to operate in the
“Registered” Mode, then data will be outputted via this pin
upon the rising edge of the “REG_CLK” clock signal.
34
EC
I
Echo Clock Mode Select Input Pin
This input pin permits the user to enable or disable the “Echo-
Clock” Mode feature within the XRT4500 device. If the user con-
figures the XRT4500 to operate in the “Echo-Clock” Mode, then
the RX3D output pin (Pin 73) will be internally looped into the
“TX2D” input pin (Pin 67).
Setting this input pin “LOW” enables the “Echo-Clock” Mode.
Setting this input pin “HIGH” disables the “Echo-Clock” Mode.
Note: The “Echo-Clock” Mode feature is only available if the
XRT4500 is operating in the DTE Mode.
This input pin contains an internal 20KΩ pull-up to VDD.
NOTE: Signal names beginning with D_ are digital signals.
NOTE: Signal names ending with B and A are the positive
and negative polarities of differential signals respectively.
13
XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
35
RX5B
DSRB
DTRB
I
Receiver 5 – Positive Data Differential Input from Line
The XRT4500 will accept either a V.10, V.11 or V.28 type signal via
this input pin, along with RX5A (Pin 36) and will generate a result-
ing CMOS level binary data stream, via the RX5D (Pin 33) output
pin. The exact function of this input pin depends upon whether the
XRT4500 device is operating in the DTE or DCE mode.
DTE Mode – Positive polarity portion of the DSR line signal.
DCE Mode – Positive polarity portion of the DTR line signal.
Note: This output pin is not used if the XRT4500 has been con-
figured to operate in either the V.28/EIA-232 or V.10 Modes.
36
RX5A
DSRA
DTRA
I
Receiver 5 – Negative Data Differential Input from Line
The XRT4500 will accept either a V.10, V.11 or V.28 type signal
via this input pin, along with RX5B (pin 35) and will generate a
resulting CMOS level binary data stream, via the RX5D (Pin 33)
output pin. The exact function of this input pin depends upon
whether the XRT4500 device is operating in the DTE or DCE
mode.
DTE Mode – Negative polarity portion of the DSR line signal.
DCE Mode – Negative polarity portion of the DTR line signal.
Note: If the XRT4500 has been configured to operate in either
the V.28/EIA-232 or V.10 Modes, then all of the data will be out-
put (to the line) in a single-rail manner via this output pin.
37
RX4A
CTSA
RTSA
I
Receiver 4 – Negative Data Differential Input from Line
The XRT4500 will accept either a V.10, V.11 or V.28 type signal
via this input pin, along with RX4B (pin 38) and will generate a
resulting CMOS level binary data stream, via the RX4D output
pin (Pin 40). The exact function of this input pin depends upon
whether the XRT4500 device is operating in the DTE or DCE
mode.
Note: If the XRT4500 has been configured to operate in either
the V.28/EIA-232 or V.10 Modes, then all of the data will be out-
put (to the line) in a single-rail manner via this output pin.
38
RX4B
CTSB
RTSB
I
Receiver 4 – Positive Data Differential Input from Line
The XRT4500 will accept either a V.10, V.11 or V.28 type signal
via this input pin, along with RX4A (pin 37) and will generate a
resulting CMOS level binary data stream, via the RX4D output
pin (Pin 40). The exact function of this input pin depends upon
whether the XRT4500 device is operating in the DTE or DCE
mode.
NOTE: This output pin is not used if the XRT4500 has been con-
figured to operate in either the V.28/EIA-232 or V.10 Modes.
NOTE: Signal names beginning with D_ are digital signals.
NOTE: Signal names ending with B and A are the positive
and negative polarities of differential signals respectively.
14
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE MODE
DCE
TYPE FUNCTION
39
SLEW_CNTL
O
V.28/V.10 Slew-Rate Control Pin – This pin permits the user to
specify the slew rate of the V.10 or V.28 output driver. The user
accompanies this by connecting a resistor (of a specific value)
between this pin and ground.
Figure 34 presents a plot which depicts the relationship
between the ‘Rise/Fall Time’ of a V.10 output signal (from the
XRT4500) and the value of this resistor.
Figure 35 presents a plot which depicts the relationship
between the slew-rate (expressed in terms of V/µs) of a V.28 out-
put signal (from the XRT4500) and the value of this resistor.
40
RX4D
D_CTS
D_RTS
O
Receiver 4 – Digital Data Output to Terminal Equipment
This output pin is the digital (CMOS level) representation of the
line signal that is applied to the RX4A (pin 37) and RX4B (pin 38)
input pins.
The exact role that this pin plays depends upon whether the
XRT4500 is operating in the DCE or DTE Mode.
DCE Mode – CTS (Clear to Send) Output Signal
For DCE Mode applications, this output pin should be connected
to the “CTS” input pin of the Terminal Equipment.
DTE Mode – RTS (Request to Send) Output Signal
For DTE Mode applications, this output pin should be connected
to the “RTS” input pin of the Terminal Equipment.
41
42
43
44
Vsense
Isense
I
I
Switching Regulator – Voltage sense input
Switching Regulator – Current sense input
Switching Regulator Ground
GND_REG
LATCH
I
Mode Control Input Latch Enable – Logic 0:
This input pin permits the user to latch the states of the Mode
Control Input pins (4, 5, and 6) (M0, M1, and M2) into the
XRT4500 circuitry. This feature frees up the signals (driving the
Mode Control Input pins) for other purposes.
Driving this input, from “low” to “high” latches the contents of the
Mode Control pins of the XRT4500 (into the XRT4500 circuitry).
For the duration that the LATCH input pin is “high”, the user can
change the state of the signals controller the M0, M1 and M2
input pins, without effecting the operation of the XRT4500.
45
CLKFS
O
Internally Generated 500kHz Clock – This clock signal is inter-
nally used to drive both the switching regulator and the digital
‘Glitch’ filters. The user is advised to leave this pin floating.
NOTE: Signal names beginning with D_ are digital signals.
NOTE: Signal names ending with B and A are the positive
and negative polarities of differential signals respectively.
15
XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
46
E_232H
I
High Speed RS-232 Enable – Logic 0 enables high speed RS-
232 mode (drives 3KΩ in parallel with 1000pF at 256 KHz).
Internal 20KΩ pull-up to VDD.
This input pin permits the user to either enable or disable the
‘High-Speed RS-232 Driver’ feature. The non high speed mode
provides a 120 Kbps clock rate.
Note: This pin setting applies to all ‘RS-232/V.28 Drivers’ within
the XRT4500.
47
48
VDD
Analog VDD for the Internal Switching Regulator
EN_OUT
I
Output Enable Pin for Receiver 5 and 8
This active-low output pin permits the user to tri-state the
“RX5D” and “RX8D” output pins (Pins 23 & 33).
Setting this input pin “low” causes the XRT4500 to tri-state the
“RX5D” and “RX8D” output pins. Conversely, setting this input
pin “high” enables the “RX5D” and the “RX8D” output drivers for
signal transmission to the local Terminal Equipment.
This input pin contains an internal 20kΩ pull-down resistor to
ground.
49
REG_CLK
I
Register Mode Clock Input Signal:
If the XRT4500 has been configured to operate in the “Regis-
tered” Mode, then a rising clock edge at this input causes the
XRT4500 to do the following.
•
•
Data at the TX5D and TX8D input pins (Pins 15 & 17) will be
latched into the XRT4500 circuitry.
Data will be outputted via the RX5D and RX8D pins (Pins 23
& 33).
This input pin has no function when the XRT4500 is operating in
the “Non-Registered” Mode. The user configures the XRT4500
to operate in the “Registered” Mode, by pulling the “REG” input
pin to VDD
.
This input pin contains an internal 20kΩ pull-up to VDD
.
NOTE: Signal names beginning with D_ are digital signals.
NOTE: Signal names ending with B and A are the positive
and negative polarities of differential signals respectively.
16
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
50
2CK/3CK
I
2 or 3 Clock Select Input Pin
This input pin permits the XRT4500 to operate in either the “2
Clock” or “3 Clock” Mode. If the XRT4500 is configured to oper-
ate in the ‘2-Clock’ mode, then the XRT4500 will synthesize the
‘RX2D’ Clock signal, from the clock signal applied at the ‘TX3D’
input pin. Conversely, if the XRT4500 is configured to operate in
the ‘3 Clock’ Mode, then the XRT4500 will synthesize the ‘RX2D’
Clock signal from the live signal received via ‘RX2A’ and ‘RX2B’
input pin. Setting this input pin “high” configures the XRT4500 to
operate in the “2 Clock” Mode. Conversely, setting this input pin
“low” configures the XRT4500 to operate in the “3 Clock” Mode.
Note:
1. This input pin is ignored if the XRT4500 is configured to
support the X.21 Communications Interface.
Logic Don’t Care: 1 Clock When in the X.21 Mode (M2, M1, M0 = 011)
≠ X.21 (M2, M1, M0 ≠ 011)
≠ X.21 (M2, M1, M0 ≠ 011)
Logic 0: 3 Clocks When Mode
Logic 1: 2 Clocks When Mode
NOTE:
2. This input pin is ignored if the XRT4500 is configured to
operate in the DTE Mode.
This input pin contains an internal 20kΩ pull-up to VDD
.
51
52
VDD_REG
SR_OUT
Analog VDD – Charge pump and switching regulator output
drivers
O
Switching Regulator – Inductor driver output
NOTE: Signal names beginning with D_ are digital signals.
NOTE: Signal names ending with B and A are the positive
and negative polarities of differential signals respectively.
17
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
53
OSCEN
I
Test Oscillator Enable – Active Low;
This active-low input pin permits the user to enable or disable the
“Internal Oscillator” within the XRT4500. If the user enables this fea-
ture then the XRT4500 will begin generating a clock signal via both
the RX2D and RX3D output pins. The frequency of this clock signal
ranges between 32kHz and 64kHz.
This clock signal can be used to support “Stand-Alone DTE Diag-
nostic” Testing.
Setting this input to “0” enables the “Internal Oscillator”.
Setting this input to “1” disables the “Internal Oscillator”.
Note: The “Internal Oscillator” is only available if the XRT4500 is
operating in the DTE Mode.
If LP = “0” The Clock Signal (32 - 64kHz) is available on Rx3D.
If LP = “0” and EC = “0” the clock signal is available on RX2D.
Ω pull-up to V
.
NOTE: This input pin contains an internal 20k
DD
54
CLKINV
I
Invert Clock Input Pin – This ‘Active -Low’ input pin permits the
user to either enable or disable the ‘Clock/Inversion’ feature. The
exact manifestation of the ‘Clock Inversion’ feature depends upon
whether the XRT4500 is operating in the ‘DCE’ or ‘DTE’ Mode.
If the XRT4500 is operating in the DTE Mode, then the RX3D output
signal (which is receiving the TXC signal) will be inverted before it is
outputted to the terminal equipment.
If the XRT4500 is operating in the DCE Mode, then the TX3D input
signal (which is transmitting the TXC signal) will be inverted before it
converted into the analog format and is output to the line.
Setting this input pin ‘Low’ enables the ‘Clock Inversion’ feature.
Conversely, setting this input pin ‘High’ disables this feature.
Ω pull-up to V
.
NOTE: This input pin contains an internal 20k
DD
55
DTINV
I
Invert Data – Active Low; Logic 0: Data Inverted.
Ω pull-up V
Logic 1: Data not Inverted. Internal 20K
.
DD
56 VSS_T123
-6V Power Supply Signal: This supply voltage is internally gener-
ated by the Switching Regulator Circuit within the XRT4500.
57
GND
Digital Ground: for transmitters 1, 2, and 3
Analog VDD: for transmitters 1, 2, and 3
Analog Ground: Transmitters 1 and 2
58 VDD_T123
59
GND_T12
18
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
60
TX1D
D_TXD
D_RXD
I
Transmitter 1 – Digital Data Input from Terminal Equipment.
The exact role that this input pin plays depends upon whether
the XRT4500 is operating in the DTE or DCE Modes.
DTE Mode – TXD (Transmit Data) Input:
The DTE Terminal Equipment is expected to apply the TXD
(Transmit Data) to this input pin.
The XRT4500 will convert this binary data stream into either the
V.35, V.11, or V.28 format and will output this data via the TX1A
and TX1B output pin.
DCE Mode – RXD (Receive Data) Input:
The DCE Terminal Equipment is expected to apply the RXD
(Receive Data) to this input pin.
The XRT4500 will convert this binary data stream into either the
V.35, V.11 or V.28 format and will output this data via the TX1A
and TX1B output pins.
61
62
CM_TX1
TX1B
O
O
AC GND- Transmitter 1 Output Termination center tap in V.35
Mode. Connect a 0.1µF capacitor to ground.
TXDB
RXDB
Transmitter 1 – Positive Data Differential Output to line.
The exact function of this output pin depends upon whether the
XRT4500 is operating in the DCE or DTE Modes.
DTE Mode: Transmit Data (TXD) – Positive Polarity Output
Line Signal
Transmitter 1 accepts a TTL Level binary data stream (as the
“Transmit Data” – TXD) from the DTE Terminal Equipment.
Transmitter 1 converts this digital data into any of the following
electrical formats: V.10, V.11, V.28 and V.35, prior to transmis-
sion to the line.
If this data is being converted into either the V.11 or V.35 format,
then this pin outputs the positive-polarity portion of the “TXD”
data to the line. If this data is being converted into either the V.10
or V.28 formats, then this pin is inactive.
DCE Mode: Receive Data (RXD) – Positive Polarity Output
Line Signal
Transmitter 1 accepts a CMOS (or TTL) level signal binary data
stream (as the “Receive Data” – RXD) from the DCE Terminal
Equipment. Transmitter 1 converts this digital data into any of the
following electrical formats: V.10, V.11, V.28 and V.35 prior to
transmission to the line.
If this data is being converted into either the V.11 or V.35 format,
then this pin outputs the positive polarity portion of the “RXD”
data to the line. If this data is being converted into either the V.10
or V.28 formats, then this pin is inactive.
19
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
63
TX1A
TXDA
RXDA
O
Transmitter 1 – Negative Data Differential Output to Line
The exact function of this output pin depends upon whether the
XRT4500 is operating in the DCE or DTE Modes.
DTE Mode: Transmit Data (TXD) – Negative Polarity Output
Signal
Transmitter 1 accepts a TTL level binary data stream (as the
“Transmit Data” – TXD) from the DTE Terminal Equipment. Trans-
mitter 1 converts this digital data into any of the following electrical
formats: V.10, V.11, V.28 and V.35 prior to transmission to the line.
If this data is being converted into either the V.11 or V.35 format,
then this pin outputs the negative-polarity portion of the “TXD”
data to the line. If this data is being converted into either the V.10
or V.28 formats, then this pin outputs this data to the line in a sin-
gle-ended manner.
DCE Mode: Receive Data (RXD) – Negative Polarity Output
Line Signal
Transmitter 1 accepts a TTL level binary data stream (as the
“Receive Data” – RXD) from the DCE Terminal Equipment.
Transmitter 1 converts this digital data into any of the following
electrical formats: V.10, V.11, V.28 and V.35 prior to transmission
to the line.
If this data is being converted into either the V.11 or V.35 format,
then this pin outputs the negative-polarity portion of the “RXD”
data to the line. If this data is being converted into either the V.10
or V.28 formats, then this pin outputs this data to the line in a sin-
gle-ended manner.
20
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
64
TX2A
SCTEA
RXCA
O
Transmitter 2 – Negative Data Differential Output to Line
The exact function of this output pin depends upon whether the
XRT4500 is operating in the DCE or DTE Mode.
DTE Mode Transmit Clock Echo (SCTE) – Negative Polarity
Output Signal
Transmitter 2 accepts a TTL level binary data system (as the
‘Transmit Clock Echo’ – SCTE) from the DTE terminal equip-
ment. Transmitter 2 converts this digital data into any of the fol-
lowing electrical formats: V.10, V.11, V.28 or V.35 prior to
transmission to the line.
If this data is being converted into the V.11 or V.35 electrical format
then this pin outputs the ‘Negative Polarity’ portion of the ‘SCTE’
data to the line. If this data is being converted into the V.10 or V.28
electrical format, tthen this pin outputs this data to the line in a
single-ended manner.
DCE Mode Receive Clock (RXC) Signal – Negative Polarity
Output Line Signal
Transmitter 2 accepts a TTL level binary data system (as the
‘Receive Clock - RXC) from the DCE terminal equipment. Trans-
mitter 2 converts this digital data into any of the following electrical
formats: V.10, V.11, V.28 or V.35 prior to transmission to the line.
If this data is being converted into the V.11 or V.35 electrical for-
mat then this pin outputs the ‘Negative Polarity’ portion of the
‘RXC’ data to the line. If this data is being converted into the V.10
or V.28 electrical format, then this pin outputs this data to the line
in a single-ended manner.
21
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
65
TX2B
SCTEB
RXCB
O
Transmitter 2 – Positive Data Differential Output to line.
The exact function of this output pin depends upon whether the
XRT4500 is operating in the DCE or DTE Mode.
DTE Mode Transmit Clock Echo (SCTE) – Positive Polarity
Output Signal
Transmitter 2 accepts a TTL level binary data system (as the
‘Transmit Clock Echo’ – SCTE) from the DTE terminal equip-
ment. Transmitter 2 converts this digital data into any of the fol-
lowing electrical formats: V10, V.11, V.28 or V.35 prior to
transmission to the line.
If this data is being converted into the V.11 or V.35 electrical format
then this pin outputs the ‘Positive Polarity’ portion of the ‘SCTE’
data to the line. If this data is being converted into the V.10 or V.28
electrical format, then this output pin is in-active.
DCE Mode Receive Clock (RXC) Signal – Positive Polarity
Output Line Signal
Transmitter 2 accepts a TTL level binary data system (as the
‘Receive Clock - RXC) from the DCE terminal equipment. Trans-
mitter 2 converts this digital data into any of the following electrical
formats: V.10, V.11, V.28 or V.35 prior to transmission to the line.
If this data is being converted into the V.11 or V.35 electrical for-
mat then this pin outputs the ‘Positive Polarity’ portion of the
‘RXC’ data to the line. If this data is being converted into the V.10
or V.28 electrical format, then this output pin is in-active.
66
CM_TX2
O
Transmitter 2 Output Termination Center Tap in V.35 Mode –
This pin should be by-passed to ground with an external 0.1µF
capacitor.
22
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
67
TX2D
D_SCTE D_RXC
I
Transmitter 2 – Digital Data Input from Terminal Equipment
The exact role that this input pin plays, depends upon whether
the XRT4500 is operating in the DTE or DCE Mode.
DTE Mode: SCTE (Transmit Clock Echo) Input
The Serial Communications Controller (at the DTE Terminal) is
expected to derive the SCTE (Transmit Clock Echo) clock signal,
from the TXC signal, and input it (into the XRT4500) via this
input pin. The XRT4500 will convert this binary data stream into
either the V.35, V.11 or V.28 format and will output this data via
the TX2A and TX2B output pins.
DCE Mode: RXC (Receive Clock) Input
The Serial Communications Controller (at the DCE Terminal) is
expected to apply the RXC clock signal to this input pin. The
XRT4500 will convert this binary data stream into either the V.35,
V.11 or V.28 format and will output this data via the TX2A and
TX2B output pins.
Note: If the XRT4500 has been configured to operate in both the
DTE and the “Echoed Clock” Mode, then the XRT4500 will
ignore this input pin and will instead use the clock signal which is
output via the “D_TXC” output pin (e.g., RX3D or pin 73).
68
TX3D
D_X
D_TXC
I
Transmitter 3 – Digital Data Input from Terminal Equipment
The exact role that this pin plays depends upon whether the
XRT4500 is operating in the DCE or DTE Modes.
DTE Mode: This input pin is not used
DCE Mode: TXC – Transmit Clock Signal
This input pin functions as the “TXC” (Transmit Clock) input signal
from the DCE Terminal. The XRT4500 will convert this “digital”
clock data into either the V.35, V.11 or V.28 format and will output
this data via the TR3A and TR3B output pins.
69
70
71
CM_TR3
TR3A
O
DTE Mode: AC GND – Transmitter 3 Output Termination center
tap in V.35 Mode. Connect a 0.1µF capacitor to ground.
DCE Mode: AC GND – Receiver 3 Input Termination center tap
in V.35 Mode. Connect a 0.1µF capacitor to ground.
TXCA
TXCB
TXCA
TXCB
I/O
I/O
DTE Mode: Receiver 3 – Negative Data Differential Input from
Line
DCE Mode: Transmitter 3 – Negative Data Differential Output
to Line.
TR3B
DCE Mode: Transmitter 3 – Positive Data Differential Output to Line.
DTE Mode: Receiver 3 – Positive Data Differential Input from Line.
23
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
72
73
GND
Analog GND: Receivers 4, 5, 6, 7 and 8
Receiver 3 – Digital Output to Terminal Equipment:
RX3D
D_TXC
D_X
O
This output pin is the digital (CMOS level) representation of the
line signal that is received via the TR3A (pin 70) and TR3B (pin
71) input pins.
The exact role that this pin plays depends upon whether the
XRT4500 is operating in the DCE or DTE Mode.
DTE Mode: TXC – Transmit Clock Signal
This output pin functions as the “TXC” (Transmit Clock) output
signal to the Terminal Equipment. The DTE Terminal Equipment
will typically use this signal to synthesize the SCTE clock signal.
DCE Mode: This output pin is NOT used.
Note: If the “Internal Oscillator” (within the XRT4500) is enabled,
then this pin will output a 32kHz to 64kHz clock signal. This clock
signal can be used for “Stand-Alone DTE Diagnostic” Testing.
74
RX2D
R_RXC D_SCTE
O
Receiver 2 – Digital Data Output to Equipment
This output pin is the digital (CMOS level) representation of the
line signal that is received via the RX2A (pin 77) and RX2B (pin
76) input pins.
The exact role that this pin plays depends upon whether the
XRT4500 is operating in the DCE or DTE Modes.
DCE Mode: SCTE – Transmit Clock Echo Signal:
This output pin functions as the SCTE (Transmit Clock Echo)
output signal to the Terminal Equipment. The DCE Terminal
Equipment will typically use this clock signal to sample the “TXD”
(Transmit Data).
DTE Mode: RXC – Receive Clock Signal:
This output pin functions as the “RXC” (Receive Clock) output
signal to the Terminal Equipment. The DTE Terminal Equipment
will typically use this signal to sample the “RXD” (Receive Data).
Note: If the “Internal Oscillator” (within the XRT4500) is enabled,
then this pin will output a 32kHz – 64kHz clock signal. This clock
signal can be used for “Stand-Alone DTE Diagnostic” testing.
75
EN_FLTR
I
Enable Glitch Filter on Receiver 4, 5, 6, 7, 8 inputs. Internal
20kΩ pull-down
76
77
RX2B
RX2A
RXCB
RXCA
SCTEB
RXCB
I
I
Receiver 2 – Positive Data Differential Input from Line
Receiver 2 – Negative Data Differential Input from Line
24
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
PIN DESCRIPTIONS
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE FUNCTION
78
79
RX1A
RX1B
RXDA
RXDB
TXDA
TXDB
I
I
Receiver 1 – Negative Data Differential Input from Line
Receiver 1 – Positive Data Differential Input from Line
The exact function of this input pin depends upon whether the
XRT4500 is operating in the DCE or DTE Mode. This input pin,
along with “RX1A” (pin 78) will accept a line signal in either the
V.35, V.11, V.28/EIA-232 or V.10 electrical format. Receiver 1 will
then convert this line signal into a CMOS level binary data
stream, and will output this data (to the Terminal Equipment) via
the “RX1D” output pin (pin 1).
DCE Mode – Receive Data (RXD) – Negative Polarity Input
Line Signal
80
EN_TERM
I
Enable Input Termination for Receiver 1, 2, 3, in V.11 Mode.
Internal 20kΩ pull-down to ground.
25
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
ELECTRICAL CHARACTERISTICS
Supply Voltage
Vpp +12V Supply
Vss
MIN
11
TYP
12
MAX
13
UNITS
TEST CONDITIONS
V
V
Full Load on V.28
Full Load on V.28
-5.7
-6.0
-6.3
IDD in DCE Mode- Ta=25°C, VDD=5V, Data and Clock at maximum operating frequencies unless other-
wise specified
PARAMETER
MIN
TYP
MAX
UNITS
TEST CONDITIONS
V.10
145
160
180
160
180
200
190
215
240
mA
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 10 kHz
Typical Load at 50 kHz
M0=0, M1=0, M2=0
EIA-530-A (V.11)
M0=1, M1=0, M2=0
125
205
230
275
140
230
255
305
170
275
305
365
mA
mA
mA
mA
mA
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
Typical Load at 10 MHz
EIA-530, RS449, V.36
M0=0, M1=1, M2=0
120
195
225
270
135
215
250
300
160
260
300
360
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
Typical Load at 10 MHz
X.21
115
195
215
260
130
215
240
290
155
260
290
350
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
M0=1, M1=1, M2=0
Typical Load at 10 MHz
V.35
215
255
265
290
240
285
295
320
290
340
355
385
No Load or Signal, TX Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
M0=0, M1=0, M2=1
Typical Load at 10 MHz
RESERVED
M0=1, M1=0, M2=1
120
200
225
270
135
225
250
300
160
270
300
360
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
Typical Load at 10 MHz
RS-232 (V.28)
M0=0, M1=1, M2=1
115
215
225
130
240
250
155
290
300
mA
mA
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 10 kHz
Typical Load at 100 kHz
POWER DOWN
80
90
110
Reduced Power Mode
M0=1, M1=1, M2=1
NOTES:
950mW in V.35 and 800mW in the V.28 mode. In
the “Reduced Power Mode” the XRT4500 chip dis-
sipation is 310mW.
1. Absolute Maximum Ratings are those beyond
which the safety of a device may be impaired.
4. "Typical Load" is the corresponding receiver in
another XRT4500 operating in the DTE mode.
2. All currents into device pins are positive; all cur-
rents out of device are negative. All voltages are
referenced to device ground unless otherwise
specified.
5. A 50% duty cycle square wave, at the specified fre-
quency in the table, is applied to all Clock and Data
lines of the High Speed Transmitters).
3. The efficiency of the switching regulator and the
charge pump is approximately 70%. The actual
power dissipation of the XRT4500 at 5V, with maxi-
mum loading, is 660mW in V.10, 700mW in V.11,
6. A 10 KHz 50% duty cycle square wave is applied to
all Handshake Lines (Low Speed Transmitters).
26
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
7. Input termination is enabled on High Speed V.11
Receivers.
IDD in DTE Mode - Ta=25°C, VDD=5V, Data and Clock at maximum operating frequencies unless other-
wise specified
PARAMETER
MIN
TYP
MAX
UNITS
TEST CONDITIONS
V.10
145
160
170
160
180
190
190
215
230
mA
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 10 kHz
Typical Load at 50 kHz
M0=0, M1=0, M2=0
EIA-530-A (V.11)
M0=1, M1=0, M2=0
130
190
210
250
145
210
235
280
175
250
280
335
mA
mA
mA
mA
mA
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
Typical Load at 10 MHz
EIA-530, RS449, V.36
M0=0, M1=1, M2=0
125
180
205
245
140
200
230
275
170
240
275
330
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
Typical Load at 10 MHz
X.21
120
170
190
230
130
190
210
255
155
230
250
305
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
M0=1, M1=1, M2=0
Typical Load at 10 MHz
V.35
180
220
235
255
200
245
260
285
240
295
310
340
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
M0=0, M1=0, M2=1
Typical Load at 10 MHz
RESERVED
M0=1, M1=0, M2=1
125
185
205
245
140
205
230
275
170
245
275
330
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 1 MHz
Typical Load at 4 MHz
Typical Load at 10 MHz
RS-232 (V.28)
M0=0, M1=1, M2=1
115
200
205
130
220
230
155
265
275
mA
mA
No Load or Signal, Tx Digital Inputs tied High
Typical Load at 10 kHz
Typical Load at 100 kHz
POWER DOWN
80
90
110
Reduced Power Mode
M0=1, M1=1, M2=1
NOTES:
the “Reduced Power Mode” the XRT4500 chip dis-
sipation is 310mW.
1. Absolute Maximum Ratings are those beyond
which the safety of a device may be impaired.
4. "Typical Load" is the corresponding receiver in
another XRT4500 operating in the DCE mode.
2. All currents into device pins are positive; all cur-
rents out of device are negative. All voltages are
referenced to device ground unless otherwise
specified.
5. A 50% duty cycle square wave, at the specified fre-
quency in the table, is applied to all Clock and Data
lines of the High Speed Transmitters).
3. The efficiency of the switching regulator and the
charge pump is approximately 70%. The actual
power dissipation of the XRT4500 at 5V, with maxi-
mum loading, is 660mW in V.10, 700mW in V.11,
950mW in V.35 and 800mW in the V.28 mode. In
6. A 10 KHz 50% duty cycle square wave is applied to
all Handshake Lines (Low Speed Transmitters).
7. Input termination is enabled on High Speed V.11
Receivers.
27
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
TA = 25°C, VDD = 5V, VSS = -6V, VPP = 12V, MAXIMUM OPERATING FREQUENCY UNLESS OTHERWISE SPECIFIED
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
MODE
INTERFACE/CONDITIONS
M2 TEST CONDITIONS
SUPPLY CURRENTS
M0
0
M1
0
IDD
VDD Supply Current
(DCE Mode, All Digital
Pins = GND or VDD
27
75
27
32
90
32
mA
mA
mA
0
0
0
V.10, No Load, No Signal
V.10, Full Load, w/ Signal
0
0
)
1
0
EIA-530A, No Load,
(V.11)
230
65
270
75
mA
mA
mA
1
0
0
0
0
0
0
1
1
EIA-530A, Full Load,
(V.11)
V.35, No Load on V.28
Drivers
68
80
V.35, Full Load on V.28
Drivers
20
26
16
25
32
20
mA
mA
mA
0
0
1
1
1
1
1
1
1
RS232, No Load
RS232, Full Load
Reduced Power Mode
ELECTRICAL CHARACTERISTICS (CONTIUED)
SYMBOL PARAMETER
LOGIC INPUTS
MIN
TYP
MAX
UNIT
CONDITIONS
VIH
VIL
Logic Input High Voltage
Logic Input Low Voltage
2
V
V
TTL Compatible
TTL Compatible
0.8
IIN
Logic Input Current
±250
µA
With 20kΩ internal pull-up/down
resistor to ground
LOGIC OUTPUTS
VOH
Output High Voltage
3
4.5
0.3
V
V
IO = -4mA, TTL/CMOS
Compatible
VOL
Output Low Voltage
0.8
60
IO = 4mA, TTL/CMOS
Compatible
IOSR
Output Short-Circuit Current
Three-State Output Current
-60
0
mA
µA
0V ≤ VO ≤ VDD, TTL
Compatible
IOZR
±1
M0 = Ml = M2 = VDD 0V ≤ VO
≤
VDD, TTL Compatible
28
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
POWER SUPPLY CONSUMPTION
The table below shows the typical currents the +5V,
+12V and -6V supplies require for each of the interface
modes.
When external power supplies are available, the
switching regulator and charge pumps may be dis-
abled to save on component cost and current con-
sumption from the +5V supply.
IDD
IPP
ISS
MODE
INTERFACE/CONDITIONS
SUPPLY
+5V
27
75
27
230
27
27
65
68
27
20
26
+12V
17
17
15
15
15
15
15
45
15
30
65
-6V
40
UNIT
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
M2
0
M1
0
M0
0
V.10, No Load, No Signal
V.10, Full Load with Signal
EIA-530A, No Load (V.11)
EIA-530A, Full Load (V.11)
EIA-530 (V.36) No Load
X.21
-160
-35
-130
-35
-35
-70
-120
-35
-45
-55
0
0
0
0
0
1
0
0
1
0
1
0
0
1
1
1
0
0
V.35, No Load on V.28 drivers
V.35, Full Load on V.28 drivers
Reserved
1
0
0
1
0
1
1
1
0
RS-232, No Load
1
1
0
RS-232, Full Load
The following two charts show how the IDD current
varies with temperature and voltage when only a sin-
gle 5V supply is used in the EIA-530 (V.11) mode.
This mode has the highest current consumption.
FIGURE 1. SUPPLY CURRENT VERSUS TEMPERATURE AND SUPPLY VOLTAGE, WITHOUT LOAD OR
SIGNAL IN EIA-530 (V.11) MODE
Supply Current, No Signal, No Load, All CH
154
152
150
4.75V
148
5.00V
5.25V
146
144
142
140
- 20
0
25
50
70
85
Temperature ( C)
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
FIGURE 2. SUPPLY CURRENT VERSUS TEMPERATURE AND SUPPLY VOLTAGE, WITH LOAD IN EIA-
530 (V.11) MODE
Supply Current, Signal, Full Load
360
350
4.75V
340
5.00V
330
5.25V
320
310
- 20
0
25
50
70
85
Tem perature (C)
ELECTRICAL CHARACTERISTICS (CONTIUED)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
V.11 DRIVER
VOD
VOD
Differential Output Voltage
Differential Output Voltage
+5.5
V
Open Circuit
±2
RL = 50Ω (Figure 3)
RL = 50Ω (Figure 3)
∆VOD
Change in Magnitude of Differential
Output Voltage
0.25
V
VOC
Common Mode Output Voltage
3.0
0.2
V
V
RL = 50Ω (Figure 3)
RL = 50Ω (Figure 3)
∆VOC
Change in Magnitude of Common
Mode Output Voltage
ISS
IOZ
Short-Circuit Current
±150
±100
mA
VO = GND
Output Leakage Current
±1
µA
-0.25V ≤ VO ≤ 0.25V, Power
Off or Driver Disabled
tr, tf
TPLH
TPHL
∆t
Rise or Fall Time (Transition Time)
Input to Output
4
30
30
0
10
70
65
5
25
100
100
15
ns
ns
ns
ns
ns
(Figures 4, 8 )
(Figures 4, 8 )
(Figures 4, 8 )
(Figures 4, 8 )
(Figures 4, 8 )
Input to Output
Inp. to Out. Difference, |TPLH - TPHL
|
TSKEW Output to Output Skew
5
V.11 RECEIVER
Maximum Transmission Rate
20
MHz
V
VTH
Input Threshold Voltage
Input Hysteresis
-0.2
0.2
60
-7V ≤ VCM ≤ 7V
-7V ≤ VCM ≤ 7V
∆VTH
35
mV
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
ELECTRICAL CHARACTERISTICS (CONTIUED)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
V.11 RECEIVER
IIN
RIN
tr,
Input Current (A, B)
Input Impedance
±2
10
10
5
±2.5
11
mA
kΩ
ns
ns
ns
ns
ns
-10V ≤ VA,B ≤ 10V
-10V ≤ VA,B ≤ 10V
(Figures 4, 9 )
(Figures 4, 9 )
(Figures 4, 9 )
(Figures 4, 9 )
(Figures 4, 9 )
9
RiseTime
tf
Fall Time
10
100
100
20
TPLH
TPHL
∆t
Input to Output
30
30
0
70
70
10
Input to Output
Inp. to Out. Difference, |TPLH - TPHL
|
ELECTRICAL CHARACTERISTICS (CONTINUED)
SYMBOL PARAMETER
V.35 Driver
MIN
TYP
MAX
UNIT
CONDITIONS
Maximum Transmission Rate
20
±0.44 ±0.55 ±0.66
MHz
V
VOD
IOH
IOL
Differential Output Voltage
Transmitter Output High Current
Transmitter Output Low Current
Transmitter Output Leakage Current
Rise or Fall Time
With Load, (Figure 9)
VA, B = 0V
-12
10
-11
11
±1
5
-10
12
mA
mA
µA
ns
VA, B = 0V
IOZ
±100
-0.25 ≤ VA,B ≤ 0.25V
(Figures 5, 8 )
(Figures 5, 8 )
(Figures 5, 8 )
(Figures 5, 8 )
(Figures 5, 8 )
tr, tf
TPLH
TPHL
∆t
Input to Output
30
25
0
60
55
5
100
80
ns
Input to Output
ns
Inp. to Out. Difference, |TPLH - TPHL
|
20
ns
TSKEW Output to Output Skew
5
ns
V.35 Receiver
VTH
∆VTH
IIN
Differential Input Threshold Volt.
-0.2
135
0.2
60
V
mV
mA
Ω
-2V = (VA + VB)/2 = 2V (Figure 5)
-2V = (VA + VB)/2 = 2V (Figure 5)
-10V = VA, B = 10V
-10V = VA, B = 10V
(Figure 5, 9 )
Input Hysteresis
Input Current (A, B)
Input Impedance (A, B)
Rise Time
35
±60
150
10
RIN
tr
165
ns
ns
ns
ns
tf
Fall Time
5
(Figure 5, 9 )
TPLH
TPHL
Input to Output
Input to Output
75
100
100
(Figure 5, 9 )
75
(Figure 5, 9 )
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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ELECTRICAL CHARACTERISTICS- TA = 25°C, VDD = 5V + 5%
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
V.10 DRIVER
Maximum Transmission Rate
Output Voltage
120
Kbps
V
VO
VO
ISS
IOZ
±4.0
±6.0
Open Circuit, RL = 3.9k
RL = 450Ω (Figure 6)
VO = GND
Output Voltage
±3.6
V
Short-Circuit Current
Input Leakage Current
±100
±100
mA
µA
±0.1
1.5
-0.25 ≤ VO ≤ 0.25V, Power Off or
Driver Disabled
tr, tf
Rise or Fall Time
Input to output
Input to output
0
µs
µs
µs
(Figures 6, 10 ), RL = 450Ω, CL =
100pF, RSLEW_CNTL = 10k
TPLH
1.5
0.5
3
1
6
2
(Figures 6, 10 ), RL = 450Ω, CL = 100pF
RSLEW_CNTL = 10k
TPHL
(Figures 6, 10 ), RL = 450Ω, CL = 100pF
RSLEW_CNTL = 10k
V.10 RECEIVER
VTH
AVTH
IIN
Receiver Input Threshold Voltage
-0.2
0.2
60
V
Receiver Input Hysteresis
Receiver Input Current
Receiver Input Impedance
Rise or Fall Time
35
±2.0
11
mV
mA
kΩ
ns
-2.5
9
±2.5
12
-10 ≤ VA ≤ 10V
-10 ≤ VA ≤ 10V
(Figures 7, 11 )
(Figures 7, 11 )
(Figures 7, 11 )
RIN
tr, tf
10
TPLH
TPHL
Input to Output
200
250
ns
Input to Output
ns
V.28 Driver
Maximum Transmission Rate
120
±5
Kbps
V
VO
Output Voltage
±5.5
±1
±6.5
Open Circuit
RL = 3k (Figure 6)
ISS
IOZ
Short-Circuit Current
Input Leakage Current
±100
±100
mA
VO = GND
µA
-0.25 ≤ VCM ≤ 0.25V, Power Off or
Driver Disabled
SR
Slew Rate
2
5
2
2
30
6
V/µs (Figures 6, 10 ), RL = 3k, CL = 2500pF
TPLH
TPHL
Input to output
Input to output
µs
µs
(Figures 6, 10 ), RL = 3k, CL = 2500pF
(Figures 6, 10 ), RL = 3k, CL = 2500pF
6
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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ELECTRICAL CHARACTERISTICS (CONTINUED)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
CONDITIONS
V.28 RECEIVER
Maximum Transmission Rate
256
Kbps
V
VTHL
VTLH
AVTH
RIN
Input Low Threshold Voltage
Input High Threshold Voltage
Receiver Input Hysteresis
Receiver Input Impedance
Rise or Fall Time
1.4
1.4
0.4
5
0.8
2.0
0.1
3
V
V
1.0
7
kΩ
ns
ns
ns
-15 ≤ VA ≤ 15V
(Figures 7, 11 )
(Figures 7, 11 )
(Figures 7, 11 )
tr, tf
10
TPLH
TPHL
Input to Output
400
450
Input to Output
The following tests circuits and timing diagrams are
referenced in the preceding Electrical Characteristics
Tables.
FIGURE 3. RS422 DRIVER TEST CIRCUIT
TXB
RL=50
RL=50
Ω
Ω
VOD
TXA
VOC
FIGURE 4. RS422 DRIVER/RECEIVER AC TEST CIRCUIT
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
FIGURE 5. V.35 DRIVER/RECEIVER AC TEST CIRCUIT (TX1/RX1, TX2/RX2 ONLY)
FIGURE 6. V.10/V.28 DRIVER TEST CIRCUIT
FIGURE 7. V.10 (RS-423) V.28 (RS-232) RECEIVER
TEST CIRCUIT
FIGURE 8. V.11, V.35 DRIVER PROPAGATION DELAYS
FIGURE 9. V.11, V.35 RECEIVER PROPAGATION DELAYS
V1 = 0V for V.35, 2.5V for V.11
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
FIGURE 10. V.10 (RS-423) V.28 (RS-232) DRIVER PROPAGATION DELAYS
FIGURE 11. V.10, V.28 RECEIVER PROPAGATION DELAYS
V1 = 1.8V for V.28, 0.1V for V.10
V2 = 1.0V for V.28. -0.1V for V.10
TABLE 1: RECEIVER SPECIFICATIONS
V.35
V.11
V.10
RS232
SINGLE-ENDED OR
DIFFERENTIAL
DIFFERENTIAL
DIFFERENTIAL
SINGLE-ENDED
SINGLE-ENDED
Max Signal Level
Min Signal Level
± 660 mV
± 260 mV
± 2 V
± 6 V
± 300 mV
± 7 V
± 6 V
± 300 mV
Note 1
± 10 V
± 12 V
N/A
± 15 V
± 3 V
Common-Mode Voltage
Max Signal Peak Operation
Max Signal Peak no Damage
Rin Differential
N/A
± 2.66 V
± 10 V
± 10 V
± 12 V
Note 2
N/A
± 15 V
± 25 V
100 Ω±10%
150 Ω±15%
> 175 Ω
N/A
N/A
Rin Common-Mode
N/A
DC Rin Each Input to
Ground
> 8K Ω
> 8K Ω
3K Ω < DC Rin < 7 K Ω
Clock Frequency
20 MHz
20MHz
120KHz
256KHz
NOTES:
2. 100 to 150 Ohms terminated.
1. ± 7 V on Receivers 1-6, not applicable for Receiv-
ers 7-8
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
TABLE 2: TRANSMITTER SPECIFICATION
V.35 V.11
SINGLE-ENDED OR
DIFFERENTIAL
V. 10
RS-232
SINGLE-ENDED
DIFFERENTIAL
DIFFERENTIAL
SINGLE-ENDED
Max Signal Level
± 660 mV
|V0| < 6 V
4 < |V0| < 6 V
± 6 V
RL = 100Ω
RL = 3900Ω
RL = 3900Ω
3000Ω < RL < 7000Ω
Min Signal Level
± 440 mV
2V < |VT| >0.5
|VT| > 0.9 V0
± 5 V
RL = 100Ω
V0 R L = 100Ω
RL = 450Ω
3000Ω < RL < 7000Ω
Offset Voltage
Rout Differential
N/A
100Ω ± 10%
150Ω ± 15%
N/A
|Vos| < 3V
100Ω
N/A
N/A
N/A
N/A
Rout Common-Mode
Rout Power Off
N/A
N/A
N/A
N/A
N/A
> 300Ω
< 30 V/ms
256 KHz
Output Slew Rate/Tr,Tf
Clock Frequency
20 ns
20 ns
1ms
20 MHz
20 MHz
120 KHz
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
1.0 SYSTEM DESCRIPTION
signals must comply with the “ITU-T V.35 Electrical
Interface” requirements.
The XRT4500 Multi-protocol Serial Network Interface
IC is a flexible transceiver chip that is capable of sup-
porting the following “Communication Interfaces”.
• RXD - Receive Data (CCITT Circuit 104)
• TXD - Transmit Data (CCITT Circuit 103)
• RXC - Receive Clock (CCITT Circuit 115)
• TXC - Transmit Clock (CCITT Circuit 114)
• SCTE (or TXCE) - Transmit Clock Echo
• ITU-T V.35
• ITU-T V.28/EIA-232
• EIA-449
• ITU-T V.36
• ITU-T X.21
• EIA-530
Also, the ITU-T V.35 Communications Interface speci-
fication states that each of the following signals must
comply with the “ITU-T V.28 Electrical Interface” re-
quirements.
• EIA-530A
• RTS - Request to Send (CCITT Circuit 105)
• CTS - Clear to Send (CCITT Circuit 106)
• DTR - Data Terminal Ready
The XRT4500 uses the following “electrical interfac-
es” in order to realize each of these “Communication
Interfaces”.
• ITU-T V.11/EIA-422
• ITU-T V.10/EIA-423
• ITU-T V.35
• DSR - Data Set Ready (CCITT Circuit 107)
• DCD - Data Carrier Detect (CCITT Circuit 109)
• RL - Remote Loop-back Indicator*
• ITU-T V.28/EIA-232
• LL - Local Loop-back Indicator*
1.1 THE DIFFERENCE BETWEEN AN ELECTRI-
CAL INTERFACE AND A COMMUNICATIONS
INTERFACE
• TM - Test Mode Indicator*
NOTE: *Option Signals, per the “ITU-T V.35 Electrical Interface”
Finally, the “ITU-T V.35 Communications Interface”
recommends the use of the ISO-2593 34 pin Connec-
tor. (See Figure 46 connector drawings on page 73).
It is important to describe the difference between an
Electrical Interface specification and a Communica-
tions Interface specification. An Electrical Interface
specification defines the electrical characteristics of a
transmitter or receiver. These characteristics include
voltage, current, impedance levels, rise/fall times and
other similar parameters. Examples of electrical inter-
faces are ITU-T V.10 (EIA-423), ITU-T V.11 (EIA-
422), V.35 and V.28 (EIA-232).
The XRT4500 contains a sufficient number of receiv-
ers, transmitters and transceivers to transport all of
the signals required for each of the above-mentioned
Communication Interface standards. By configuring
the XRT4500 to operate in a particular “Communica-
tion Interface” Mode, each of the Transmitters and
Receivers will automatically be configured to support
the appropriate “Electrical Interface” requirements.
In contrast, a Communications Interface specification
describes a “Physical Layer” interface in its entirety.
This description includes the names and functions of
all of the involved signals. The Communications Inter-
face specification identifies which electrical interface
is to be used to realize each of these signals as well
as the connector type. Examples of communication
interface types include ITU-T V.35, ITU-T V.28 (EIA-
232), EIA-449, EIA-530A, ITU-T X.21, and ITU-T
V.36.
Table 3 and Table 4 present the relationship between
the Communication Interface Mode that the
XRT4500 has been configured to operate in and the
corresponding Electrical Interface Mode that a giv-
en Transmitter or Receiver will be automatically con-
figured in.
Table 3 presents this information for the XRT4500
configured to operate in the DTE Mode. Table 4 pre-
sents this information when the XRT4500 has been
configured to operate in the DCE Mode.
For example, the “ITU-T V.35 Communications Inter-
face” specification requires that each of the following
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XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
TABLE 3: DTE MODE - CONTROL PROGRAMMING FOR DRIVER AND RECEIVER MODE SELECTION
DRIVER/RECEIVER PAIR AND CORRESPONDING SIGNAL NAME - DTE MODE
CONTROL
INTERFACE
INPUTS
TX1 RX1 TX2 RX2 TX3 RX3 TX4 RX4 TX5 RX5 TX6 RX6
TXD RXD SCTE RXC - TXC RTS CTS DTR DSR DCD
TX8 RX8
RL RI/TM
TX7 RX7
LL -
STANDARD
M2 M1 M0
-
V.10
0 0 0
V.10 V.10 V.10 V.10 Off V.10 V.10 V.10 V.10 V.10 Off V.10 V.10 Off V.10 V.10
V.11 V.11 V.11 V.11 Off V.11 V.11 V.11 V.10 V.10 Off V.11 V.10 Off V.10 V.10
EIA-530-A
(V.11)
0 0 1
EIA-530,
RS449,
V.36
0 1 0
V.11 V.11 V.11 V.11 Off V.11 V.11 V.11 V.11 V.11 Off V.11 V.10 Off V.10 V.10
X.21
V.35
0 1 1
1 0 0
1 0 1
1 1 0
V.11 V.11 V.11 V.11 Off V.11 V.11 V.11 V.11 V.11 Off Off
Off Off
Off Off
V.35 V.35 V.35 V.35 Off V.35 V.28 V.28 V.28 V.28 Off V.28 V.28 Off V.28 V.28
V.11 V.11 V.11 V.11 Off V.11 V.11 V.11 V.11 V.11 Off V.11 V.10 Off V.10 V.10
V.28 V.28 V.28 V.28 Off V.28 V.28 V.28 V.28 V.28 Off V.28 V.28 Off V.28 V.28
RESERVED
RS232
(V.28)
POWER
DOWN
1 1 1
Off Off
Off Off
Off Off Off Off
Off Off Off Off
Off Off
Off Off
TABLE 4: DCE MODE - CONTROL PROGRAMMING FOR DRIVER AND RECEIVER MODE SELECTION
DRIVER/RECEIVER PAIR AND CORRESPONDING SIGNAL NAME - DCE MODE
CONTROL
INPUTS
INTERFACE
STANDARD
TX1 RX1 TX2 RX2 TX3 RX3 TX4 RX4 TX5 RX5 TX6 RX6 TX7 RX7 TX8 RX8
M2 M1 M0
RXD TXD RXC SCTE TXC
-
CTS RTS DSR DTR DCD -
- LL
RI/TM RL
V.10
0 0 0
0 0 1
V.10 V.10 V.10 V.10
V.11 V.11 V.11 V.11
V.10 Off V.10 V.10 V.10 V.10 V.10 Off
V.11 Off V.11 V.11 V.10 V.10 V.11 Off
Off V.10 V.10 V.10
Off V.10 V.10 V.10
EIA-530-A
(V.11)
EIA-530,
RS449,
V.36
0 1 0
V.11 V.11 V.11 V.11
V.11 Off V.11 V.11 V.11 V.11 V.11 Off
Off V.10 V.10 V.10
X.21
V.35
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
V.11 V.11 V.11 V.11
V.35 V.35 V.35 V.35
V.11 V.11 V.11 V.11
V.28 V.28 V.28 V.28
V.11 Off V.11 V.11 V.11 V.11 Off Off
V.35 Off V.28 V.28 V.28 V.28 V.28 Off
V.11 Off V.11 V.11 V.11 V.11 V.11 Off
V.28 Off V.28 V.28 V.28 V.28 V.28 Off
Off Off
Off Off
Off V.28 V.28 V.28
Off V.10 V.10 V.10
Off V.28 V.28 V.28
RESERVED
RS232
POWER
DOWN
Off Off
Off Off
Off Off Off Off
Off Off Off Off
Off Off
Off Off
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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1.2 THE SYSTEM ARCHITECTURE
• Configure the XRT4500 into the “Latch” Mode.
• Configure the XRT4500 into the “Register” Mode.
The XRT4500 contains the following functional
blocks.
• Configure the XRT4500 into either the “2-Clock” or
• The High-Speed Transceiver Block
the “3-Clock” Mode.
• The Handshaking/Control Transceiver Block
• Enable the “Internal Oscillator”, in order to support
“Stand-Alone DTE Diagnostic Operation.
• The Diagnostic Operation Indicator Transceiver
Block
• Invert the TXC Clock signal (for DCE Application) or
the RXC Clock signal (for DTE Applications).
• The Control Block
• Invert the TXD signal (for DTE Applications) or the
RXD signal (for DCE Applications).
Block Diagrams are located on page 1 and 2. The
figures illustrate how the eight receivers and transmitters
in the XRT4500 are grouped into the “High-Speed
Transceiver” Block, the “Handshaking/Control Trans-
ceiver” Block and the “Diagnostic Operation Indicator
Transceiver” Block.
• Enable the X.21 mode.
A more detailed discussion of the “Control” Block can
be found in Section 1.2.4.
Figure 12, Figure 13, Figure 14, and Figure 15 are a
set of functional block diagrams that give more de-
tailed information about the four functional blocks
shown in the top-level diagram. Figure 12 presents
detailed information on the “High-Speed Transceiver”
block. Figure 13 presents detailed information about
the “Handshaking/Control Transceiver” block.
Figure 14 presents detailed information about the “Di-
agnostic Operation Indicator Transceiver” Block. Fi-
nally, Figure 15 presents some detailed information
about the “Control” Block.
The “Control” block permits the user to implement the
following configuration options in the XRT4500.
• Select which Communication Interface Mode the
XRT4500 will operate in. (RS-252, V.36, etc.)
• Configure the XRT4500 into either the DTE or the
DCE Mode.
• Configure the XRT4500 to operate in a “Loop-back”
Mode.
• Enable the “Echo-Clock” Mode.
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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1.2.1 The “High -Speed Transceiver” Block
the center of the internal termination. This pin should
be bypassed to ground with an external 0.1µF capac-
itor in order to provide the best possible driver output
stage balance.
The “High-Speed Transceiver” block supports the
transmission and reception of high speed data and
clock signals for the selected “Communication Inter-
face”. This block contains receivers RX1 and RX2,
transmitters TX1 and TX2, and bi-directional trans-
ceiver TR3 which is composed of TX3 and RX3. Each
of these devices may be configured to support the
“Electrical Interface” requirements per ITU-T V.35,
ITU-T V.11 (EIA-422), ITU-T V.10 (EIA-423), or ITU-T
V.28 (EIA-232). In the “ITU-T V.35” Mode, each trans-
mitter has a common mode pin that is connected to
In a system application, the TX1-RX1 pair and TX2-RX2
pair handle the TXD-RXD (Transmit Data - Receive
Data) and the TXC-RXC (Transmit Clock - Receive
Clock) high speed interface signals respectively. Trans-
ceiver TR3 is dedicated to the SCTE (Transmit Clock
Echo) signal for both DCE and DTE modes of operation.
Transceiver TR3 functions as a receiver for the DTE
mode and as a transmitter during the DCE mode.
FIGURE 12. HIGH-SPEED TRANSCEIVER BLOCK
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
1.2.2 The “Handshaking/Control Signal Trans-
ceiver” Block
ments per ITU-T V.11 (EIA-422), ITU-T V.10 (EIA-
423), or ITU-T V.28 (EIA-232). The RX4-TX4 pair is
dedicated for the “RTS” (Request to Send) and “CTS”
(Clear-to-Send) signals while RX5-TX5 are intended
to support the “DTR” (Data Terminal Ready) and the
“DSR” (Data Set Ready) signals. Transceiver TR6
supports the “DCD” (Data Carrier Detect) signal.
The “Handshaking/Control Signal Transceiver” Block
contains receivers RX4 and RX5, transmitters TX4
and TX5, and a transceiver TR6 which is composed
of TX6 and RX6. Each of these devices may be con-
figured to support the “Electrical Interface” require-
FIGURE 13. HANDSHAKING/CONTROL TRANSCEIVER BLOCK
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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1.2.3 The “Diagnostic Operation Indicator
Transceiver” Block
These devices may be configured to support the
“Electrical Interface” requirements, per ITU-T V.10
(EIA-423) or ITU-T V.28 (EIA-232). These devices
were specifically designed to support the Local Lock
(LL), Remote Loopback (RL) and RI (or TM) signals.
The “Diagnostic Operation Indicator Transceiver”
block contains transceiver TR7, which is composed of
TX7 and RX7, receiver RX8 and transmitter TX8.
FIGURE 14. DIAGNOSTIC OPERATION INDICATOR TRANSCEIVER BLOCK
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1.3 THE CONTROL BLOCK
• To optionally configure the XRT4500 to operate in
the “Latch” Mode.
The purpose of the Control Block is to permit the user
to configure the XRT4500 into a wide variety of oper-
ating modes. In particular, the Control Block permits
the user to implement the following configuration se-
lections for the XRT4500.
• To optionally configure the XRT4500 to operate in
the “Register” Mode.
• To configure the XRT4500 to operate in either the
“2 Clock” or the “3-Clock” Mode.
To select which Communication Interface Mode the
XRT4500 will operate in.
• To enable or disable the Internal Oscillator (for DTE
Stand-Alone Diagnostic operation).
• To configure the XRT4500 to operate in either the
DTE or the DCE Mode.
• To invert the TXC clock signal (for DCE applica-
tions) or the RXC clock signal (for DTE applica-
tions).
• To optionally configure the XRT4500 to operate in a
Loop-back Mode.
• To invert the TXD data (for DCE applications) or the
RXD data (for DTE applications).
• To enable or disable the “Echo-Clock” Mode.
FIGURE 15. DIAGRAM OF THE XRT4500 CONTROL BLOCK
The input pins shown in Figure 15, the Control Block,
are described in detail, below.
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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1.3.1 M[2:0] - The (Communication Interface)
Mode Control Select Pins.
• ITU-T V.36
• ITU-T X.21
• EIA-530
As mentioned earlier, the XRT4500 is capable of sup-
porting each of the following “Communication Inter-
face” standards.
• EIA-530(A)
The XRT4500 can be configured to operate in either
one of these “Communication Interface” standards, by
setting the “M[2:0]” bit-fields to the appropriate val-
ues, as listed in Table 5.
• ITU-T V.35
• ITU-T V.28 (EIA-232)
• EIA-449
TABLE 5: THE RELATIONSHIP BETWEEN THE SETTINGS FOR THE M[2:0] BIT-FIELDS AND THE CORRESPONDING
COMMUNICATION INTERFACE THAT IS SUPPORTED
COMMUNICATION INTERFACE M2 M1 M0
COMMENTS
RS423 (V.10)
0
0
0
All Transmitters and Receivers are functioning in the V.10 Mode.
NOTE: This is not a standard Communication Interface.
EIA-530A (V.11)
EIA-530 (V.36)
RS449
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
1
0
0
1
0
1
0
1
X.21
V.35
Reserved
RS232 (V.28)
Power Down Mode
All Transmitters and Receivers are shut-off. Transmitter outputs are tri-stated
and all internal loads are disconnected. The charge pump and DC-DC con-
nect continues to operate.
NOTE: The M[2:0] input pins are internally pulled “high”. As
a consequence, the XRT4500 will automatically be config-
ured into the “POWER-DOWN” Mode, if the M[2:0] input
pins are left “floating”.
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
1.3.2 DCE/DTE - The DCE/DTE Mode Select Pin
"low" configures the XRT4500 to operate in the "DTE"
Mode. A brief description of DCE Mode and DTE
Mode operations are listed below.
The XRT4500 is capable of supporting either the
"DCE" or "DTE" Modes of operation. Setting this in-
put pin "high" configures the XRT4500 to operate in
the "DCE" Mode. Conversely, setting this input pin
FIGURE 16. A SIMPLE ILLUSTRATION OF THE DCE/DTE INTERFACE
DTE
DCE
EQUIPMENT
EQUIPMENT
TXD
RXD
TXC
RXC
TXCE
XRT4500
DTR
XRT4500
DSR
DCD
CTS
RTS
LL
RL
RI (or TM)
Figure 16 presents a very simple illustration of a DCE
Terminal being interfaced to a DTE Terminal. From
this figure, one can make the following observations
about the DCE and DTE Terminals.
Further, the DCE Terminal is responsible for receiving/
terminating all of the following signals.
• TXD - Transmit Data (High Speed Signal)
• TXCE (or SCTE) - Transmit Clock Echo (High
Speed Signal)
The DCE Terminal
The DCE Terminal is responsible for sourcing/gener-
ating all of the following signals.
• DTR - Data Terminal Ready
• RTS - Request to Send
• RXD - Receive Data (High Speed Signal)
• RXC - Receive Clock (High Speed Signal)
• TXC - Transmit Clock (High Speed Signal)
• DSR - Data Set Ready
• LL - Local Loop-back Indicator
• RL - Remote Loop-back Indicator
Because of this, whenever the XRT4500 is configured
to operate in the “DCE” Mode, then the following con-
figuration conditions are “TRUE”.
• DCD - Data Carrier Detect
• CTS - Clear to Send
• Three “high-speed” Transmitters are enabled, and
• Two “high-speed” Receivers are enabled.
• Four “low-speed” Transmitters are enabled, and
• Four “low-speed” Receivers are enabled.
• RI (Ring Indicator) or
• TM (Test Mode).
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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The DTE Terminal
• Two “high-speed” Transmitters are enabled, and
• Three “high-speed” Receivers are enabled.
• Four “low-speed” Transmitters are enabled, and
• Four “low-speed” Receivers are enabled.
The DTE Terminal is responsible for sourcing/gener-
ating all of the following signals.
• TXD - Transmit Data
• TXCE (or SCTE) - Transmit Clock Echo
• DTR - Data Terminal Ready
• RTS - Request to Send
Other Comments about DCE and DTE Equipment
Whenever DCE and DTE Equipment are interfaced to
each other, the DCE Equipment is typically the
source of all timing signals. The DTE Equipment will
typically function as a “Clock Slave”.
• LL - Local Loop-back Indicator
• RL - Remote Loop-back Indicator
1.3.3 The LP - Loop-Back Enable/Disable
Select Pin
Further, the DTE Terminal is responsible for receiv-
ing/terminating all of the following signals.
As mentioned earlier, the XRT4500 can be configured
to operate in the loop-back mode. Setting the “LP” in-
put pin “high” disables the loop-back mode (within the
XRT4500). Conversely, setting this input “low” config-
ures the XRT4500 to operate in the “TXD/RXD” loop-
back mode.
• RXD - Receive Data
• TXC - Transmit Clock
• RXC - Receive Clock
• DSR - Data Set Ready
• DCD - Data Carrier Detect
• CTS - Clear-to-Send
• RI (Ring Indicator)
A detailed description of the “TXD/RXD” loop-back
Mode is presented below.
Behavior of DTE/DCE Mode Devices, when the
Loop-Back Mode is Disabled
• TM (Test Mode Indicator).
Because of this, whenever the XRT4500 is configured
to operate in the “DTE” Mode, then the following con-
figuration conditions are “TRUE”.
Figure 17 presents an illustration of a DTE and DCE
Terminal interfaced to each other when no XRT4500
Loop-Back Mode has een configured.
FIGURE 17. ILLUSTRATION OF BOTH THE DTE AND DCE MODE XRT4500 OPERATING, WHEN THE LOOP-BACK
MODE IS DISABLED
SCC (L)
DTE (#2)
RX1
SCC (R)
DTE (#1)*
TX1
TXD
78
79
63
62
60
67
1
TXD
TXD_IN
SCTE
64
65
77
76
74
SCTE
RX2
TX2
SCTE_IN
TXC
RXC
RXD
70
71
70
71
68
67
60
73
74
RX3
RX2
TXC_IN
TX3
TX2
TXC
RXC
RXD
64
77
76
RXC_IN
RXD_IN
65
63
62
78
79
1
RX1
TX1
XRT4500
XRT4500
* Indicates scenario # from Table 8
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
Figure 27 indicates that the DTE Serial Communica-
tions Controller (SCC) sources the “TXD” signal. This
digital signal is then converted into an “Analog Line”
signal (as dictated by the “M[2:0]” settings) by the
“DTE Mode” XRT4500. This line signal is then trans-
mitted over the DTE/DCE Interface and is received by
the DCE Terminal. This Analog Line signal is then
converted back into the digital format by the “DCE
Mode” XRT4500. This digital signal is ultimately re-
ceived and terminated by the DCE SCC (Serial Com-
munications Controller). Likewise, this figure indicates
that the RXD signal is sourced by the DCE SCC. This
digital signal is then converted into an “Analog Line”
signal by the “DCE Mode” XRT4500. This line signal is
then transported over the DCE/DTE Interface and is re-
ceived by the “DTE Mode” XRT4500. This “Analog Line
signal” is then converted back into the digital format by
the “DTE Mode” XRT4500. The XRT4500 then outputs
this signal to the “DTE SCC”. This is considered to the
be the “Normal” (Non-loop-back/Diagnostic) Mode of
operation.
NOTE: Figure 27 only depicts the “High-Speed” DCE/DTE
Interface signals. The “Low-Speed” control/handshaking
signals are not affected by the loop-back mode.
Behavior of the DTE Mode XRT4500, when the
Loop-Back Mode is Enabled.
Figure 18 presents an illustration of a DTE and a
DCE Terminal interfaced to each other. In this case,
the XRT4500 (associated with the DTE Terminal) has
been configured to operate in the “Loop-back” Mode
FIGURE 18. ILLUSTRATION OF THE BEHAVIOR THE DTE MODE XRT4500, WHEN IT IS CONFIGURED TO OPERATE IN
THE LOOP-BACK MODE
Digital/Terminal
Loop-back Path
Analog/Line
Loop-back Path
DCE (#2)
RX1
SCC (L)
S C C ( R )
DTE (#3)
M U X
1
T X D
78
79
63
60
67
1
T X D
TXD_IN
TX1
62
77
64
S C T E
74
SCTE
RX2
TX2
SCTE_IN
76
65
T X C
R X C
R X D
70
70
71
68
67
60
73
74
RX3
TX3
TX2
TXC_IN
RXC_IN
RXD_IN
T X C
R X C
R X D
71
64
65
71
RX2
77
63
62
78
1
RX1
TX1
79
X R T 4 5 0 0
X R T 4 5 0 0
NOTE: Figure 18 only depicts the “High-Speed” signals.
The “Low-Speed” control/handshaking signals are not
affected by the loop-back mode.
Terminal Equipment). The signals (from the DTE
SCC) are never converted into the Analog format,
and are not outputted to the line.
If the Loop-back Mode is configured within the
XRT4500, while it is operating in the DTE Mode, then
the following two (2) loop-back paths will exist.
The TXD signal (originating from the DTE SCC),
along with the SCTE (Transmit Echo Clock) will be not
be outputted to the DCE Terminal. Instead, this signal
will be loop-back into the “DTE SCC. The “TXD” sig-
nal will ultimately be outputted to the DTE SCC via
the “RXD” output pin of the “DTE Mode” XRT4500.
The SCTE signal will ultimately output the DTE SCC
via the “RXC” output pin of the XRT4500.
• A Digital/Terminal-Side Loop-back
• An Analog/Line-Side Loop-back
Each of these Loop-back paths are described below.
1. The Digital/Terminal Side Loop-back path:
This loop-back path is referred to as a “Digital/Termi-
nal Side” Loop-back, because all signals originate
from and are terminated by the DTE SCC (e.g., the
NOTE: Since the DTE SCC requires the TXC signal (in
order to synthesize the SCTE signal), this loop-back still
permits the TXC signal to pass through to the DTE SCC.
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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2. The Analog/Line-Side Loop-back path:
signal will be looped-back out to the “DCE Terminal”
via the “TXD” signal path.
This loop-back path is referred to as an “Analog/Line-
Side” Loop-back, because all signals originate from and
are ultimately terminated by the DCE Terminal. These
signals originate from the DCE Terminal; and are out-
putted to the line, to the DTE Terminal. However, these
signals (from the DCE Terminal) are never converted in-
to the Digital format (by the DTE Mode XRT4500).
These signal are kept in the “Analog” format, and are
looped-back (over the line) to the DCE Terminal.
NOTE: In this loop-back mode, the RXC signal (e.g., the
companion clock signal to RXD) is also received by the
DTE Terminal and looped-back out to the DCE Terminal. In
this case, the “RXC” (Receive Clock) signal will be routed to
the DCE Terminal through the “SCTE” signal path The DCE
SCC can still use the RXC (via the SCTE signal path), in
order to sample the RXD signal (which is available via the
“TXD” signal path).
Behavior of the DCE Mode XRT4500, when the
Loop-Back Mode is Enabled.
The RXD signal (originating from the DCE Terminal)
will be transmitted over the line to the DTE Terminal.
However, this signal will not be converted into the dig-
ital format by the “DTE Mode” XRT4500. Instead, this
Figure 19 presents an illustration of a DTE and a
DCE Terminal interfaced to each other. In this case,
the XRT4500 (associated with the DCE Terminal) has
been configured to operate in the “Loop-back” Mode.
FIGURE 19. ILLUSTRATION OF THE BEHAVIOR OF THE DCE MODE XRT4500, WHEN IT IS CONFIGURED TO OPERATE
IN THE LOOP-BACK MODE
Analog/Line
Loop-back Path
Digital/Terminal
Loop-back Path
DTE (#1)
TX1
SCC (L)
DCE (#4)
RX1
SCC (R)
MUX
1
78
79
T X D
63
62
60
67
1
T X D
TXD_IN
77
76
S C T E
64
65
74
SCTE
RX2
TX2
SCTE_IN
70
71
T X C
70
71
68
67
73
RX3
TXC_IN
RXC_IN
RXD_IN
TX3
T X C
R X C
R X D
64
65
77
76
R X C
R X D
74
1
RX2
RX1
TX2
TX1
78
79
63
62
60
XRT4500
XRT4500
NOTE: Figure 19 only depicts the “High-Speed” DCE/DTE
Interface signals. The “Low-Speed” control/handshaking
signals are not affected by the loop-back mode.
(e.g., the Terminal Equipment). The signals (originat-
ing at the DCE SCC) are not converted into the Ana-
log format, and are not output to the line.
If the Loop-back Mode is configured within the
XRT4500, while it is operating in the DCE Mode, then
the following two (2) loop-back paths exists.
The “RXD” signal (originating from the DCE SCC)
along with the “RXC” (Receive Clock) signal will not
be converted into the Analog format, nor output to the
DTE Terminal (over the line). Instead, this signal will
remain in the “Digital-format” and will be looped-back
into the DCE SCC. The “RXD” signal will ultimately be
output to the DCE SCC via the “TXD” output of the
“DCE Mode” XRT4500.
• A Digital/Terminal-Side Loop-back
• An Analog/Line-Side Loop-back
Each of these Loop-back paths are described below.
1. The Digital/Terminal Side Loop-back:
Again, this loop-back path is referred to as a “Digital/
Terminal Side” Loop-back, because all of the signals
originate from, and are terminated by the DCE SCC
NOTE: The “RXC” signal (e.g., the companion clock signal to
“RXD”) will also be loop-back into the “DCE SCC”. This signal
will be output (by the XRT4500) via the “SCTE” output pin.
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2. The Analog/Line-Side Loop-back:
Data Communications equipment. These SCCs can
be realized in an ASIC solution or they can be a stan-
dard product. An example of a standard product SCC,
would be the Am85C30 from AMD.
This loop-back path is referred to as an “Analog/Line-
Side” loop-back, because all signals originate from
and are terminated by the DTE Terminal (over the
line). These signals originate from the DTE Terminal,
and are output, over the line, to the DTE Terminal.
However, these signal (originating from the DTE Ter-
minal) are never converted into the Digital format (by
the DCE Mode XRT4500). These signals are kept in
the “Analog” format, and are looped-back (over the
line) to the DTE Terminal.
One variation that exists among these SCCs are in
the number of “Clock Signals” that these chips use
and process, in order to support Data Communica-
tions over a DTE/DCE Interface. For example, some
SCCs process 3 clock signals in order to support the
transmission/reception of data over a DTE/DCE Inter-
face. Other SCCs process only 2 or 1 clock signals.
The “TXD” signal (originating from the DTE Terminal)
will be transmitted over the line to the DCE Terminal.
However, this signal will not be converted into the dig-
ital format by the “DCE Mode” XRT4500. Instead, this
signal will be loop-back to the DTE Terminal, via the
“RXD” signal path.
Examples of a “3-Clock” and a “2-Clock” DTE/DCE
Interface are presented below.
The “3-Clock” DCE/DTE Interface
Many of the Data Communication Standards (e.g.,
ITU-T V.35, EIA-530(A), etc.) define three clock sig-
nals that are to be transported over the DTE/DCE In-
terface. These tree clock signals are listed below.
NOTE: In this loop-back mode, the “SCTE” signal (e.g., the
companion clock signal to “TXD”) is also received by the
DCE Terminal and is looped-back to the DTE Terminal. In
this case, the SCTE signal will be routed through the “RXC”
path. The DTE SCC can use this signal to sample the TXD
(now RXD signal).
• TXC - Transmit Clock
• RXC - Receive Clock
• SCTE (or TXCE) - Transmit Clock Echo
Figure 20 presents an illustration of a DTE and DCE
exchanging data over a “3-Clock DTE/DCE” Interface.
1.3.4 The EC* (Echo Clock Mode - Enable/
Disable Select Input pin)
A wide variety of Serial Communications Controller
(SCCs) are deployed in either “DTE” or “DCE” type of
FIGURE 20. ILLUSTRATION OF A TYPICAL “3-CLOCK DCE/DTE” INTERFACE
SCC (L)
DTE (#1)
T X 1
DCE (#2)
R X 1
SCC (R)
TXD
7 8
7 9
6 3
6 2
6 0
6 7
1
T X D
T X D _ I N
SCTE
6 4
6 5
7 7
7 6
7 4
S C T E
R X 2
T X 2
S C T E _ I N
7 0
7 1
TXC
7 0
6 8
6 7
7 3
2
R X 3
R X 2
T X C _ I N
T X 3
T X 2
T X C
R X C
R X D
7 1
6 4
6 5
7 7
7 6
RXC
RXD
7 4
1
R X C _ I N
R X D _ I N
6 3
6 2
7 8
7 9
6 0
R X 1
T X 1
XRT4500
XRT4500
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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The important things to note about Figure 20 are as
follows.
6. Because the DTE provides the SCTE clock signals
and since the falling edge of this clock signal will oc-
cur at the middle of the bit-period (for the signal on
the TXD line); the “3-Clock DTE/DCE Interface” is
largely immune to the affects of propagation delay
(via the DCE SCC to DTE SCC” link and the “DTE
SCC to DCE SCC” link), and will operate properly
over a very wide range of data rates.
1. The DCE Terminal is the ultimate source of all
clock signals.
2. The DCE Serial Communications Controller (SCC)
will transmit the TXC clock signal to the DTE node.
3. The DTE SCC will update the state on the TXD
line, upon the rising edge of the “incoming” TXC clock
signal when ‘Clock Invert’ is not activated.
Figure 21 presents an illustration of the wave-forms of
the signals that are transported across a “3-Clock
DTE/DCE” Interface. Further, this figure indicates that
a “3-Clock DTE/DCE” Interface provides the DCE
SCC with a TXD to TXC set-up time of “one-half” of
the bit-period (0.5 * tb). Hence, a “3-Clock DTE/DCE”
Interface can support very wide range of data rates,
and still insure that the DCE SCC will be provided a
sufficient “TXD to TXC” set-up time.
4. The DTE SCC will generate the rising edge of the
SCTE clock signal, upon receipt of the rising edge of
the “incoming” TXC clock signal when clock invert is
not activated.
5. The DCE SCC will use the falling edge of the
SCTE clock signal in order to sample the “incoming”
TXD signal.
FIGURE 21. ILLUSTRATION OF THE WAVE-FORMS OF THE SIGNALS THAT ARE TRANSPORTED ACROSS A “3-CLOCK
DTE/DCE” INTERFACE
TXC (at DCE)
TXC (at DTE)
SCTE (at DTE)
SCTE (at DCE)
TXD (at DTE)
TXD (at DCE)
0.5*tb
The “2-Clock” DTE/DCE Interface
Communications Equipment Manufacturers design
their DCE or DTE equipment to only support the
transmission of two clocks over the DTE/DCE Inter-
face; these two clocks signals are typically the “TXC”
(Transmit Clock) and the “RXC” (Receive Clock) sig-
nals. Figure 22 presents an illustration of a DTE and
DCE exchanging data over a “2-Clock DCE/DTE” In-
terface.
Although the Data Communications standards rec-
ommends the use of these three clock signals; in
practice, some Data Communications Equipment
manufacturers will build equipment that only supports
the transmission of “2-Clock” signals. The reason for
this can be due to cost, or due to the fact that the Da-
ta Communications Equipment manufacturer is using
an SCC that only handles 2-clock signals. When Data
NOTE: In the “2-Clock DTE/DCE” Interface, the DTE Termi-
nal does not supply the SCTE clock signal back to the DCE.
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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FIGURE 22. ILLUSTRATION OF A “2-CLOCK DTE/DCE” INTERFACE
SCC (L)
D T E
T X 1
D C E
R X 1
SCC (R)
2
TXD
6 3
6 2
7 8
7 9
6 0
6 7
1
T X D
T X D _ I N
6 4
6 5
7 7
7 6
7 4
S C T E
R X 2
T X 2
S C T E _ I N
7 0
7 1
TXC
7 0
6 8
6 7
7 3
R X 3
T X C _ I N
T X 3
T X C
R X C
R X D
7 1
6 4
6 5
7 7
7 6
RXC
RXD
7 4
1
R X 2
R X C _ I N
R X D _ I N
T X 2
6 3
6 2
7 8
7 9
6 0
R X 1
T X 1
XRT4500
XRT4500
Since the DTE SCC will not provide the DCE SCC
2. The DCE SCC will use the falling edge of the (lo-
cally generated) TXC clock signal in order to sample
the “incoming” TXD signal.
with the SCTE signal, the DCE SCC will have to use
a different clock signal in order to sample the “incom-
ing” data on the TXD line. A common approach, in
this case, is to simply “hard-wire” the “TXC” output
signal to the “SCTE” input pin of the DCE SCC) and
to use the falling edge of the TXC clock signal in order
to sample the “incoming” data on the TXD line, as il-
lustrated above in Figure 1.8.
Unlike the “3-Clock DTE/DCE” Interface, the “2-Clock
DTE/DCE” Interface is sensitive to the “round-trip”
propagation delay between the DCE and the DTE
Terminals (due to the cable, components comprising
the DCE and DTE Terminals, etc.) An example of this
sensitivity is presented below.
NOTE: There are numerous bad things about designing
DCE Equipment, per the illustration in Figure 1.9. In addi-
tion to the reasons presented below, since the DCE SCC is
now “hard-wired” to use the “TXC” as the means to sample
the “incoming” “TXD” signal, this approach is not flexible if
the user is interfacing to a DTE that happens to support “3-
Clock” signal. In this case, the user is advised to consider
using the “2-Clock” Mode feature (which is also offered by
the XRT4500) and is discussed in Section 1.2.5.
Case 1 - “2-Clock DTE/DCE” Operation at
1.0Mbps
Consider the case where the DCE and DTE are ex-
changing data at a rate of 1.0Mbps. Further, let's con-
sider that the total propagation delay from the DCE to
the DTE is 160 ns. Likewise, let's consider that the to-
tal propagation delay from the DTE to the DCE is also
160ns. Given these conditions, Figure 23 plots out
the clock and signal wave-forms for the TXC and TXD
at both the DCE and DTE SCCs.
Important things to note about Figure 1.9.
1. The DTE SCC will not supply the SCTE signal to
the DCE SCC.
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FIGURE 23. THE BEHAVIOR OF THE TXC AND TXD SIGNALS AT THE DCE AND DTE SCCS, (DATA RATE =
1.0MBPS, “DCE-TO-DTE” PROPAGATION DELAY = 160NS, “DTE-TO-DCE” PROPAGATION DELAY = 160NS)
1us
500ns
TXC (at DCE)
TXC (at DTE)
TXD (at DTE)
TXD (at DCE)
180ns
Figure 23 indicates that the TXC (Transmit Clock) sig- DCE” propagation delays are each 160ns, then the
nal will originate at the DCE SCC terminal. However,
because of the “DCE-to-DTE” propagation delay, the
TXC signal will arrive at the DTE SCC 160ns later.
Per the various “Communication Interface Standards”
(e.g., EIA-530A, etc.), the DTE must update the data
on the “TXD” line upon detection of the rising edge of
the “incoming” TXC clock signal. Hence, Figure 1.10
illustrates the DTE SCC toggling the TXD line coinci-
dent with the rising edge of TXC. Finally, because of
the “DTE to DCE” propagation delay, the TXD signal
will arrive at the DCE SCC 160 ns later.
DCE SCC will be provided with 180ns of set-up time,
(in the TXD line) prior to sampling the data. For most
digital IC’s, this amount of set-up time is sufficient
long and should not result in any bit errors.
Case 2 - “2 Clock DCE/DTE” Operation at 1.544
Mbps
Now let's consider the case where the DCE and DTE
Terminals are now exchanging data at a rate of
1.544Mbps (e.g., the DS1 rate). Further, let's consid-
er that the “DCE-to-DTE” and “DTE-to-DCE” propa-
gation delays are each 160ns (as in the prior case).
Given these conditions, Figure 24 illustrates the re-
sulting clock and signal wave-forms for the TXC and
TXD at both the DCE and DTE SCCs.
Recall that the DCE SCC is using the TXC clock sig-
nal to sample the data on the “incoming” TXD line.
The scenario depicted in Figure 1.10 indicates that if
the Data Rate (between the DCE and DTE) is
1.0Mbps; and that if the “DCE to DTE” and “DTE to
FIGURE 24. THE BEHAVIOR OF THE TXC AND TXD SIGNALS AT THE DCE AND DTE SCCS (DATA RATE =
1.544MBPS, DCE-TO-DTE PROPAGATION DELAY = 160NS, DTE-TO-DCE PROPAGATION DELAY = 160NS)
648ns
324 ns
TXC (at DCE)
TXC (at DTE)
TXD (at DTE)
TXD (at DCE)
4ns
The scenario depicted in Figure 24 indicates that if
the Data Rate (between the DCE and the DTE) is
1.544Mbps and that if the “DCE-to-DTE” and the
“DTE-to-DCE” propagation delays are each 160ns,
then the DCE SCC will be provided with 4ns of set-up
time (in the TXD line) prior to sample the data. For
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some digital Is, this amount of set-up time is marginal
and is likely to result in bit-errors. Throughout the re-
mainder of this document, this phenomenon will be
referred to as the “2-Clock/Propagation Delay” phe-
nomenon.
face” is a much more robust and reliable medium to
transport data, than is the “2-Clock DTE/DCE” Inter-
face.
Using the “Echo-Clock” Feature within the
XRT4500
Cases 1 and 2 indicate that if a wide range of data
rates are to be supported by some Data Communica-
tion Equipment over a “2-Clock DTE/DCE” Interface'
and if the propagation delays are sufficiently large (in
the “DCE-to-DTE” and “DTE-to-DCE” link); then there
are some data rates that will be handled in an “error-
free” manner; and other data rates which are prone to
errors. Consequently, the “3-Clock DTE/DCE Inter-
The “Echo-Clock” features within the XRT4500 helps
to mitigate the “2-Clock/Propagation Delay” phenom-
enon by forcing the DTE Mode XRT4500 to supply an
additional clock signal (over the DTE/DCE Interface),
over and above that provided by the DTE SCC.
Figure 25 presents an illustration of the “Echo Clock”
feature (within the DTE Mode XRT4500) being used.
FIGURE 25. ILLUSTRATION OF THE “ECHO-CLOCK” FEATURE WITHIN THE XRT4500
SCC (L)
D T E
D C E
R X 1
SCC (R)
TXD
7 8
7 9
6 3
6 2
6 0
6 7
1
T X D
T X D _ I N
T X 1
SCTE
6 4
6 5
7 7
7 6
7 4
S C T E
R X 2
T X 2
S C T E _ I N
7 0
7 1
TXC
7 0
6 8
6 7
7 3
R X 3
T X 3
T X C _ I N
T X C
R X C
R X D
7 1
6 4
6 5
7 7
7 6
RXC
RXD
7 4
1
R X 2
R X C _ I N
R X D _ I N
T X 2
6 3
6 2
7 8
7 9
6 0
R X 1
T X 1
XRT4500
XRT4500
In the example, presented in Figure 25, the DTE SCC
does not supply the SCTE signal to the DTE/DCE In-
terface (just as in the two previous examples). How-
ever, in this case, the XRT4500 (on the DTE side) has
been configured to operate in the “Echo-Clock” Mode.
While the XRT4500 is operating in this mode, it will
simply take the “incoming” Transmit Clock signal
(TXC) and will “echo” it back to the SCTE input pin of
the DCE SCC. If we were to closely analyzer the
clock signals that are transported across the “DTE/
DCE” Interface, in order to determine the resulting
“TXC to TXD set-up time”, we would observe the fol-
lowing.
2. The DTE SCC will update the state of the TXD line
on the rising edge of the “incoming” TXC clock signal.
3. The “DTE” XRT4500 will “internally” route the
“RX3D” output signal to the TX2D output signal. As a
consequence, the incoming TXC clock signal will be
“echoed” back out to the SCTE input pin of the DCE
SCC.
4. If we neglect the “Clock-to-Output” delay of the
DTE SCC, the DCE SCC will receive the falling edge
of the SCTE clock signal, very close to the middle of
the bit-period of each bit on the TXD line.
This phenomenon is also illustrated below in
Figure 26.
1. The DCE SCC sources the TXC clock signal to the
DTE node.
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FIGURE 26. ILLUSTRATION OF THE WAVE-FORMS, ACROSS A DCE/DTE INTERFACE, WHEN THE ECHO-CLOCK FEATURE
(WITHIN THE XRT4500) IS USED AS DEPICTED IN FIGURE 25
TXC (at DCE)
TXC (at DTE)
SCTE (at DTE)
SCTE (at DCE)
TXD (at DTE)
TXD (at DCE)
0.5*tb
By using the “Echo-Clock” feature, within the
XRT4500, the “Overall System” (comprised of the
DTE and DCE Terminals) is nearly as immune to the
“2-Clock/Propagation Delay” phenomenon, as is the
“3-Clock DTE/DCE Interface”; even though the DTE
SCC only processes two clock signals.
tion Delay” phenomenon. The “Echo-Clock” Mode is
an approach that can be used to attack this phenom-
enon, if the XRT4500 is designed into a DTE Equip-
ment. However, if a system manufacturer, of DCE
Equipment, encounters this problem, one is not able
to configure a way out of this phenomenon by en-
abling the “Echo-Clock” Mode. Fortunately, the
XRT4500 does offer the “DCE Equipment” design a
couple of another options which can be used to miti-
gate the “2-Clock/Propagation Delay” phenomenon.
These two features are:
Hence, in short, the purpose of the Echo-Clock Mode
is to provide the “Overall-System” with the SCTE
clock signal, when it is not being supplied by the DTE
SCC. The impact of being able to accomplish this is a
more robust, reliable system performance.
• The “2-Clock/3-Clock Mode” Feature
• The “Clock Inversion” Feature
Configuring the Echo-Clock Mode
The user can configure the “Echo-Clock” Mode, with-
in the XRT4500, by pulling the “EC” input pin (pin 34)
“low”. Conversely, the user can disable the “Echo-
Clock” Mode by pulling the “EC” input pin “high”.
This section discusses the “2-Clock/3-Clock” Feature.
As mentioned above, if the DTE/DCE Interface only
consists of two clock signals, (e.g., missing the SCTE
signal), then there will be some data rates at which
the DCE SCC will not be provided with sufficient set-
up time, when sampling the TXD signal.
When the “EC” input pin is pulled “low”, then the
XRT4500 will internally use the “TXC” digital signal
(which is output, from the DTE Mode XRT4500, via
the RX3D output pin) as the source for the “SCTE” (or
the TX2D) signal.
Figure 27 presents an illustration of two XRT4500 be-
ing implemented in a “DTE/DCE” Interface. In this fig-
ure, the “DCE Mode” XRT4500 has been configured
to operate in the “2-Clock” Mode. When the XRT4500
is configured to operate in the “2-Clock” Mode, then it
will internally use the “TXC” signal as a means to syn-
thesize the “SCTE” clock signal (as depicted below).
NOTE: The “Echo-Clock” Mode is only available if the
XRT4500 is operating the DTE Mode.
1.3.5 The “2CK/3CK” (2-Clock/3-Clock Mode -
Enable/Disable Select Input pin)
Section 1.3.4 discusses the “Echo-Clock” Mode, and
how it can be used to combat the “2-Clock/Propaga-
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FIGURE 27. ILLUSTRATION OF THE DCE/DTE INTERFACE, WITH THE DCE MODE XRT4500 OPERATING IN THE “2-
CLOCK” MODE
SCC (L)
D T E
D C E
R X 1
SCC (R)
T X D
78
79
63
62
60
67
1
T X D
T X D _ I N
T X 1
64
65
77
76
74
S C T E
R X 2
T X 2
S C T E _ I N
T X C
R X C
R X D
70
71
70
71
68
67
60
73
74
R X 3
T X C _ I N
T X 3
T X C
R X C
R X D
64
77
76
R X 2
R X C _ I N
R X D _ I N
T X 2
65
63
62
78
79
1
R X 1
T X 1
XRT4500
XRT4500
In this case, the “2-Clock” Mode offers a considerable
amount of design flexibility. This approach permits the
“DCE Equipment” System Design Engineer to design
and layout a board that can be automatically config-
ured to support either the “3-Clock” Mode (if all three
clock signals are present, over the DTE/DCE Inter-
face). Further, this approach also permits the System
Design Engineer to configure the XRT4500 into the
“2-Clock” Mode (if the SCTE clock signal is not
present). This feature is a nice alternative to “hard-
wiring” the “TXC” output (of the DCE SCC) to the
“SCTE” input.
DTE that only supports two (2) clock signals. Once
the user has configured the XRT4500 to operate in
the “2-Clock” Mode, then the user can “solve” the “2-
Clock/Propagation Delay” phenomenon by invoking
the “Clock Inversion” feature, as described below in
Section 1.2.6.
Configuring the “2-Clock” Mode.
The user can configure the XRT4500 to operate in
the “2-Clock” Mode by setting the “2CK/3CK” input
pin “high”. Conversely, the user can disable the “2-
Clock” Mode (otherwise known as operating the
XRT4500 in the “3-Clock” Mode) by setting the “2CK/
3CK” input pin “low”.
NOTE: The “2-Clock” Mode feature, by itself, does not solve
the “2-Clock/Propagation Delay” phenomenon. However,
the “2-Clock” Mode, within the XRT4500, permits the user
to do the following.
1.3.6 The “Clock Inversion” (CK_INV) feature
The XRT4500 can be configured to invert the “TXC”
signal by setting the “CK_IN” input pin (pin 54) “low”.
Setting the “CK_INV” input to “high” removes the in-
vert from the “TXC” signal path. An illustration of the
“DCE Mode” XRT4500, configured to invert the “TXC”
signal is illustrated in Figure 28.
a. To configure the XRT4500 to automatically operate
in the “3-Clock” Mode, whenever it is interfaced to a
DTE that supports all three (3) clock signals, or
b. To configure the XRT4500 to automatically operate
in the “2-Clock” Mode, whenever it is interfaced to a
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FIGURE 28. ILLUSTRATION OF THE DCE MODE XRT4500 BEING CONFIGURED TO INVERT THE TXC SIGNAL
D T E
D C E
SCC (R)
SCC (L)
T X D
78
79
63
62
60
67
1
T X D
R X 1
R X 2
T X D _ I N
T X 1
S C T E
64
65
77
76
74
S C T E
T X 2
S C T E _ I N
T X C
R X C
R X D
70
71
70
68
67
60
73
74
R X 3
T X 3
T X C _ I N
R X C _ I N
R X D _ I N
T X C
71
64
65
77
76
R X 2
T X 2
R X C
63
62
78
79
1
R X 1
T X 1
R X D _ O U T
XRT4500
XRT4500
The “Clock Inversion” feature is also available if the
XRT4500 is operating in the “DTE” Mode. Figure 29
presents an illustration of a DTE Mode XRT4500,
when it is configured to invert the TXC clock signal.
FIGURE 29. ILLUSTRATION OF THE DTE MODE XRT4500 BEING CONFIGURED TO INVERT THE TXC SIGNAL
SCC (L)
SCC (R)
D T E
D C E
78
79
T X D
63
62
60
67
1
T X D
R X 1
T X D _ I N
T X 1
T X 2
SCTE
77
76
64
65
74
S C T E
R X 2
S C T E _ I N
T X C
70
71
70
71
73
74
68
67
60
R X 3
T X 3
T X C _ I N
R X C _ I N
R X D _ I N
T X C
R X C
R X D
64
R X C
R X D
77
76
R X 2
R X 1
T X 2
T X 1
65
63
62
78
79
1
XRT4500
XRT4500
The Benefits of the “Clock Inversion” Feature
ture was also presented as a possible solution to the
“2-Clock/Propagation Delay” phenomenon. However,
the “Echo-Clock” feature has a drawback. If a “DCE
Equipment” manufacturer were to interface his/her
equipment to a DTE Terminal that does not support
In Section 1.3.4 of this document, a lengthy discussion,
regarding the “2-Clock/Propagation Delay” phenomenon
is presented. In this Section, the “Echo-Clock” Fea-
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the SCTE clock signal; it is highly unlikely that the
“DCE Equipment” manufacturer will be able to (over
the DTE/DCE Interface) invoke the “Echo-Clock”
mode and resolve the “2-Clock/Propagation Delay”
phenomenon.
Clock/Propagation Delay” phenomenon. By doing the
following things.
a. Configuring the DCE Mode XRT4500 to operate in
the “2-Clock” Mode, and
b. Inverting the TXC signal, within the DCE Mode
XRT4500, the user can largely resolve the “2-Clock/
Propagation Delay” phenomenon.
NOTE: This is especially the case if the DTE Equipment is
not using the XRT4500 as the Multi-protocol Transceiver IC.
As a consequence, the “DCE Equipment” manufac-
turer would have to resort to undesirable things, such
as using the (locally generated) TXC signal as the
sampling clock for the “TXD” signal.
Figure 30 presents an illustration of the DCE Mode
XRT4500, being configured to (1) operate in the “2-
Clock” Mode, and (2) to invert the “TXC” signal.
However, the XRT4500 does offer the DCE Equip-
ment manufacturer an elegant solution to the “2-
FIGURE 30. ILLUSTRATION OF THE DCE MODE XRT4500, WHICH IS OPERATING IN THE “2-CLOCK” MODE, AND
INVERTING THE “TXC” SIGNAL
SCC (L)
D T E
T X 1
D C E
SCC (R)
T X D
78
79
63
62
60
67
1
T X D
R X 1
R X 2
T X D _ I N
S C T E
64
65
77
76
74
S C T E
T X 2
S C T E _ I N
T X C
R X C
R X D
70
71
70
68
67
60
73
74
R X 3
T X 3
T X C _ I N
R X C _ I N
R X D _ I N
T X C
71
64
65
77
76
R X 2
T X 2
R X C
63
62
78
79
1
R X 1
T X 1
R X D _ O U T
XRT4500
XRT4500
By taking advantage of both the “2-Clock” Mode and
the ability to invert the “TXC” clock signal, the “DCE
Equipment” manufacture can mitigate the “2-Clock/
Propagation Delay” phenomenon by simply inverting
the “TXC” whenever the DTE/DCE Interface and sys-
tem configuration settings begin to violate the “TXD to
TXC” set-up time requirement of the DCE SCC de-
vice. By inverting the TXC signal, the phase relation-
ship, between the “TXD and the TXC signal will shift
by 180 degrees. At this point, the sampling edge of
the TXC signal will be near the middle of the “TXD”
bit-period, and the system will not be violating the
“TXD to TXC” set-up time requirements of the DCE
SCC device.
In summary, the “2-Clock” Mode (within the
XRT4500) provides the user with the following op-
tions.
The DCE Equipment (which uses the XRT4500) can
easily be configured to interface to DTE Equipment
that supports the SCTE clock signal, as well as DTE
Equipment that does not support the SCTE clock sig-
nal. If the DCE Equipment is being interfaced to a
DTE which supports the SCTE clock signal, then the
DCE Equipment should configure the XRT4500 to op-
erate in the “3-Clock” Mode. Conversely, if the DCE
Equipment is being interfaced to a DTE which does
not support the SCTE clock signal, then the DCE
Equipment should configure the XRT4500 to operate
in the “2-Clock” Mode. This step will automatically
configure the XRT4500 to route the “TXC” clock sig-
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nal to the “SCTE_IN” input pin of the DCE SCC.
The user disables the “LATCH” feature by driving the
There is no need to design in extra glue logic to multi- “LATCH” input pin, from “high” to “low”. Once the
plex the “SCTE” output pin of the XRT4500 with the
TXC output pin of the DCE SCC.
“LATCH” input pin is “low”, then the behavior of the
XRT4500 will be dictated by the state of the “M[2:0]”
input pins.
Additionally, if the DCE Equipment is being interfaced
to a DTE Terminal which does not support the SCTE
signal, (e.g., the XRT4500 is now operating in the “2-
Clock” Mode), and if the “DCE/DTE Interface” config-
uration settings are such that the “TXD-to-TXC” set-
up time requirements of the DCE SCC are being vio-
lated, then the user can eliminate this problem by in-
voking the “Clock Invert” feature of the XRT4500.
1.3.8 The Registered Mode of Operation
The XRT4500 includes a feature which is known as
“Registered Mode” operation. The user can enable
the “Registered” Mode by setting the “REG” input pin
“HIGH”. Conversely, the user can disable the “Regis-
tered” Mode by setting the “REG” input pin “LOW”.
If the user enables the “Registered” Mode, then the
following things will happen.
1.3.7 The Latch Mode of Operation
The Latch Mode of operation permits the user to latch
the state of the “Mode Control” input pins (M[2:0]) into
the XRT4500 internal circuitry. This feature frees up
of the signals, driving the M[2:0] input pins (pins 6, 5,
and 4) for other purposes.
a. The XRT4500 will be configured to sample and
latch the contents of the “TX5D” and “TX8D” input
pins, upon the rising edge of the “REG_CLK” input
signal.
b. The XRT4500 will be configured to output data (to
the SCC) via the “RX5D” and “RX8D” output pins, up-
on the rising edge of the “REG_CLK” signal.
Because of this feature, it is permissible to control the
state of the “M[2:0]” input pins via certain signals
within a bi-directional data bus (which is controlled by
a microprocessor or microcontroller).
This feature is useful in application, which use a SCC
or a Microcontroller (that requires an external clock
signal to sample the “DSR” and the “RI” (or “TM”) sig-
nals. Further, this feature also configures the
XRT4500 to sample the state of the “DTR” and the
“RL” signal upon the rising edge of an external clock
signal.
The user invokes this feature by driving the “LATCH”
input pin (pin 44) from “low” to “high”. During this
“low” to “high” transition, the contents of the “M[2:0]”
input pins will be “locked” (or latched) into internal cir-
cuitry within the XRT4500. At this point (as long as
the “LATCH” input pin remains “high”) the user's sys-
tem can do other things with the signal which are also
driving the “M[2:0]” without affecting the behavior the
XRT4500.
If the user invokes this feature, then the relationship
between the XRT4500 and the SCC/Microprocessor
is as depicted below in Figure 31.
FIGURE 31. AN ILLUSTRATION OF THE EFFECTIVE INTERFACE BETWEEN THE XRT4500 AND THE SCC/MICROPRO-
CESSOR WHEN THE “REGISTERED” MODE IS ENABLED
XRT4500
DTR_Signal
TX5D
DSR_Signal
RX5D
µ µ
C P
/
RL_Signal
TX8D
RX8D
RI_Signal
REG_CLK
External Clock
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A system design similar to that presented below in
lationship between another Multi-protocol Transceiver
Figure 32, will accomplish the exact same function/re- IC and the SCC/Microprocessor.
FIGURE 32. AN ILLUSTRATION OF THE NECESSARY GLUE LOGIC REQUIRED TO DESIGN A FEATURE SIMILAR TO THAT
OFFERED BY THE “REGISTERED” MODE, WHEN USING A DIFFERENT MULTI-PROTOCOL SERIAL NETWORK INTERFACE IC
DTE Mode
D-Flip-Flops
Serial
Network
µC/µP
Interface Device
DTR_Signal
Q
C L K
DSR_Signal
Q
C L K
RL_Signal
Q
C L K
RI_Signal
Q
C L K
Clock
Clock Source
1.3.9 The Internal Oscillator
the “Internal Oscillator” feature by pulling the
“OSC_EN” input pin “high”.
The XRT4500 includes an “Internal Oscillator” that
can be used to support “DTE Stand-Alone Testing/
Diagnostics” operations.
If the user enables this feature, then the XRT4500 will
synthesize a clock signal (of frequencies ranging from
32kHz to 64kHz). Further, this clock signal will be out-
put via the “RX2D” and the “RX3D” output pins. Fig-
ure 1.20 presents an illustration of the XRT4500
(while interfaced to the DTE SCC) when the Internal
Oscillator is enabled.
The user can enable the “Internal Oscillator” feature
(within the XRT4500) by pulling the “OSC_EN” input
pin (pin 53) “low”. Conversely, the user can disable
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FIGURE 33. ILLUSTRATION OF THE INTERNAL OSCILLATORS WITHIN THE XRT4500
D T E
SCC (L)
T X D
T X D
T X 1
T X 2
S C T E
S C T E
T X C
73
74
O S C
R X 3
R X 2
T X C _ I N
R X C
R X D
O S C
R X C _ I N
R X D _ I N
R X 1
XRT4500
If the user enables the Internal Oscillator, within the
XRT4500, then the XRT4500 will output between a
32kHz and a 64kHz clock signal via the RX2D and
RX3D signals. When the XRT4500 is interfaced to the
DTE SCC, this translates into the XRT4500 generating
the timing signals for “TXC” and the “RXC” input signals.
As a consequence, the DTE SCC is provided with all of
the requisite timing signals that it would normally have, if
it were interfaced to a DCE Terminal. This feature per-
mits the user to implement a wide variety of diagnostic
programs for DTE Equipment stand-alone testing.
the DTINV* input to logic 0 enables an inverter at the
output of RX1 and input of TX1.
1.3.12 Data Interlude
Similar to TXC, there is a provision in the XRT4500 to
invert the TXD and RXD signals. Once the Setting the
DTINV* input to logic 0 enables an inverter at the out-
put of RX1 and input of TX1.
2.0 RECEIVER AND TRANSMITTER
SPECIFICATIONS
Table 3 and Table 4, which are for the XRT4500 re-
ceiver and transmitter sections respectively, summa-
rize the electrical requirements for V.35, V.11, V.10,
and RS232 interfaces. These tables provide virtually
all of the electrical information necessary to describe
these 4 interfaces in a concise form.
NOTE: The Internal Oscillator feature is only available if the
XRT4500 has been configured to operate in the DTE Mode.
1.3.10 Glitch Filters
Occasional extraneous glitches on control/handshake
signal inputs such as CTS, RTS, DTR and DSR can
have damaging effects on the integrity of a connection.
The XRT4500 is equipped with lowpass filters on the
input of each of the receivers for the control and
handshake signals. These filters eliminate glitches
which are narrower than 10µs. The user may disable
these filters by setting EN_FLTR to logic 0.
3.0 V.10\V.28 OUTPUT PULSE RISE AND FALL
TIME CONTROL
SLEW_CNTL (pin 47) is an analog output that con-
trols transmitter pulse rise and fall time for the V.10
and V.28 modes. Connecting a resistor, RSLEW, hav-
Ω
ing a value between 0 and 200 k from this pin to
ground controls the rise/fall times for V.10 and the
slew rate for V.28 as shown in Figure 34 and
Figure 35 respectively.
1.3.11 Data Inversion
Similar to TXC, there is a provision in the XRT4500 to
invert the TXD and RXD signals. Once the Setting
60
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
FIGURE 34. V.10 RISE/FALL TIME AS A FUNCTION OF RSLEW
3
1 10
100
10
1
100K
1 Meg
10K
R (Ohms)
FIGURE 35. V.28 SLEW RATE OVER ± 3 V OUTPUT RANGE WITH 3 KΩ IN PARALLEL WITH 2500 PF LOAD AS A
FUNCTION OF RSLEW
10
V.
28
Sle
w
1
Ra
te
(V/
us)
0.1
0.01
10K
100K
1 Meg
R (Ohms)
4.0 THE HIGH-SPEED RS232 MODE
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
When E_232H (pin 55) is set to logic 0 in RS232 mode,
the transmitters are configured to operate in a special
and transmitter output terminations respectively. Ad-
ditionally, Tables 4 and 5 provide a summary of re-
ceiver and transmitter specifications respectively for
the different electrical modes of operation.
Ω
high-speed RS232 mode that can drive loads of 3000
in parallel with 1000pF at speeds up to 256 KHz.
V.10 (RS423) Interface
5.0 INTERNAL CABLE TERMINATIONS
XRT4500 has fully integrated receiver and transmitter
cable terminations for high speed signals (RXD, TXD,
RXC, TXC, SCTE). Therefore, no external resistors
Figure 28 shows a typical V.10 (RS423) interface.
This configuration uses an unbalanced cable to con-
nect the transmitter TXA output to the receiver RXA
and/or switches are necessary to implement the prop- input. The “B” outputs and inputs that are present on
er line termination. The schematic diagrams given in
Figures 26 and 27 show the effective receiver and
transmitter terminations respectively for each mode of
operation. When a specific electrical interface is se-
lected by M0, M1 and M2, the termination required for
that interface is also automatically chosen. The
XRT4500 eliminates double termination problems
and makes point to midpoint operation possible in the
V.11 mode by providing the option for disabling the in-
ternal input termination on high speed receivers.
the differential transmitters and receivers contained in
the XRT4500 are not used. The system ground pro-
vides the signal return path. The receiver input resis-
Ω
tance is 10 k nominal and no other cable termina-
tion is normally used for the V.10 mode.
V.11 (RS422) Interface
Figure 29 shows a typical V.11 (RS422) interface. This
configuration uses a balanced cable to connect the
transmitter TXA and TXB outputs to the receiver RXA
and RXB inputs respectively. The XRT4500 includes
6.0 OPERATIONAL SCENARIOS
Ω
provisions for adding a 125 terminating resistor for
Visualizing features such as clock/data inversion,
echoed clock, and loopbacks, in DTE and DCE
modes makes configuring the XRT4500 a non-trivial
task. A series of 48 system level application diagrams
located at the end of the data sheet called “Scenari-
os” assist users in understanding the benefits of
these different features. The internal XRT4500 con-
nections required for a particular scenario are made
through MUX1 and MUX2 that are shown on the
block diagrams given in Figures 2 and 3 respectively.
Table 8 contains the signal routing information versus
control input logic level for MUX1 and Table 9 con-
tains similar information for MUX2.
the V.11 mode. Although this resistor is optional in the
V.11 specification, it is necessary to prevent reflections
that would corrupt signals on high-speed clock and data
lines. The differential receiver input resistance without
Ω
the optional termination is 20 k nominal.
V.28 (RS232) Interface
Figure 28 shows a typical V.28 (RS232) interface.
This configuration uses an unbalanced cable to con-
nect the transmitter TXA output to the receiver RXA
input. The “B” outputs and inputs that are present on
the differential transmitters and receivers contained in
the XRT4500 are not used. The system ground pro-
vides the signal return path. The receiver “B” input is
internally connected to a 1.4 V reference source to
provide a 1.4 V threshold. The receiver input resis-
7.0 APPLICATIONS INFORMATION
Traditional interfaces either require different transmit-
ters and receivers for each electrical standard, or use
complicated termination switching methods to change
modes of operation. Mechanical switching schemes,
which are expensive and inconvenient, include relays,
and custom cables with the terminations located in
the connectors. Electrical switching circuits using
FETs are difficult to implement because the FET
must remain off when the signal voltage exceeds the
supply voltage and when the interface power is off.
Ω
tance is 5 k nominal and no other cable termination
is normally used for the V.28 mode.
V.35 Interface
Figure 30 shows a typical V.35 interface. This configu-
ration uses a balanced cable to connect the transmit-
ter TXA and TXB outputs to the receiver RXA and
RXB inputs respectively. The XRT4500 internal termi-
nations meets the following V.35 requirements. The
Ω
Ω
receiver differential input resistance is 100 ± 10
The XRT4500 uses innovative, patented circuit de-
sign techniques to solve the termination switching
problem. It includes internal circuitry that may be con-
trolled by software to provide the correct terminations
for V.10 (RS423), V.11 (RS422), V.28 (RS232), and
V.35 electrical interfaces. The schematic diagrams
given in Figures 26 and 27 conceptually show the
switching options for the high-speed receiver input
and the shorted-terminal resistance (RXA and RXB
Ω
Ω
connected together) to ground is 150 ± 15 . The
Ω
transmitter differential output resistance is 100 ± 10
Ω
and the shorted-terminal resistance (TXA and TXB
Ω
Ω
connected together) to ground is 150 ± 15 .
The junction of the 3 resistors (CMTX) on the transmit
termination is brought out to pins 61 and 66 for TX1
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
and TX2 respectively. Figure 30 shows how capacitor
C having a value of 100 to 1000 pF bypasses this
point to ground to reduce common mode noise. This
capacitor shorts current caused by differential driver
rise and fall time or propagation delay miss-match di-
rectly to ground. If it was not present, the flow of this
Ω
current through the 125 resistor to ground would
cause common mode voltage spikes at the TXA and
TXB outputs.
FIGURE 36. RECEIVER TERMINATION
RXxA
R9
4K
RXxB
R1
20
R10
4K
Rx
R2
20
S3
R3
85
R11 R12
R8
10K
6K
6K
S2
S1
S4
R4
30
R4
30
R6
125
TABLE 6: RECEIVER SWITCHES
SWITCHES
MODE
S1
S2
S3
S4
V.35
V.11 Terminated
V.11 Unterminated
V.10
Closed
Open
Open
Open
Open
Closed
Open
Open
Open
Open
Open
Closed
Open
Open
Open
Open
Open
Open
Open
Closed
V.28
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
FIGURE 37. TRANSMITTER TERMINATION
TXxB
TXxA
TX
S2
S1
R1
50
R2
50
R3
125
TABLE 7: TRANSMITTER SWITCHES
SWITCHES
MODE
S1
S2
V.35
Closed
Open
Closed
Open
V.11/V.10/V.28
FIGURE 38. TYPICAL V.10 OR V.28 INTERFACE (R1 = 10 KΩ IN V.10 AND 5 KΩ IN V.28)
FIGURE 39. TYPICAL V.11 INTERFACE (TERMINATION RESISTOR, R1, IS OPTIONAL.)
64
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
FIGURE 40. TYPICAL V.35 INTERFACE
0.1uf
NOTE: All Resistors shown above are internal to the
XRT4500
TABLE 8: MUX1 CONNECTION TABLE
LOGIC LEVEL APPLIED TO CONTROL INPUT
NAME/PIN NUMBER
SIGNAL SOURCE FOR OUTPUT NAME/PIN NUMBER
SCENARIO
NUMBER
DCE/
DTE
31
EC
2CK/
3CK
50
LP
CK
INV
54
DT EN_O
INV
SC
RX1D
1
TX1B-TX1A
62, 63
RX2D
74
TX2B-TX2A
65, 64
RX3D
73
TR3B-TR3A
71, 70
55
53
34
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
18
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
TX1D
RX2B-RX2A
RX2B-RX2A
TX2D
TX2D
TR3B-TR3A
X
TX2D
X
TX3D
3
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
TR3B-TR3A
X
4
TX1D
TX2D
RX2B-RX2A
X
TX3D
5
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
RX2B-RX2A
TX2D
TX2D
(TR3B-TR3A)*
X
6
TX1D
TX2D
X
(TX3D)*
7
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
(TR3B-TR3A)*
X
8
TX1D
TX2D
RX2B-RX2A
X
(TX3D)*
9
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
TX3D
X
TR3B-TR3A
X
10
11
12
13
14
15
16
17
18
19
20
TX1D
TX2D
X
TX3D
RX1B-RX1A
RX1B-RX1A
TX1D
TX2D
X
TR3B-TR3A
X
TX1D
TX2D
TX3D
X
TX3D
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
TX3D
X
(TR3B-TR3A)*
X
TX1D
TX2D
X
(TX3D)*
RX1B-RX1A
RX1B-RX1A
TX1D
TX2D
X
(TR3B-TR3A)*
X
TX1D
TX2D
TX3D
X
(TX3D)*
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
TX2D
X
TX2D
RX2B-RX2A
X
X
X
X
TX1D
X
TR3B-TR3A
X
RX1B-RX1A
RX1B-RX1A
TX2D
X
TX1D
TX2D
RX2B-RX2A
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
TABLE 8: MUX1 CONNECTION TABLE (CONTINUED)
LOGIC LEVEL APPLIED TO CONTROL INPUT
NAME/PIN NUMBER
SIGNAL SOURCE FOR OUTPUT NAME/PIN NUMBER
SCENARIO
NUMBER
DCE/
DTE
EC
2CK/
3CK
LP
CK
INV
DT EN_O
INV
SC
RX1D
1
TX1B-TX1A
62, 63
RX2D
74
TX2B-TX2A
65, 64
RX3D
73
TR3B-TR3A
71, 70
31
50
54
55
53
34
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
0
18
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
0
0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
0
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
RX1B-RX1A
RX1B-RX1A
TX1D
TX1D
TX1D
RX2B-RX2A
(TX2D)*
X
(RX2B-RX2A)*
X
TX2D
X
X
RX1B-RX1A
NOTE 1
TX1D
TX2D
X
(RX2B-RX2A)*
X
TX1D
TX2D
TX2D
X
X
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
RX2B-RX2A
TR3B-TR3A
TX3D
TR3B-TR3A
TX3D
TR3B-TR3A
X
TX1D
X
TR3B-TR3A
X
TX3D
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
RX2B-RX2A
X
TX1D
TX3D
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
RX2B-RX2A
(TR3B-TR3A)* (TR3B-TR3A)*
X
TX1D
TX3D
X
(TX3D)*
RX1B-RX1A (TR3B-TR3A)*
RX2B-RX2A
(TR3B-TR3A)*
X
TX1D
RX1B-RX1A
TX1D
TX3D
RX2B-RX2A
TX3D
RX2B-RX2A
X
(TX3D)*
RX1B-RX1A
RX1B-RX1A
TX1D
X
TX3D
X
TR3B-TR3A
X
TX1D
X
TX3D
RX1B-RX1A
RX1B-RX1A
TX1D
TR3B-TR3A
TX3D
TR3B-TR3A
X
TX1D
TX3D
X
X
TX3D
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
TX3D
(TR3B-TR3A)*
X
TX1D
TX3D
X
X
(TX3D)*
RX1B-RX1A (TR3B-TR3A)*
(TR3B-TR3A)*
X
TX1D
RX1B-RX1A
TX1D
TX3D
RX2B-RX2A
TX3D
TX3D
X
X
(TX3D)*
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
X
X
X
X
X
X
X
X
TX1D
TX3D
X
X
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
TX3D
RX2B-RX2A
TX1D
TX3D
X
X
RX1B-RX1A
RX1B-RX1A
TX1D
RX2B-RX2A
(TX3D)*
(RX2B-RX2A)*
TX1D
TX3D
X
X
RX2B-RX2A
X
RX1B-RX1A
NOTE 1
RX2B-RX2A
TX3D
TX1D
TX3D
INVERT
INVERT
UNCHANGED UNCHANGED UNCHANGED UNCHANGED
UNCHANGED UNCHANGED UNCHANGED UNCHANGED
UNCHANGED UNCHANGED 32-64 kHz UNCHANGED
32-64 kHz
32-64 kHz
UNCHANGED
UNCHANGED
NOTES:
2. Signal names ending with A or B are analog inputs
or outputs. Signal names ending with D are digital
1. Table entries are inputs to MUX1. Column headings
are outputs.
66
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
.
inputs or outputs. * indicates signal complement. X
is don't care.
TABLE 9: MUX2 CONNECTION TABLE (RX4-RX7, TX4-TX7), OUTPUT VERSUS INPUT
CONTROL INPUT/
PIN NUMBER
SIGNAL SOURCE FOR OUTPUT NAME/PIN NUMBER
SCENARIO
NUMBER
DCE/
DTE
TX4B-
TX4A
TX5B-
TX5A
LP
RX4D
RX5D
RX67D
TR6B-TR6A
TR7
31
18
40
10, 11
33
13, 12
32
30, 29
27
A
B
C
D
0
0
TX4D
RX4B-
RX4A
TX5D
TR6B-
TR6A
TX5D
X
TX76D
0
1
1
1
0
1
RX4B-
RX4A
TX4D
RX5B-
RX5A
TX5D
TR6B-
TR6A
X
TX76D
TX4D
RX4B-
RX4A
TX76D
RX5B-
RX5A
TR7
RX5B-RX5A
TX76D
X
X
RX4B-
RX4A
TX4D
RX5B-
RX5A
TX5D
TR7
NOTES:
• Which signals are to be used when operating the
XRT4500 in the “differential” or “single-ended”
modes.
1. Table entries are inputs to MUX2.
2. Column headings are outputs.
3. Signal names ending with A or B are analog inputs or
outputs. Signal names ending with D are digital inputs
or outputs.
• How does one configure the “DCE Mode” and “DTE
Mode” XRT4500 to operate in these scenarios.
NOTES:
4. X = Don’t Care (not used)
1. The “line” signals are drawn with both a “solid” line
and a “dashed” line. Both lines are used to transmit
and receive “differential” mode signals. However,
the “solid” line identifies the signal that should be
used, when operating the Transmitter in the “Sin-
gle-Ended” mode.
5. Shaded blocks = Normal (No Loop-Back)
Operating Modes for the XRT4500
The XRT4500 Multi protocol Serial Interface device
can be configured to operate in a wide variety of
modes or “scenarios”. This document illustrates some
of these “scenarios” and provides the reader with the
following information associated with each of these
scenarios.
2. Each scenario includes a table that indicates how
to configure the XRT4500 into each of these
modes, by specifying the appropriate logic states
for EC, 2CK/3CK, LP, CKINV, DTINV, and EN_OSC.
• Which pins (on the “DCE Mode” XRT4500 and
“DTE Mode” XRT4500) are used to propagate vari-
ous data or clock signals.
3. In all, 48 scenarios have been defined for the
XRT4500 device. Currently, this document only lists
a subset of these scenarios. Further versions of the
XRT4500 data sheet will include this information for
all 48 scenarios.
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
FIGURE 41. SCENARIO A, MUX2, (DCE/DTE = 0, LP = 0)
SCENARIO A
MUX2 (DCE/DTE = 0, LP = 0)
3
GND
RX1,2,3
8
TX4D
20
37
Digital MUX 2
RX4,5,6,7
VDD
RX4A
11
TX4A
TX4
TX5
Filter
RX4
RX5
10
TX4B
38
40
RX4B
RX4D
15
TX5D
36
12
RX5A
TX5A
Filter
13
9
35
33
TX5B
VDD
RX5B
RX5D
TX4,5,6,7,8
29
TR6A
RX6
Filter
Filter
TX6
TX7
30
28
TR6B
TX76D
32
RX67D
27
17
TR7
RX7
48
25
TX8D
EN_OUT
RX8I
19
14
Filter
RX8
TX8O
GND
TX8
TX4,5,6,7,8
23
75
RX8D
V.11 (RX1,2,3) Termination 80
Glitch Filter
EN_TERM
EN_FLTR
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MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
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FIGURE 42. SCENARIO B, MUX2, (DCE/DTE = 0, LP = 1), LOOP BACK NOT ENABLED
SCENARIO B
MUX2 (DCE/DTE = 0, LP = 1)
Loop Back not enabled
3
GND
RX1,2,3
8
TX4D
TX4A
20
37
Digital MUX 2
RX4,5,6,7
VDD
RX4A
11
TX4
TX5
Filter
Filter
RX4
RX5
10
TX4B
38
40
RX4B
RX4D
15
12
TX5D
TX5A
36
RX5A
13
9
35
33
TX5B
VDD
RX5B
RX5D
TX4,5,6,7,8
29
TR6A
RX6
RX7
Filter
Filter
TX6
TX7
30
28
TR6B
TX76D
32
RX67D
27
17
TR7
48
25
TX8D
EN_OUT
RX8I
19
14
Filter
RX8
TX8O
GND
TX8
TX4,5,6,7,8
23
75
RX8D
80
V.11 (RX1,2,3) Termination
Glitch Filter
EN_TERM
EN_FLTR
69
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
FIGURE 43. SCENARIO C, MUX2, (DCE/DTE = 1, LP = 0)
SCENARIO C
MUX2 (DCE/DTE = 1, LP = 0)
3
GND
RX1,2,3
8
TX4D
20
37
Digital MUX 2
RX4,5,6,7
VDD
RX4A
11
TX4A
TX4
Filter
RX4
RX5
10
TX4B
38
40
RX4B
RX4D
15
TX5D
36
12
RX5A
TX5A
Filter
TX5
13
35
33
TX5B
9
RX5B
RX5D
TX4,5,6,7,8
VDD
29
TR6A
RX6
Filter
Filter
TX6
TX7
30
TR6B
28
TX76D
32
RX67D
27
TR7
RX7
17
48
25
TX8D
EN_OUT
RX8I
19
Filter
RX8
TX8O
TX8
14
TX4,5,6,7,8
GND
23
75
RX8D
V.11 (RX1,2,3) Termination
80
Glitch Filter
EN_TERM
EN_FLTR
70
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
FIGURE 44. SCENARIO D, MUX2, (DCE/DTE = 1, LP = 1), LOOP BACK NOT ENABLED
SCENARIO D
MUX 2 (DCE/DTE = 1, LP = 1)
Loop Back not enabled
3
GND
RX1,2,3
8
TX4D
TX4A
20
37
Digital MUX 2
RX4,5,6,7
VDD
RX4A
11
TX4
TX5
Filter
RX4
RX5
10
TX4B
38
40
RX4B
RX4D
15
12
TX5D
TX5A
36
RX5A
Filter
13
9
35
33
TX5B
VDD
RX5B
RX5D
TX4,5,6,7,8
29
TR6A
RX6
Filter
Filter
TX6
TX7
30
28
TR6B
TX76D
32
RX67D
27
17
TR7
RX7
48
25
TX8D
EN_OUT
RX8I
19
14
Filter
RX8
TX8O
GND
TX8
TX4,5,6,7,8
23
75
RX8D
80
V.11 (RX1,2,3) Termination
Glitch Filter
EN_TERM
EN_FLTR
71
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
FIGURE 45. SERIAL INTERFACE SIGNALS AND CONNECTOR PIN-OUT
hfw.2gs1u(B)rXplmdbcavionte
g
y
csiPBCgurdlpanofehtXRT4.50
*
*
*
*
*
m
(P3,1972lugfcvdamrsinohteXRT504)
72
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
FIGURE 46. SERIAL INTERFACE CONNECTOR DRAWINGS
Serial Interface Connector Drawings
5
19
1
10
15
1
8
9
15
20
25
30
33
37
X.21 Connector (ISO 4903)
DTE Connector - DB-15 Pin Male
DCE Connector - DB-15 Pin Female
RS-449 Connector (ISO 4902)
DTE Connector Face - DB-37 Pin Male
DCE Connector Face - DB-37 Pin Female
FIGURE 46A
FIGURE 46B
NN JJ DD
Z
Y
V
U
R
L
F
E
B
A
LL
FF BB
X
T
S
N
J
D
1
7
13
25
MM HH CC
KK EE AA
P
K
14
20
RS-232 & EIA-530- Connector (ISO 2110)
DTE Connector - DB-25 Pin Male
W
M
H
C
DCE Connector - DB-25 Pin Female
FIGURE 46C
V.35/ISO 2593 Connector
DTE Connector Face - 34 Pin Male
DCE Connector Face - 34 Pin Female
IGURE
D
46
F
73
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
FIGURE 47. EIA-530 CONNECTION DIAGRAM FOR XRT4500
74
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
FIGURE 48. RS-232 CONNECTION DIAGRAM FOR XRT4500
75
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
SCENARIOS 1 & 2 NORMAL: ‘3-CLOCK’ DCE/DTE INTERFACE OPERATION
HDLC (L)
DTE (#1)
DCE (#2)
HDLC (R)
78
79
63
62
TXD
60
67
1
TXD
RX1
RXD
TX1
64
65
SCTE
77
76
74
SCTE
TXC
RX2
TX2
RXC
70
70
71
TXC
68
67
73
74
RX3
TX3
TX2
TXC
SCTE
TXD
71
64
65
77
76
RXC
RXD
RX2
RX1
RXC
RXD
63
62
78
79
1
60
TX1
XRT4500
XRT4500
INPUT PIN SETTINGS
DTE (#1)
STATE
DCE (#2)
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
STATE
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
0
1
1
1
1
DTE
No Echo
3 clock
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
0
1
1
1
1
DCE
No Echo
2CK/3CK
LP
2CK/3CK
LP
3 clock
No Loopback
No Invert
No Invert
No Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Internal OSC
No Internal OSC
NOTE:
1. When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
2. (See Table 8. MUX Connection Table)
76
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
SCENARIO 3 &2 DTE LOOP-BACK MODE
HDLC (L)
DTE (#3)
MUX 1
DCE (#2)
HDLC (R)
TXD
78
79
63
62
60
67
1
TXD
RX1
RXD
TX1
TX2
77
64
65
SCTE
74
SCTE
TXC
RX2
RXC
76
70
71
TXC
RXC
RXD
70
71
68
67
60
73
74
RX3
TX3
TX2
TXC
SCTE
TXD
64
65
77
76
RX2
RXC
RXD
63
62
78
79
1
RX1
TX1
XRT4500
XRT4500
INPUT PIN SETTINGS
DTE (#3)
STATE
DCE (#2)
STATE
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
0
0
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
0
1
1
1
1
DCE
No Echo
2CK/3CK
LP
3 clock
2CK/3CK
LP
3 clock
Loopback
No Invert
No Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
77
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
SCENARIO 4
HDLC (L)
DTE (#1)
DCE (#4)
HDLC (R)
MUX 1
78
79
63 TXD
60
67
1
TXD
RX1
RXD
TX1
62
77
76
64 SCTE
74
SCTE
TXC
RX2
TX2
RXC
65
70
71
70 TXC
68
67
73
74
RX3
RX2
RX1
TX3
TXC
SCTE
TXD
71
64
65
72
RXC
RXC
RXD
TX2
TX1
76
78
63
62
RXD
1
60
79
XRT4500
XRT4500
COMMENTS: DCE LOOP-BACK MODE
INPUT PIN SETTINGS
DTE (#1)
STATE
DCE (#4)
STATE
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
0
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
0
0
1
1
1
DCE
No Echo
2CK/3CK
LP
3 Clock
2CK/3CK
LP
3 clock
No Loopback
No Invert
Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
78
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
SCENARIO 5 & 2
HDLC (L)
DTE (#5)
DCE (#2)
HDLC (R)
78
79
63
62
TXD
60
67
1
TXD
RX1
RXD
TX1
77
76
64
65
SCTE
74
SCTE
TXC
RX2
TX2
RXC
TXC
70
71
70
71
73
74
68
67
60
RX3
TX3
TX2
TXC
SCTE
TXD
64
72
76
RXC
RXD
RX2
RX1
RXC
RXD
65
63
62
78
79
1
TX1
XRT4500
XRT4500
COMMENTS: TXC CLOCK INVERSION IN DTE MODE
INPUT PIN SETTINGS
DTE (#5)
STATE
DCE (#2)
STATE
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
0
1
0
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
0
1
1
1
1
DCE
No Echo
2CK/3CK
LP
3 clock
2CK/3CK
LP
3 clock
No Loopback
Invert
No Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
79
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
SCENARIO 6
HDLC (L)
DTE (#1)
DCE (#6)
HDLC (R)
TXD
78
79
63
62
60
67
1
TXD
RX1
RX2
RXD
TX1
64
65
SCTE
77
76
74
SCTE
TXC
TX2
RXC
70
71
TXC
RXC
RXD
70
68
67
60
73
74
RX3
RX2
TX3
TXC
SCTE
TXD
71
64
65
72
76
RXC
RXD
TX2
TX1
63
62
78
79
1
RX1
XRT4500
XRT4500
COMMENTS: TXC CLOCK INVERSION IN DCE MODE
INPUT PIN SETTINGS
DTE (#1)
STATE
DCE (#6)
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
STATE
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
0
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
0
1
0
1
1
DCE
No Echo
2CK/3CK
LP
3 clock
2CK/3CK
LP
3 clock
No Loopback
No Invert
No Loopback
Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
80
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
SCENARIO 7 & 2
HDLC (L)
DTE (#7)
DCE (#2)
HDLC (R)
MUX 1
63
62
TXD
SCTE
TXC
78
79
60
67
1
TXD
RX1
RXD
TX1
64
65
77
76
74
TX2
SCTE
TXC
RX2
RXC
70
71
70
68
67
60
73
RX3
TX3
TXC
SCTE
TXD
71
64
65
72
76
RXC
RXD
74
1
RX2
RX1
RXC
RXD
TX2
78
79
63
62
TX1
XRT4500
XRT4500
INPUT PIN SETTINGS
DTE (#7)
STATE
DCE (#2)
STATE
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
0
0
0
1
1
DTE
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
0
1
1
1
1
DCE
No Echo
No Echo
3 clock
2CK/3CK
LP
2CK/3CK
LP
3 clock
Loopback
Invert
No Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
81
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
SCENARIO 8
HDLC (L)
DCE (#1)
DCE (#8)
MUX 1
HDLC (R)
78
79
TXD
63
62
60
76
1
TXD
RX1
RX2
RXD
TX1
77
76
64 SCTE
74
SCTE
TXC
TX2
RXC
65
70
71
70 TXC
73
68
RX3
RX2
TX3
TXC
SCTE
TXD
71
64
65
72
RXC
67
60
74
1
RXC
RXD
TX2
TX1
76
78
63
62
RXD
RX1
79
XRT4500
XRT4500
INPUT PIN SETTINGS
DTE (#1)
STATE
DCE (#8)
STATE
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
0
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
0
0
0
1
1
DCE
No Echo
2CK/3CK
LP
3 clock
2CK/3CK
LP
3 clock
No Loopback
No Invert
Loopback
Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
82
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
SCENARIO 9 & 10
HDLC (L)
DTE (#9)
DCE (#10)
HDLC (R)
TXD
78
79
63
62
60
67
1
TXD
RX1
RXD
TX1
64
65
77
76
74
SCTE
TXC
RX2
TX2
RXC
70
71
TXC
RXC
RXD
70
71
68
67
60
73
RX3
RX2
TX3
TXC
SCTE
TXD
64
72
76
74
1
RXC
RXD
TX2
TX1
65
63
62
78
79
RX1
XRT4500
XRT4500
COMMENTS: 2 CLOCK MODE OPERATION WITHIN THE ‘DCE MODE’. THIS FEATURE IS USEFUL FOR APPLICATIONS
THAT INTERFACE TO A DEVICE WHICH DOES NOT SUPPLY ‘SCTE’ CLOCK SIGNAL
INPUT PIN SETTINGS
DTE (#9)
STATE
DCE (#10)
STATE
PIN
#
PIN
#
NAME
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
X
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
1
1
1
1
1
DCE
No Echo
2CK/3CK
LP
Don’t Care
No Loopback
No Invert
2CK/3CK
LP
2 clock
No Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
83
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
SCENARIO 12
DTE (#9)
HDLC (L)
HDLC (R)
DCE (#12)
MUX 1
78
79
TXD
63
62
60
67
1
TXD
RX1
RX2
RXD
TX1
77
76
64
65
75
SCTE
TXC
TX2
RXC
70
71
TXC
70
71
68
67
60
73
RX3
RX2
RX1
TX3
TXC
SCTE
TXD
64
65
72
76
RXC
RXD
74
1
RXC
RXD
TX2
TX1
78
79
63
62
XRT4500
XRT4500
INPUT PIN SETTINGS
DTE (#9)
STATE
DCE (#12)
STATE
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
0
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
1
0
1
1
1
DCE
No Echo
2CK/3CK
LP
3 clock
2CK/3CK
LP
2 clock
No Loopback
No Invert
Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
84
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
SCENARIO 13 & 10
HDLC (L)
DTE (#13)
HDLC (R)
DCE (#10)
TXD
78
79
63
62
60
67
1
TXD
RX1
RXD
TX1
64
65
77
76
74
SCTE
RX2
TX2
RXC
70
71
TXC
70
73
68
67
60
RX3
RX2
TXC
TX3
TX2
TXC
SCTE
TXD
71
64
65
72
76
RXC
RXD
74
1
RXC
RXD
63
62
78
79
RX1
TX1
XRT4500
XRT4500
INPUT PIN SETTINGS
DTE (#13)
STATE
DCE (#10)
STATE
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
1
1
0
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
1
1
1
1
1
DCE
No Echo
2CK/3CK
LP
2 clock
2CK/3CK
LP
2 clock
No Loopback
Invert
No Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
85
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
SCENARIO 14
HDLC (L)
DTE (#13)
DCE (#14)
HDLC (R)
78
79
63
62
TXD
60
67
1
TXD
RX1
RX2
RXD
TX1
64
65
77
76
74
SCTE
TXC
TX2
RXC
70
71
TXC
70
68
73
RX3
RX2
TX3
TXC
SCTE
TXD
71
64
65
72
76
RXC
RXD
67
60
74
1
RXC
RXD
TX2
63
62
78
79
RX1
TX1
XRT4500
XRT4500
COMMENTS: TXC CLOCK INVERSION AND 2 CLOCK MODE OPERATION WITHIN THE DCE MODE. THIS SCENARIO CAN
BE USED TO RESOLVE THE 2 CLOCK PROPAGATION DELAY TIMING VIOLATION ISSUE.
INPUT PIN SETTINGS
DTE
DCE
PIN
#
PIN
#
NAME
STATE
DESCRIPTION
NAME
STATE
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
1
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
1
1
0
1
1
DCE
No Echo
2CK/3CK
LP
2 clock
2CK/3CK
LP
2 clock
No Loopback
No Invert
No Loopback
Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
86
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
SCENARIO 16
HDLC (L)
DTE (#9)
DCE (#16)
HDLC (R)
MUX 1
78
79
TXD
63
62
60
67
1
TXD
RX1
RXD
TX1
77
76
64
65
74
SCTE
TXC
RX2
TX2
RXC
70
71
70 TXC
73
68
67
60
RX3
RX2
TX3
TXC
SCTE
TXD
71
64
65
72
RXC
74
1
RXC
RXD
TX2
TX1
76
78
63
62
RXD
RX1
79
XRT4500
XRT4500
INPUT PIN SETTINGS
DTE (#9)
STATE
DCE (#16)
STATE
PIN
NAME
#
PIN
#
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
1
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
1
0
0
1
1
DCE
No Echo
2CK/3CK
LP
2 clock
2CK/3CK
LP
2 clock
No Loopback
No Invert
Loopback
Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
87
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
SCENARIO 17 & 18
HDLC (L)
DTE (#17)
DCE (#18)
HDLC (R)
TXD
78
79
64
62
60
67
1
TXD
RX1
RXD
TX1
64
65
77
76
74
SCTE
TXC
RX2
TX2
RXC
70
71
70
71
68
67
60
73
RX3
RX2
TX3
TX2
TXC
SCTE
TXD
RXC
RXD
64
72
76
74
1
RXC
RXD
65
63
62
78
79
RX1
TX1
XRT4500
XRT4500
COMMENTS: X:21 MODE OPERATION
INPUT PIN SETTINGS (1 CLOCK MODE)
DTE (#17)
DCE (#18)
STATE
PIN
#
PIN
#
NAME
STATE
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
X
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
X
1
1
1
1
DCE
No Echo
2CK/3CK
LP
Don’t care
No Loopback
No Invert
2CK/3CK
LP
Don’t care
No Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
88
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
SCENARIO 20
HDLC (L)
DTE (#17)
DCE (#20)
MUX 1
HDLC (R)
TXD
78
79
63
62
60
67
1
TXD
RX1
RX2
RXD
TX1
77
76
64
65
74
SCTE
TXC
TX2
RXC
70
71
70
71
68
67
60
73
RX3
RX2
TX3
TXC
SCTE
TXD
RXC
RXD
64
65
72
76
74
1
RXC
RXD
TX2
TX1
78
79
63
62
RX1
XRT4500
XRT4500
INPUT PIN SETTINGS (1 CLOCK MODE)
DTE (#17)
DCE (#20)
STATE
PIN
#
PIN
#
NAME
STATE
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
X
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
X
0
1
1
1
DCE
No Echo
2CK/3CK
LP
Don’t care
No Loopback
No Invert
2CK/3CK
LP
Don’t care
Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
89
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
SCENARIO 21
HDLC (L)
DTE (#21)
DCE (#18)
HDLC (R)
63
62
TXD
78
79
60
67
1
TXD
RX1
RXD
TX1
64
65
77
76
74
TX2
SCTE
TXC
RX2
RXC
70
71
70
68
67
73
RX3
TX3
TXC
SCTE
TXD
61
64
65
72
76
RXC
RXD
74
1
RX2
RX1
RXC
RXD
TX2
78
79
63
62
60
TX1
XRT4500
XRT4500
INPUT PIN SETTINGS (1 CLOCK MODE)
DTE (#21)
DCE (#18)
STATE
PIN
#
PIN
#
NAME
STATE
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
X
1
0
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
X
1
1
1
1
DCE
No Echo
2CK/3CK
LP
Don’t care
No Loopback
Invert
2CK/3CK
LP
Don’t care
No Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
90
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
SCENARIO 22
HDLC (L)
DTE (#17)
DCE (#22)
HDLC (R)
TXD
78
79
63
62
60
67
1
TXD
RX1
RXD
TX1
64
65
77
76
74
SCTE
TXC
RX2
TX2
RXC
70
71
70
68
67
60
73
RX3
RX2
TX3
TXC
SCTE
TXD
71
RXC
64
65
72
76
74
1
RXC
RXD
TX2
RXD
63
62
78
79
RX1
TX1
XRT4500
XRT4500
INPUT PIN SETTINGS (1 CLOCK MODE)
DTE (#17)
DCE (#22)
STATE
PIN
#
PIN
#
NAME
STATE
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
X
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
X
1
0
1
1
DCE
No Echo
2CK/3CK
LP
Don’t care
No Loopback
No Invert
2CK/3CK
LP
Don’t care
No Loopback
Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
91
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
SCENARIO 23
HDLC (L)
HDLC (R)
DTE #23)
DCE (#18)
MUX 1
63
62
TXD
78
79
60
67
1
T X D
R X 1
R X D
T X 1
64
65
77
76
74
T X 2
S C T E
R X 2
R X C
70
71
70
61
68
67
73
R X 3
T X C
T X 3
T X C
S C T E
T X D
RXC
RXD
64
72
76
74
1
R X 2
R X 1
R X C
R X D
T X 2
65
78
79
63
62
60
T X 1
XRT4500
XRT4500
INPUT PIN SETTINGS (1 CLOCK MODE)
DTE (#23)
DCE (#18)
STATE
PIN
#
PIN
#
NAME
STATE
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
X
0
0
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
1
X
1
1
1
1
DCE
No Echo
2CK/3CK
LP
Don’t care
Loopback
Invert
2CK/3CK
LP
Don’t care
No Loopback
No Invert
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
92
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
SCENARIO 48
HDLC (L)
DTE (#17)
DCE #48)
HDLC (R)
63
62
TXD
78
79
60
67
1
TXD
RX1
RXD
TX1
TX2
64
65
77
76
74
SCTE
TXC
RX2
RXC
70
71
70
68
67
73
RX3
TX3
TXC
SCTE
TXD
61
64
65
72
76
RXC
RXD
74
1
RX2
RX1
RXC
RXD
TX2
78
79
63
62
60
CLK
Q
D
TX1
XRT4500
XRT4500
INPUT PIN SETTINGS (1 CLOCK MODE)
DTE (#17)
DCE (#48)
STATE
PIN
#
PIN
#
NAME
STATE
DESCRIPTION
NAME
DESCRIPTION
31
34
50
18
54
55
53
DCE/DTE
EC
0
1
X
1
1
1
1
DTE
No Echo
31
34
50
18
54
55
53
DCE/DTE
EC
1
0
X
0
0
1
1
DCE
Echo Mode
Don’t care
Loopback
Invert
2CK/3CK
LP
Don’t care
No Loopback
No Invert
2CK/3CK
LP
CKINV
DTINV
OSCEN
CKINV
DTINV
OSCEN
No Invert
No Invert
No Internal OSC
No Internal OSC
NOTE: When M0=1, M2=1, M2=0 the XRT4500 is in the 1 clock (X.21) mode and the 2CK/3CK input pin is ignored.
93
XRT4500
áç
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
External Components used by the XRT4500
Function
VSS by-pass Capacitor
Description
Notes
-6V switching Regulator filter.
25-47 F, 12V, SMT Tantalum
µ
Low ESR. (0.20 max at 100kHz)
Ω
Sprague Type
SPR595D476X9025R2T-X
Must be Schottky type
JW Miller PM105-470K or PM105-
680k.
Schottky Diode
Inductor
1N5819 40V, 1A.
47 or 68 H SMT inductor
µ
Coilcraft D03316P-473
Current Sense Resistor
Charge Pump Capacitor
VPP by-pass Capacitor
VDD by-pass Capacitor
0.5 , 0.5W, 5%
Ω
+12V Charge Pump
+12V Charge Pump
+5V decoupling. (In addition to
2.2 F, 25V, SMT Tantalum
µ
10 F, 25V, SMT Tantalum
µ
22 F, 16V, Electrolytic
µ
various 0.1 F, 50V capacitors)
µ
General by-pass
Capacitors
Panasonic X7R Dielectric, 1206
size.
0.1 F, 50V
µ
Digikey PCC104BCT-ND
94
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
80 LEAD THIN QUAD FLAT PACK
(14 x 14 x 1.4 mm TQFP)
REV. 3.00
D
D1
60
41
61
40
D1
D
80
21
2
0
1
A2
B
e
C
A
α
Seating Plane
A1
L
Note: The control dimension is the millimeter column
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
1.40
0.05
MAX
1.60
0.15
A
0.055
0.002
0.063
0.006
A1
A2
0.053
0.009
0.004
0.622
0.547
0.057
0.015
0.008
0.638
0.555
1.35
0.22
1.45
0.38
B
C
0.09
0.20
D
15.80
13.90
16.20
14.10
D1
e
L
α
0.0256 BSC
0.65 BSC
0.018
0.030
0.45
0.75
0°
7°
0°
7°
95
áç
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV.1.0.7
REVISIONS
Rev. 1.0.3 -- Updated electrical characteristics, made minor text edits.
Rev. 1.0.4 -- Corrected page formatting problems.
Rev. 1.0.5 -- Corrected table anchor format problem page 46 (caused text to hide), replaced TR3 with TR6
page 41.
Rev. 1.0.6 -- Figure 2: Supply current vs. Temp, edited IDD values.
Rev. 1.0.7 -- Table 1, Receiver specs V.35-- Min Signal level = ±250mV, Max Signal Peak = ±10V, DC Rin =
175Ω. Table 6, Switch S4 V.28 changed from Open to Closed.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no represen-
tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-
tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-
ration is adequately protected under the circumstances.
Copyright 2002 EXAR Corporation
Datasheet September 2002.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
96
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