XRT56L85D [EXAR]
Low Power PCM Line Interface; 低功耗PCM线接口
| 型号： | XRT56L85D |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Low Power PCM Line Interface |
| 文件： | 总12页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRT56L85
Low Power
PCM Line Interface
October 2000-1
FEATURES
APPLICATIONS
D Low Power (Typical 14mA)
D Single +5V Supply
D T1 and CEPT Interfaces
D CPI
D DMI
D Up to 2.048 Mbps Operation in Both TX and RX
Directions
D Receiver Input can be:
Balanced Transformer Coupled
Capacitively (Twisted Pair)
Single Coaxial Capacitive Coupling
GENERAL DESCRIPTION
The XRT56L85 is a PCM line interface chip. It consists of
both transmit and receive circuitry in a DIL 18 pin
package. The maximum bit rate the chip can handle is
2.048 Mbps and the signal level to the received can be
attenuated by 10dB of cable loss at half the bit rate. Total
current consumption is between 12-16mA at +5V.
ORDERING INFORMATION
Operating
Temperature Range
Part No.
Package
18 Lead 300 Mil PDIP
18 Lead 300 Mil JEDEC SOIC
XRT56L85P
XRT56L85D
-40°C to +85°C
-40°C to +85°C
BLOCK DIAGRAM
PDC
1
Positive
Threshold
Comparator
TTL Buffer
+
RPOS
11
−
RXDATA+
RXDATA-
2
3
TTL Buffer
TTL Buffer
Negative
Threshold
Comparator
Peak
8
4
RCLK
TE
Detector
−
+
10 RNEG
TANK BIAS
Bias
Bias
6
RXV
CC
9
5
BIAS
7
RXGND
18
TXV
CC
TTL Buffer
TPOS 17
15 TXDATA+
TCLK 16
TNEG 12
TTL Buffer
13
TXDATA-
TXGND
14
Figure 1. Block Diagram
Rev. 2.11
E 2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
XRT56L85
PIN CONFIGURATION
1
18
17
16
15
14
13
12
11
10
PDC
RXDATA+
TXV
CC
TPOS
1
18
PDC
TXV
CC
2
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
10
RXDATA+
RXDATA-
TE
TPOS
TCLK
TXDATA+
TXGND
TXDATA-
TNEG
3
RXDATA-
TCLK
TXDATA+
TXGND
4
TE
BIAS
5
BIAS
6
TANK BIAS
TXDATA-
TNEG
RPOS
TANK BIAS
RXGND
RCLK
7
RXGND
RCLK
RXV
8
9
RPOS
RNEG
RNEG
RXV
CC
CC
18 Lead PDIP (0.300”)
18 Lead SOIC (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
Symbol
PDC
Type Description
1
2
Peak Detector Capacitor. This pin should be connected to a 0.1µF capacitor
RXDATA+
I
Receive Analog Input Positive. The AMI signal received from the line is applied at this and
the RX DATA(-) pin. Data and clock from the signal applied at these two pins recovered and
output on the RPOS, RNEG, and RCLK pins, respectively.
3
4
5
6
7
RXDATA-
TE
I
Receive Analog Input Negative. See the description for RX DATA(+).
LC Tank Excitation Output. This output connects to one side of the tank circuitry.
Bias. This pin should be tied to ground through a 0.1µF capacitor.
Tank Reference. The tank circuitry is biased via this output.
O
O
BIAS
TANK BIAS
RXGND
Receiver Ground. To minimize ground interference a separate pin is used to ground the re-
ceiver section.
8
RCLK
O
Recovered Receive Clock. Recovered clock signal from the AMI signal received at the RX
DATA(+) and RX DATA(-) pins. This signal is output to the terminal equipment.
9
RXVCC
RNEG
Receive Supply Voltage. 5V supply voltage for the Receive Section.
10
O
O
Receive Negative Data Output. A signal at this pin corresponds to the receipt of a negative
pulse on the RX DATA(+)/RX DATA(-) pins. This TTL compatible signal is output to the
terminal equipment.
11
RPOS
Receive Positive Data Output. A signal at this pin corresponds to the receipt of a positive
pulse on the RX DATA(+)/RX DATA pins. This TTL compatible signal is outputed to the
terminal equipment.
12
13
TNEG
I
Transmit Negative Data Input. TTL input for a negative polarity pulse (the negative portion
of the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA pins.
TXDATA-
O
Transmit Negative Data Output. This pin, along with the TX DATA(+) pin, forms a differential
driver output, this is used to drive AMI data down the line via a transformer. Note: This is an
open-collector output.
14
15
16
17
TXGND
TXDATA+
TCLK
Transmit Ground.
O
I
Transmit Positive Data Output. Please see description for TX DATA(-).
Transmit Clock. TPOS and TNEG are sampled on the rising edge of TCLK.
TPOS
I
Transmit Positive Data Input. TTL input for a positive polarity pulse (the positive portion of
the AMI pulse train) to be transmitted to the line via the TX DATA(+) and TX DATA(-) pins.
18
TXVcc
Transmit Supply Voltage. 5V supply voltage to the transmit section.
Rev. 2.11
2
XRT56L85
ELECTRICAL CHARACTERISTICS
Test Conditions: V = 5V± 5%, T = -40°C to +85°C, Unless Otherwise Specified
CC
A
Parameters
Min.
Typ.
Max.
Unit
Conditions
DC Electrical Characteristics
Supply Voltage
4.75
5
5.25
16
V
Supply Current
14
mA
Total Current to Pin 9 & Pin 18 (Transmit-
ter Outputs Open and All Ones Pattern)
Receiver Section
Tank Drive Current
Clock Output Low
Clock Output High
Data Output Low
300
3.0
3.0
0.6
500
0.3
3.6
0.3
3.6
700
0.6
µA
V
Measured at Pin 4, VCC= 5V
Measured at Pin 8, IOL = 1.6mA
Measured at Pin 8, IOH =400µA
Measured at Pin 10 & 11, IOL =1.6mA
Measured at Pin 10 & 11, IOH =400µA
V
0.6
V
Data Output High
Transmitter Section
Driver Output Low
Output Leakage Current
V
0.9
1.2
V
Measured at Pin 13 & 15, IOL =-40mA
100
µA
Measured in Off State
Output Pull-up to +20V
Input High Voltage
Input Low Voltage
Input Low Current
Input High Current
Output Low Current
2.2
V
Measured at Pin 12, 16 & 17
IOL = -40mA, VOL = 1.0V
0.8
-1.6
40
V
Measured at Pin 12, 16 & 17
Output Off
mA
µA
mA
Measured at Pin 12, 16 & 17
Input Low Voltage = 0.4V
Measured at Pin 12, 16 & 17
Input Low Voltage = 0.4V
-30
Measured at Pin 13 & 15
VOL= 1.0V
AC Electrical Characteristices
Receiver Section
Input Level
6
6.6
Vpp
Vpp
Measured Between Pin 2 & 3
Loss Input Signal Alarm Level
0.6
Measured Between Pin 2 & 3
Alarm on Pull Data/Clock Output High
Input Impedance at 2.048MHz
2.5
kΩ
Measured Between Pin 2 & 3
With Sinewave Input
Clock Duty Cycle
35
35
50
20
50
65
40
75
%
Measured at Pin 8 at 2.0V DC Level
Measured at Pin 8, CL = 15pF
Clock Rise & Fall Time
Data Pulse Width
ns
% of
clock
period
Measured at Pin 10 & 11
At 1V DC Level, Cable Loss = €dB
Transmitter Section
Pulse Width at 2.048MHz
Output Rise Time
234
244
12
264
25
ns
ns
ns
ns
Measured at Pin 13 & 15 Figure 3
Figure 3
Output Fall Time
12
25
Figure 3
Output Fall Imbalance
2.5
At 50% Output Level
Rev. 2.11
3
XRT56L85
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20V
Storage Temperature . . . . . . . . . . . . . -65°C to 150°C .
SYSTEM DESCRIPTION
The Receiver
appropriate frequency is added externally to provide the
appropriate frequency-selective filtering of the received
clock signal.
The incoming bipolar PCM signal, which is attenuated
and distorted by the cable is applied to the receiver input,
consisting of the RX DATA(+) and RX DATA(-) pins, either
through a balanced transformer, a balanced capacitively
coupled terminal or a single-ended coaxial cable (see
Figure 5). A peak detector following the input generates a
DC reference for the positive and negative threshold
comparator (to extract the positive and negative data
pulses). Information on the positive and negative data
pulses is outputed as TTL compatible signals at pins
RPOS and RNEG, respectively. More specifically, an
output signal present at the RPOS pin indicates that a
positive pulse was received at the RX DATA(+)/RX
DATA(-) pins, from the incoming bipolar data stream.
Likewise an output signal present at the RNEG pin
indicates that a negative pulse was received at the RX
DATA(+)/RX DATA(-) pins. This conversion from the
bipolar signal to TTL compatible signals allows for digital
processing of the clock and data signals by the terminal
equipment. An example of the waveforms of the TTL
compatible recovered clock and data as output by the
receiver portion of the chip is presented in Figure 2,
Figure 3 and Figure 5. A tank circuit tuned to the
The Transmitter
The transmitter portion of the chip receives TTL
compatible signals and transmits a corresponding bipolar
data stream down the line (See Figure 5). TPOS and
TNEG are TTL compatible signals that dictate the polarity
of the pulse to be generated and transmitted on the output
bipolar data stream. Both TPOS and TNEG inputs are
sampled by the rising edge of the transmit clock, TCLK.
The TX DATA(+) and TX DATA(-) pins form a differential
driver output, this is used to drive AMI data down the line
via a transformer. The TX DATA(+) and TX DATA(-) pins
are open-collector outputs.
When a logic “high” signal is applied to the TPOS pin, a
positive pulse (the positive portion of the bipolar data
stream) will be transmitted to the line via the TX DATA(+)
O/P and TX DATA(-) O/P pins. Likewise, when a logic
“high” signal is applied to the TNEG pin, a negative pulse
will be transmitted to the line via the TX DATA(+) and TX
DATA(-) pins. An illustration of the key waveforms
involved in this TTL to AMI conversion process, in the
Transmitter portion of the chip is presented in Figure 4.
Rev. 2.11
4
XRT56L85
V
=5V
CC
100
0.1µF
Output
Pin 13 & 15
CL=15pF
Pin 9 &18
2.048Mbps
Pulse
Input
Generator
XRT56L85
0V
Pin 12, 16, 17
Pin 7 &14
0V
Figure 2.
244ns
<5ns
90%
1.5V
10%
<5ns
3V
90%
1.5V
10%
15ns Typ.
Input Pulse
from Generator
0V
15ns Typ.
+5V
Output from Pin 13
or Pin 15
Vol
Pulse Width
Fall Time
Rise Time
Figure 3.
Rev. 2.11
5
XRT56L85
RXDATA+
RCLK Output At Pin 8
RPOS Output At Pin 11
RNEG Output At Pin 10
TCLK Clock To Pin 16
TPOS To Pin 17
TNEG To Pin 12
Bipolar Signal At
Transformer Output
Figure 4. Receiver Timing Diagram With 1-1-1-1-1-1 Pattern
Rev. 2.11
6
XRT56L85
V
CC
RCACON
2
3
5
0.1µF
0.1µF
75
18
V
CC
2
3
2
3
5
RXDATA+
RXDATA-
BIAS
0.1µF
T2
15
13
TIP
TXDATA+
TXDATA-
56
5
RING
T1
56
2
PE65415
1:1:1
TIP
4
120
T.E.
RING
L
C
3
5
XRT56L85
1:1
0.1µF
14
TGND
6
TANK BIAS
4.7µF
16
17
12
11
10
8
TCLK
TPOS
TNEG
RPOS
TCLK
TPOS
TNEG
RPOS
RNEG
RCLK
TIP
2
V
CC
0.1µF
0.1µF
9
1
120
RV
CC
PDC
RNEG
RCLK
0.1µF
0.1µF
RING
3
5
0.1µF
7
RGND
0.1µF
U1
56L85TA
L=Tank Coil AIE 415−0804 (1.544 and 2.048 Mbs)
Device
1.544Mbs
2.048Mbs
L
60µH
60µH
C
175pF
100pF
Figure 5. Application Circuit for XRT56L85
Rev. 2.11
7
XRT56L85
18 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
18
1
10
9
E
1
E
D
A
2
A
Seating
Plane
L
C
α
A
1
B
e
A
e
B
e
B
1
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.145
0.015
0.115
0.014
0.030
0.008
0.845
0.300
0.240
0.210
0.070
0.195
0.024
0.070
0.014
0.925
0.325
0.280
3.68
0.38
2.92
0.36
0.76
0.20
21.46
7.62
6.10
5.33
1.78
4.95
0.56
1.78
0.38
23.50
8.26
7.11
A
1
A2
B
B
1
C
D
E
E
e
1
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
e
e
L
A
0.310
B
0.430
0.160
7.87
10.92
4.06
0.115
2.92
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 2.11
8
XRT56L85
18 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
Rev. 1.00
D
18
1
10
E
H
9
C
A
Seating
Plane
α
e
B
A
1
L
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.093
0.004
0.013
0.009
0.447
0.291
0.104
0.012
0.020
0.013
0.463
0.299
2.35
0.10
0.33
0.23
11.35
7.40
2.65
0.30
0.51
0.32
11.75
7.60
A
B
1
C
D
E
e
0.050 BSC
1.27 BSC
H
L
0.394
0.419
0.050
10.00
0.40
10.65
1.27
0.016
α
0°
8°
0°
8°
Note: The control dimension is the millimeter column
Rev. 2.11
9
XRT56L85
Notes
Rev. 2.11
10
XRT56L85
Notes
Rev. 2.11
11
XRT56L85
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 2000 EXAR Corporation
Datasheet October 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.11
12
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