XRT56L22 [EXAR]
Low Power Repeater/Receiver; 低功率中继器/接收器
| 型号： | XRT56L22 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Low Power Repeater/Receiver |
| 文件： | 总16页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XR-T56L22
Low Power
Repeater/Receiver
...the analog plus companyTM
June 1997-3
FEATURES
APPLICATIONS
D Contains All The Active Components For A PCM
D T1 PCM Repeater/Receiver
Repeater Or Long Haul Line Receiver
D T148C PCM Repeater/Receiver
D Low Voltage Operation (5.1V)
D Low Power Consumption (8.75mA Max)
D 2Mbps Operation Capability
D European 2.048Mbps PCM Repeater/Receiver
D Digital Multiplexers, CSUs, Switching Equipment
D ISDN Compatible Equipment: Fax Machines,
D Dual Matched ALBO Ports
Computers etc.
D Internal Adjustable Phase Shift Circuitry
D Extracted Clock Output
D Internal Shunt Regulator
D Temperature Independent Current Biasing
GENERAL DESCRIPTION
The XR-T56L22 is a very low power monolithic repeater/
receiver IC designed for PCM carrier systems operating
between 1.544Mbps and 2.37Mbps. The IC provides all
the active circuitry required to implement one side of a
PCM repeater. The XR-T56L22 features on-chip
adjustable phase shifting, an extracted clock output and
an on-board shunt regulator. The very low power
consumption of the device makes it ideal for long haul
“tandem” repeater applications.
ORDERING INFORMATION
Operating
Temperature Range
Part No.
Package
18 Lead 300 Mil PDIP
XR-T56L22AP
XR-T56L22AN
XR-T56L22AD
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
18 Lead 300 Mil CDIP
18 Lead 300 Mil Jedec SOIC
Rev. 1.02
E1997
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
XR-T56L22
BLOCK DIAGRAM
2
ALBO1
3
ALBO
PEAK
DET.
18
ALBO2
ALBO FIL
1
ANA GND
5
6
7
AMP + I/P
+
AMP -O/P
AMP +O/P
AMP
4
-
AMP - I/P
Clock
Clock
Bias
GEN.
Comparators
16
LC I/P
11
Clock
Driver
Clock
AMP
Clock O/P
17
LC Bias
15
Phase Cont.
Data
Comparators
Voltage
Ref.
Gen.
13
V
REF
9
Volt.
Reg.
Q
D
Data +
14
REG Cont.
CLK
Output
Drivers
+5
12
Data
VCC
Latches
10
Data -
Q
D
8
CLK
DIG GND
Figure 1. XT-T56L22 Block Diagram
Rev. 1.02
2
XR-T56L22
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
ANA GND
ALBO1
ALBO FIL
LC BIAS
1
18
ANA GND
ALBO FIL
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
10
ALBO1
ALBO2
LC BIAS
LC I/P
PHASE CONT.
REG CONT.
VREF
VCC
CLOCK O/P
DATA-
ALBO2
AMP-I/P
AMP +I/P
LC I/P
PHASE CONT.
REG CONT.
AMP-I/P
AMP +I/P
AMP -O/P
AMP +O/P
DIG GND
DATA+
AMP -O/P
AMP +O/P
DIG GND
DATA+
V
REF
V
CC
CLOCK O/P
DATA-
18 Lead PDIP, CDIP (0.300”)
18 Lead SOIC (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
Symbol
ANA GND
ALBO 1
Description
1
2
Ground for Analog Sections of IC and Substrate.
ALBO PORT 1 Output. Port impedance varies between 25W and 20kW proportional to input signal
level.
3
4
ALBO 2
AMP - I/P
AMP + I/P
ALBO PORT 2 Output. Similar to pin 2.
Inverting Input of Signal Preamp RIN > 20kW.
Non-Inverting Input of Signal Preamp. RIN > 20kW.
5
6
AMP - O/P Inverting Output of Signal Pre-amp. Rout < 200W. DC level typically 3.2V.
AMP + O/P Non-inverting Output of Signal Pre-amp. Similar to pin 6.
7
8
DIG GND
DATA+
Ground for Digital Portion of IC.
9
Positive Data Driver Output (Open Collector). VOL < 0.95V @ lOUT = 32mA.
Negative Data Driver Output (Open Collector). VOL < 0.95V @ lOUT = 32mA.
10
11
DATA-
CLOCK O/P Phase Shifted Clock Output (Open Collector). Decouple to GND with 0.1mF if not required. With
Rpull-up = 1K, VOL < 1.1V @ IOUT = 4mA.
12
13
14
VCC
Input Pin of Shunt Regulator and Supply Pin for IC. For voltage feed applications the regulator
must be disabled and a 5V + 5% supply connected. For line feed a current of 48-120mA is required.
ICC < 8.75mA @ RON, ALBO = 25W typical.
VREF
Output Voltage of Internal Reference of Shunt Regulator. For parallel operation of regulators
should be tied to pin 13 of 2nd T56L22 device. VREF approxi-mately VCC/2. Decouple to GND with
0.1mF.
REG CONT Input Voltage of Shunt Regulator Amp. To inhibit regulator, pin should be tied to ground. For line
feed operation decouple to GND with 0.1mF. For parallel operation of regulators tie pin 14 of 2nd
T56L22 device. VREG approximately VREF
.
15
16
PHASE
CONT
Phase Shift Adjust Input. A resistor to GND from the pin allows adjustment of phase shift from 905
to approximately 05. RP typical 1.8K to 1K. Vphase typical 340mV.
LC I/P
Clock Amplifier Input. Pulsed with current from clock comparator. Connect LC tank between 16, 17
for clock recovery. Ickon = —110mA typical.
17
18
LC BIAS
Clock Amplifier Reference Voltage. VLC = 3.6V typical.
ALBO FIL
Control Pin for ALBO Ports. Voltage developed across a capacitor on this pin defines ALBO on
impedance VALBO = 1.5V typical.
Rev. 1.02
3
XR-T56L22
ELECTRICAL CHARACTERISTICS
Test Conditions: TA = -40°C to +85°C, VCC = 5.1V ± 5% unless otherwise specified - refer to test circuit (Figure 6).
Parameter
Pin
Min.
Typ.
Max.
Unit
Conditions
General
1
Supply Voltage
12
12
4.85
5.35
8.75
100
0.1
V
mA
mA
V
Pin 12, 13 to VCC
Supply Current
7
Data Output Leakage Current
ALBO Port Off Voltage
Amplifier Pin Voltage
Amplifier Pin Voltage
Amplifier
9, 10
2, 3
4, 5
6, 7
Vpull-up = 8V
VCC = 5.35 V1
2.7
3.2
3.7
V
Input Impedance
Input Offset Voltage
Input Bias Current
Input Offset Current
Output Offset Voltage
Common Mode Rejection Ratio
Output Volage Swing
Clock Amplifier
4, 5
4, 5
40
KW
mV
mA
mV
W
-10
10
5
RS = 8.2K2
RS = 8.2K2
RS = 8.2K2
RS = 8.2K2
4, 5
4, 5
-1
-50
40
1
6, 7
50
4, 5, 6, 7
6, 7
dB
V
1.9
Input Offset Voltage
Input Bias Current
AC Gain
17, 16
17, 16
0.5
6
5
mV
mA
RS = 10K3
4
40
10
dB
-3db bandwidth
MHz
ns
Delay
35
ALBO
ALBO Filter Resistance
ALBO Impedance Match
On Current
18-1
2, 3
1
31
57
10
KW
%
1.3
0.4
2.4
1.4
25
mA
mA
W
Drive Current
18
5
5
Maximum On Impedance
Minimum Off Inpedance
2, 3-1
2, 3-1
20
KW
Notes
1 Internal regulator disabled.
2 Source Resistance.
3 RS = Wou4d3 43wiw5qnd3 PIN 16 positive with respect to Pin 17
4 Pin 16 = Pin 17 = 3.6V
5 f
= 1MHz
test
Specifications are subject to change without notice
Rev. 1.02
4
XR-T56L22
ELECTRICAL CHARACTERISTICS (CON’T)
Parameter
Pin
Min.
Typ.
Max.
Unit
Conditions
Threshold Voltages
1, 2
1, 2
3
ALBO Threshold +Ve
7, 6
7, 6
1.4
1.4
-3
1.6
1.6
3
V
V
ALBO Threshold -Ve
ALBO Threshold Difference
Clock Drive on Current + Ve
Clock Drive on Current -Ve
Clock Drive Difference
%
mA
mA
%
%
%
%
%
%
%
4
80
80
-3
140
140
3
4
3
5
Clock Threshold +Ve
7, 6
7, 6
69
69
-3
79
79
3
5
Clock Threshold -Ve
3
Clock Threshold Difference
Data Threshold +Ve
3
7, 6
7, 6
41
41
-3
50
50
3
5
Data Threshold -Ve
3
Data Threshold Difference
Data Output Stages
Output Pulse Rise Time + Ve (Tr)
Output Pulse Rise -Time-Ve(Tr)
Output Pulse Fall Time+Ve(Tf)
Output Pulse Fall Time -Ve (Tf)
Output Pulse Width +Ve (Tw)
Output Pulse Width -Ve (Tw)
9
10
9
40
40
nS
nS
nS
nS
nS
nS
nS
10%-90%6
10%-90%6
10%-90%6
10%-90%6
at 50%
40
10
9
40
224
224
-12
264
264
12
10
at 50%
Output Pulse Width Difference
(dTw)
at 50%
6
6
Output Voltage (low) (VOL)
9, 10
9, 10
0.6
0.95
0.15
V
V
Output Voltage Difference (VOL)
-0.15
Notes
1 Pk/pk voltage at Pins 6 and 7 of a 1MHz sine wave derived through amplifier and measured differentially.
2 Pk/pk voltage at Pins 6 and 7 adjusted for a current increase of 2mA at pin 1.
3 Calculation only: percentage difference = [higher value/lower value]-1 x 100%.
4 V6 - V7 adjusted to ALBO threshold voltage (Pin 16 = 3.6V)
5 Figure taken as a percentage of ALBO threshold.
6 Using a 130W pull up resistor between 9, 10 and VCC and 15pF capacitance to GND.
Specifications are subject to change without notice
Rev. 1.02
5
XR-T56L22
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
Clock Output Stage
Output Pulse Rise Time (Tr)
Output Pulse Fall Time (Tf)
Output Pulse Width (Tw)
Shunt Regulator
Pin
Min.
Typ.
Max.
Unit
Conditions
1
11
11
11
40
40
ns
ns
ns
224
264
Output Voltage
12
12
12
4.85
5.1
5.35
V
Pin 13, 14 floating
Pin 13, 14 floating
Voltage Regulation Over Temp.
Load Regulation
-0.02
%/°C
0.027
%/mA 1mA to 100mA load
Note
1 Using a 2K pull up resistor between 11 and VCC and 15pF capacitance to GND.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . . -65°C to 150°C
Operating Temperature . . . . . . . . . . . . . -40°C to 85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V
Supply Voltage Surge (10ms) . . . . . . . . . . . . . . . . . 25V
Data Output Voltage (pin 9, 10) . . . . . . . . . . . . . . . 12V
SYSTEM DESCRIPTION
With reference to the functional block diagram, the basic
operation of the XR-T56L22 may be described as follows:
The received bipolar signal, is applied to a linear amplifier
and automatic equalizer. These circuits provide the
necessary amount of gain and phase equalization to
recover the transmitted data, and band limit the signal, to
optimize repeater performance for near-end crosstalk
produced by other systems operating within the same
cable bundle.
control the time at which the output signals from the
preamplifier are sampled by the pulse regenerator
circuits. The phase shifted clock signal is made available
asanoutputfromthecircuitforinterfaceapplications. The
clock phase adjustment is performed with a single pin
using an external resistor. Adjustment of the position of
the clock sampling edge by the phase shift circuit allows
performance of the pulse regenerator to be optimized.
The pulse regenerator performs the sampling and data
slicing to regenerate the appropriate output pulse. These
pulses are applied to an external output transformer to
create the bipolar signal that drives the next section of
twisted pair.
Thepreamplifieroutputsignalswhicharebalancedandof
opposite phase, are applied to the clock extraction and
pulse regenerator circuits. Here they are rectified and
then applied to a high Q resonant circuit which extracts
the 1.544/2.048 Mbps frequency component from the
received signal. This signal is then sliced and fed to an
adjustable phase shift circuit. A second slicer is used to
Rev. 1.02
6
XR-T56L22
Typical I Vs. V
CC
CC
7.8
Variation at T=25°C
(Clock, Data Outputs
+ ALBO all Operating)
7.6
7.4
(V =6V p-p (@2.04MBPS)
IN
7.2
7.0
6.8
6.6
6.4
4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4
5.5
V
CC
in Volts
Figure 2. Supply Current Variation
with V (Regulator Inhibited)
CC
120
Max Clock Drive
Current = 100mA
@ Albo Thresholds
110
100
90
80
70
60
50% CLK Drive Max
50
40
30
20
10
1.8 1.6 1.4 1.2 1.0 .8 .6 .4 .2
0
.2 .4 .6 .8 1.0 1.2 1.4 1.6 1.8
V
= 1.44 CLK
= 1.02v
V
OUT (V)
CLK
THLD(+)
ALBO
THLD(+)
ALBOTHLD
PREAMP
V
CLKTHLD
Figure 3. Clock Drive Current Against Preamp Output Voltage
Rev. 1.02
7
XR-T56L22
60
50
40
30
20
10
0
Differential Gain
Phase
0
–45
–90
–10
–135
–20
–30
–40
–180
Frequency In Hertz
4
5
6
7
8
10
10
10
10
10
Figure 5. Preamp Gain/Phase Characteristics
Preamp Output
(Approx. 1.5 pK to pK)
Oscillator Input
Pin 16
Clock Output
Pin 12
Data Pos.
Pin 18
Data Neg.
Pin 1
Figure 4. Typical T56L22 Waveforms
Rev. 1.02
8
XR-T56L22
C11
15µF
+
1
18
IM
C18
R1
3.9K
2
3
4
5
17
16
15
14
1µF
R13
51
C1
8.22UF
C9
8.1µF
R2
100
C2
8.22UF
C7
8.1µF
R11
1.8K
R3
51
R7
680
R4
8.2K
R5
C3
C8
8.22µF
6
7
8
9
13
12
11
10
V
CC
1µF
R6
7.5K
100
C4
+
C6
47µF
C5
8.22µF
1µF
V
R18
CC
1K
R9
R8
138
130
D+
D- CLK
Figure 6. AC Parameter Test Circuit
Rev. 1.02
9
Figure 8. XR–T56L22 E1 Evaluation Circuit
Figure 9. XR–T56L22 T1 Evaluation Circuit
XR-T56L22
18 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
18
1
10
9
E
1
E
D
A
2
A
Seating
Plane
L
C
α
A
1
B
e
e
e
B
A
B
1
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.145
0.015
0.115
0.014
0.030
0.008
0.845
0.300
0.240
0.210
0.070
0.195
0.024
0.070
0.014
0.925
0.325
0.280
3.68
0.38
2.92
0.36
0.76
0.20
21.46
7.62
6.10
5.33
1.78
4.95
0.56
1.78
0.38
23.50
8.26
7.11
A
1
A2
B
B
1
C
D
E
E
e
1
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
e
e
L
A
0.310
B
0.430
0.160
7.87
10.92
4.06
0.115
2.92
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 1.02
12
XR-T56L22
18 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
Rev. 1.00
18
1
10
9
E
E
1
D
A
1
Base
A
Plane
Seating
Plane
L
c
e
α
B
B
1
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.100
0.015
0.014
0.045
0.008
0.860
0.250
0.200
0.070
0.026
0.065
0.018
0.960
0.310
2.54
0.38
0.36
1.14
0.20
21.84
6.35
5.08
1.78
0.66
1.65
0.46
24.38
7.87
A
B
B
c
1
1
D
E
E
e
L
1
0.300 BSC
0.100 BSC
7.62 BSC
2.54 BSC
0.125
0.200
3.18
5.08
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 1.02
13
XR-T56L22
18 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
Rev. 1.00
D
18
1
10
E
H
9
C
A
Seating
Plane
α
e
B
A
1
L
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.093
0.004
0.013
0.009
0.447
0.291
0.104
0.012
0.020
0.013
0.463
0.299
2.35
0.10
0.33
0.23
11.35
7.40
2.65
0.30
0.51
0.32
11.75
7.60
A
B
1
C
D
E
e
0.050 BSC
1.27 BSC
H
L
0.394
0.419
0.050
10.00
0.40
10.65
1.27
0.016
α
0°
8°
0°
8°
Note: The control dimension is the millimeter column
Rev. 1.02
14
XR-T56L22
Notes
Rev. 1.02
15
XR-T56L22
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1997 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.02
16
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