XRT5683AIP-F [EXAR]
PCM Line Interface Chip; PCM线路接口芯片
| 型号： | XRT5683AIP-F |
| 厂家： | 
EXAR CORPORATION |
| 描述： | PCM Line Interface Chip |
| 文件： | 总12页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XR-T5683A
PCM Line
...the analog plus companyTM
Interface Chip
October 2010
FEATURES
D TTL Compatible Interface
D Device Can Be Used as a Line Interface Unit With-
D Single 5V Supply
out Clock Recovery
D Receiver Input Can Be Either Balanced or
APPLICATIONS
Unbalanced
D T1, T2, E1 & E2 Rates, PCM Line Interface
D Up To 8.448Mbps Operation In Both Tx and Rx
Directions
D Network Multiplexing and Terminating Equipment
GENERAL DESCRIPTION
The XR-T5683A is a PCM line interface chip consisting of attenuated by -10dB cable loss at one-half the bit rate. At
both transmit and receive circuitry. This device is offered
in a plastic dual in-line (PDIP) or in a surface mount
package (SOIC). The maximum bit rate of the chip is
8.448Mbps, and the signal level to the receiver can be
nominal supply voltage operation, the typical current
consumption is 40mA.
ORDERING INFORMATION
Operating
Temperature Range
Part No.
Package
18 Lead 300 Mil PDIP
18 Lead 300 Mil JEDEC SOIC
XR-T5683AIP
XR-T5683AID
-40°C to +85°C
-40°C to +85°C
BLOCK DIAGRAM
1
PDC
Positive
Threshold
Comparator
TTLBuffer
RPOS
11
RXDATA-
RXDATA+
2
TTLBuffer
TTLBuffer
Peak
Detector
8
RCLK
TE
Negative
Threshold
Comparator
3
4
10
RNEG
TANK BIAS
6
BIAS
BIAS
9
7
RV
CC
BIAS
5
RGND
TV
CC
18
Open Collector
Driver
TPOS 17
13
15
TXDATA+
TXDATA-
TCLK
16
12
TNEG
TGND
Open Collector
Driver
Figure 1. Block Diagram
14
Rev. 2.0.2
E2010
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
XR-T5683A
PIN CONFIGURATION
PDC
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TV
PDC
TV
CC
CC
RXDATA-
RXDATA+
TE
TPOS
TCLK
TXDATA-
TGND
TXDATA+
TNEG
RXDATA-
RXDATA+
TE
BIAS
TANK BIAS
RGND
TPOS
TCLK
TXDATA-
TGND
TXDATA+
TNEG
RPOS
BIAS
TANK BIAS
RGND
RCLK
RCLK
11 RPOS
10
RV
RV
RNEG
CC
CC
RNEG
18 Lead PDIP (0.300”)
18 Lead SOIC (JEDEC, 0.300”)
PIN DESCRIPTION
Pin #
Symbol
PDC
Type Description
1
2
3
4
5
6
7
Peak Detector Capacitor. This pin should be connected to a 0.1µF capacitor.
Receive Analog Input Positive. Line analog input.
RXDATA-
RXDATA+
TE
I
I
Receive Analog Input Negative. Line analog input.
O
O
O
Tank Excitation Output. This output connects to one side of the tank circuitry.
Bias. This output is to be connected to the center tap of the receive transformer.
Tank Bias. The tank circuitry is biased via this output.
BIAS
TANK BIAS
RGND
Receiver Ground. To minimize ground interference a separate pin is used to ground the
receive section.
8
RCLK
RVCC
O
Recovered Receive Clock. Recovered clock signal to the terminal equipment.
Receive Supply Voltage. 5V supply voltage to the receive section.
Receive Negative Data. Negative pulse data output to the terminal equipment (active low).
Receive Positive Data. Positive pulse data output to the terminal equipment (active low).
Transmit Negative Data. TNEG is valid while TCLK is high.
9
10
11
12
13
14
15
16
17
18
RNEG
RPOS
TNEG
TXDATA+
TGND
TXDATA-
TCLK
O
O
I
O
Transmit Positive Output. Transmit bipolar signal is driven to the line via a transformer.
Transmit Ground.
O
I
Transmit Negative Output. Transmit bipolar signal is driven to the line via a transformer.
Transmit Clock. Timing element for TPOS and TNEG.
TPOS
I
Transmit Positive Data. TPOS is valid while TCLK is high.
TVCC
Transmit Supply Voltage. 5V supply voltage to the transmit section.
Rev. 2.0.2
2
XR-T5683A
ELECTRICAL CHARACTERISTICS
Test Conditions: V = 5.0V "5%, T = 25°C, Unless Otherwise Specified.
CC
A
Parameters
Min.
Typ.
Max.
Unit
Conditions
DC Electrical Characteristics
Supply Voltage
4.75
5
5.25
V
Supply Current
40
55
mA
Total Current to Pin 9 & Pin 18
Transmitter Outputs Open
Receiver Section
Tank Drive Current
Clock Output Low
Clock Output High
Data Output Low
300
3.0
3.0
0.6
500
0.3
3.6
0.3
3.6
700
0.6
µA
V
Measured at Pin 4, VCC = 5V
Measured at Pin 8, IOL = 1.6mA
Measured at Pin 8, IOH = -400µA
Measured at Pin 10 & 11, IOL = 1.6mA
Measured at Pin 10 & 11, IOH = -400µA
V
0.6
V
Data Output High
Transmitter Section
Driver Output Low
Output Leakage Current
V
0.8
0
1.0
V
Measured at Pin 13 & 15, IOL = 40mA
100
µA
Measured in Off State, Output Pull-up to
+ 20V
Input High Voltage
2.2
VCC
V
Measured at Pin 12, 16 & 17, IOL= 40mA,
VOL = 1.0V
Input Low Voltage
Input Low Current
0.8
V
Measured at Pin 12, 16 & 17, Output Off
-1.6
mA
Measured at Pin 12, 16 & 17, Input Low
Voltage = 0. 4V
Input High Current
40
40
µA
Measured at Pin 12, 16 & 17, Input High
Voltage = 2.7V
Output Low Current
mA
Measured at Pin 13 & 15, VOL = 1.0V
AC Electrical Characteristics
Receiver Section
Input Level
6
6.6
Vpp
Vpp
Measured Between Pin 2 & 3
Loss Input Signal Alarm Level
1.6
Measured Between Pin 2 & 3, Alarm on
Pull Data Output High
Input Impedance at 8,448MHz
2.5
kΩ
Measured Between Pin 2 & 3, With
Sinewave Input
Clock Duty Cycle
35
35
50
20
50
65
75
%
Measured at Pin 8 at 2.0V
Clock Rise & Fall Time
Data Pulse Width
ns
Measured at Pin 8, CL = 15pF
% of
clock
period
Measured at Pin 10 & 11, at 1V DC
Level, Cable Loss = 0
Notes
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 2.0.2
3
XR-T5683A
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameters
Min.
Typ.
Max.
Unit
Conditions
AC Electrical Characteristics (Cont’d)
Transmitter Section
Pulse Width at 8.448MHz
Output Rise Time
53
65
25
25
ns
ns
ns
ns
Measured at Pin 13 & 15, See Figure 6
See Figure 5
12
12
Output Fall Time
See Figure 5
Output Pulse Imbalance
2.5
At 50% Output Level
Specifications are subject to change without notice
Notes
Bold face parameters are covered by production test and guaranteed over operating temperature range.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +. 2. 0V
Storage Temperature . . . . . . . . . . . . .-.65°C to +150°C
SYSTEM DESCRIPTION
The incoming bipolar PCM signal which is attenuated and The maximum low level current these output stages can
distorted by the cable is applied to the threshold
comparator and the peak detector . The peak detector
generates a DC reference for the threshold comparator
for data and clock extraction. An external tank circuit
tuned to the appropriate frequency is added for the later
operation. The clock signal, data (+) and data (-) all go
through a similar level shifter to be converted into TTL
level to be compatible for digital processing.
sink is 40mA. With full width data (NRZ) applied to the
inputs together with a synchronized clock, the output will
generate a bipolar signal when driving a center-tapped
transformer. A block diagram of the XR-T5683A is shown
in Figure 1.
The clock recovery uses an external tank circuit. The
receive data will create an excitation for the tank circuitry
which in turn will create a recovered, received clock
(RCLK).
In the transmit direction, the output drivers consist of two
identical TTL inputs with open collector output stages.
Rev. 2.0.2
4
XR-T5683A
Table 1 shows typical expected jitter tolerance. The
following measurements have been done at a
transmission rate of T1 (1.544MHz). (See Figure 2).
Jitter
10Hz
100Hz
500Hz
1kHz
2kHz
3kHz
4kHz
1.544Mbs in UI
Jitter
5kHz
8kHz
10kHz
32kHz
50kHz
77kHz
-
1.544Mbs in UI
>10UI
>10UI
>10UI
6.5UI
3.3UI
2.1UI
1.5UI
1.3UI
0.8UI
0.7UI
0.5UI
0.45UI
0.45UI
-
V
CC
= +5V "5%, T = 25°C
A
Table 1. Jitter Tolerance at 1.544Mbps with 6db Cable Loss
6db Cable Attenuation
Jitter
RPOS
RCLK
RNEG
TPOS
TCLK
TNEG
XR-T5683A
Generator
HP3785B
(transmitter
RXDATA+
RXDATA-
XR-T5683A
RX
side)
TX
Clock
Clock
Phase
Shift
TXDATA+
TXDATA-
Circuit
Pattern
Generator
HP3781B
Jitter
Analyzer
HP3785B
(Receive Side)
Figure 2. Jitter Measurement Set-up
Rev. 2.0.2
5
XR-T5683A
RXDATA+
RCLK Output at Pin 8
RPOS Output at Pin 11
RNEG Output at Pin 10
Figure 3. Receiver Timing Diagram With 1-1-1-1-1-1 Pattern
TCLK Clock to Pin 16
TPOS to Pin 17
TNEG to Pin 12
Bipolar Signal at Transformer Output
Figure 4. Transmitter Input Timing Diagram
Rev. 2.0.2
6
XR-T5683A
V
CC
= 5V
100
0.1µF
Output
Pin 13 & 15
2
CI=15pF
Pin 9 & 18
XR-T5683A
Input
0V
8.448MHz
Pulse
Generator
1
Pin 12,16,17
Pin 7 & 14
0V
Notes
1
2
Inputs that are not connected to pulse generator will be tied to V via 1K resistor.
C1 includes probe and jig capacitance.
CC
Figure 5. Test Circuit
59ns
<5ns
90%
<5ns
3V
0V
90%
Input Pulse
From Generator
1.5V
1.5V
10%
10%
15ns Typ.
15ns Typ.
+5V
90%
90%
Output From Pin 13
or Pin 15
50%
10%
50%
10%
Vol
Pulse Width
Fall Time
Rise Time
Figure 6. Transmitter Test Circuit and Switching Waveforms (Measured at 8.448Mbps)
Rev. 2.0.2
7
XR-T5683A
V
CC
0.1µF
18
TV
CC
T1
3
RXDATA+
TIP
390Ω
13
15
T2
TXDATA+
TXDATA-
TIP
56Ω
56Ω
2
5
RXDATA-
BIAS
RING
PE65415
1:1:1
RING
PE65415
1:1:1
0.1µF
4
6
TE
14
R
C
L
TGND
TCLK
TANK BIAS
0.1µF
16
17
12
11
10
8
TCLK
TPOS
TNEG
RPOS
RNEG
RCLK
TPOS
TNEG
RPOS
V
CC
9
1
RV
PDC
CC
RNEG
RCLK
0.1µF
0.1µF
7
RGND
U1
XR-T5683A
Figure 7. Application Circuit
Rev. 2.0.2
8
XR-T5683A
INPUT AND OUTPUT TRANSFORMERS
Pulse Engineering types PE-65415, PE-65771 or
PE-65835 transformers, may be used for both the input
torroid cores. They dif fer in physical size, operating
temperature range and voltage isolation. These
and output transformers. These three parts, which are all transformers are suitable for operation over the 1.544
1CT:2CT turns ratio and have similar electrical through 8.448Mbps range which includes T1, T2, E1 and
specifications, are wound on small, epoxy-encapsulated, E2.
Schott-Part
Number
Nominal
Inductance
Bit Rate
(MBIT/S)
Tuning Cap.
(See Note)
Mechanical Style
24443
48µHy with CT
RM 5 Core,
4 Pin Bobbin
1.544(T1)
2.048(E1)
6.312(T2)
6.448(E2)
200pF
100pF
100pF
60pF
24444
5µHy with CT
14 x 8 Potcore,
6 Pin Bobbin
Table 2. Inductor Selection
Notes
- Capacitor values shown combined with typical stray capacitance will normally resonate the tank circuit at the specific bit rate.
- The center-tapped inductor (L) eliminates clock amplifier overload by reducing the signal amplitude applied to T5683A pin W4.hile
feeding pseudo-random data into the receive input, tune this inductor for minimum jitter on the recovered clock (pin 8) as evidewon
an oscilloscope.
- R, which may be in the 20K to 50kΩ range, is optional and may be used to lower clock recovery circuit Q if desired.
Magnetic Supplier Information:
Pulse
John Marshall
Telecom Product Group
P.O. Box 12235
San Diego, CA 92112
Tel. (619) 674-8100
Fax. (619) 674-8262
Schott Corporation
1838 Elm Hill Pike, Suite 100
Nashville, TN 37210
Tel. (615) 889-8800
Fax (615) 885-0834
Rev. 2.0.2
9
XR-T5683A
18 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
18
1
10
9
E
1
E
D
A
2
A
Seating
Plane
L
C
α
A
1
B
e
e
e
B
A
B
1
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.145
0.015
0.115
0.014
0.210
0.070
0.195
0.024
0.070
0.014
0.925
0.325
0.280
3.68
0.38
2.92
0.36
0.76
0.20
21.46
7.62
6.10
5.33
1.78
4.95
0.56
1.78
0.38
23.50
8.26
7.11
A
1
A2
B
B 0.030
1
C
D
E
0.008
0.845
0.300
0.240
E
e
1
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
e
e
L
A
0.310
B
0.430
0.160
7.87
10.92
4.06
0.115
2.92
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 2.0.2
10
XR-T5683A
18 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
Rev. 1.00
D
18
1
10
E
H
9
C
A
Seating
Plane
α
e
B
A
1
L
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.093
0.004
0.013
0.009
0.447
0.291
0.104
0.012
0.020
0.013
0.463
0.299
2.35
0.10
0.33
0.23
11.35
7.40
2.65
0.30
0.51
0.32
11.75
7.60
A
B
1
C
D
E
e
0.050 BSC
1.27 BSC
H
L
0.394
0.419
0.050
10.00
0.40
10.65
1.27
0.016
α
0°
8°
0°
8°
Note: The control dimension is the millimeter column
Rev. 2.0.2
11
XR-T5683A
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained herein are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or efectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 2010 EXAR Corporation
Datasheet October 2010
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.0.2
12
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