XRT8020 [EXAR]
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS; 650 MHz的时钟与晶振倍频，LVDS输出，
| 型号： | XRT8020 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS |
| 文件： | 总12页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
NOVEMBER 2003
REV. 1.0.2
FEATURES
DESCRIPTION
• 575 MHz to 675 MHz operating range
• Low Output Jitter: 9ps rms typical at 622 MHz
• On Chip Crystal Oscillator Circuit
The XRT8020 is a monolithic analog phase locked
loop that provides a high frequency LVDS clock out-
put, using a low frequency crystal or reference clock.
It is designed for SONET/SDH and other low jitter ap-
plications.The high performance of the IC provides a
very low jitter LVDS clock output up to 650 MHz, while
operating at 3.3 volts. The XRT8020 has a selectable
8x, 16x or 32x internal multiplier for an external crys-
tal or signal source. The Output Enable pin provides
a true disconnect for the LVDS output. The very com-
pact (4 x 4 mm) low inductance package is ideal for
high frequency operation.
• Optimized for 15 to 40 MHz crystals
• Uses parallel fundamental mode crystal
• Selectable 8x, 16x or 32x multiplier
• Selectable ÷ 1 or ÷ 2 LVDS output
• LVDS output meets TIA/EIA 644A Specification
(2001)
• 3.3V ±10% Low power CMOS: 80 mW typical
• -40°C to +85°C operating temperature
• Extremely small 16-lead QFN package
APPLICATIONS
• Gigabit Ethernet
• SONET/SDH
• SPI - 4 Phase 2
• 8x, 16x or 32x Clock Multiplier for Computer and
Telecommunication Systems
FIGURE 1. BLOCK DIAGRAM OF THE XRT8020
15-40 MHz
Crystal
+3.3V
REXT
AVDD
AVDD
OVDD
XTAL2
10kΩ
XTAL1
12 - 20 pF
12 - 20 pF
Voltage Reference
&
XRT8020
Bias Generator
VCO
Calibration Logic
Oscillator
Circuit &
Input Buffer
Selectable
Phase
Detector
Charge
Pump
Loop
Filter
VCO
÷ 1 or ÷ 2
Divider
OUTP
OUTN
Feedback Divider
÷ 8, 16 or 32
LVDS Output
OGND
AGND
(Crystal)
AGND
AGND
FS1
PD
FS0
OE
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
FIGURE 2. XRT8020 PIN LOCATION - (TOP VIEW)
12
11
10
9
1
2
XRT8020
3
4
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
-40°C to +85°C
XRT8020IL
16 - Pin QFN
2
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
DESCRIPTION .................................................................................................................... 1
APPLICATIONS ......................................................................................................................................... 1
FEATURES ................................................................................................................................................ 1
Figure 1. Block Diagram of the XRT8020 ........................................................................................ 1
ORDERING INFORMATION ............................................................................................................... 2
Figure 2. XRT8020 Pin Location - (Top View) ................................................................................. 2
ABSOLUTE MAXIMUM RATINGS ....................................................................................................................... 3
ELECTRICAL CHARACTERISTICS ..................................................................................................................... 3
Figure 3. LVDS Output Waveforms and Test Circuits .................................................................... 5
1.0 Calibration ................................................................................................................................................. 5
TABLE 1: FREQUENCY SELECTION TABLE .............................................................................................. 5
TABLE 2: POWER-DOWN AND OUTPUT TRI-STATE SELECTION TABLE ....................................................... 5
2.0 Crystal selection ....................................................................................................................................... 6
3.0 data and plots ........................................................................................................................................... 6
Figure 4. Input Referenced Jitter Connection Diagram ................................................................. 6
Figure 5. Simplified Block Diagram of the XRT8020 and PECL Receiver .................................... 7
Figure 6. LVDS Differential Output .................................................................................................. 7
Figure 7. PECL Differential Output .................................................................................................. 8
Figure 8. PECL Single-Ended Outputs (Positive and Negative Output Referenced to Ground)
9
ORDERING INFORMATION ............................................................................................. 10
REVISIONS ................................................................................................................................................. 11
I
XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
PIN DESCRIPTION
PIN
1
NAME
TYPE
DESCRIPTION
3.3V ±10% Analog Supply for Crystal Oscillator
Analog Ground for Crystal Oscillator
AVDD
AGND
XTAL1
XTAL2
AGND
REXT
OE
2
3
I
Crystal pin 1 or external clock input
4
O
Crystal pin 2 (output drive for crystal)
Analog Ground
5
6
I
I
I
I
I
External Bias Resistor (10KΩ to ground)
Output Enable, Active low (Internal 50KΩ pull-down to ground)
Power Down, Active High (Internal 50KΩ pull-down to ground)
Frequency select "1" (Internal 50KΩ pull-down to ground)
Frequency select "0" (Internal 50KΩ pull-up to VDD)
Analog Ground
7
8
PD
9
FS1
10
11
12
13
14
15
16
FS0
AGND
OGND
OUTN
OUTP
OVDD
AVDD
Output Ground for LVDS outputs
O
O
LVDS negative output for 50Ω line
LVDS positive output for 50Ω line
3.3V ±10% Digital Supply for LVDS Output buffer
3.3V ±10% Analog Supply
ABSOLUTE MAXIMUM RATINGS
Supply voltage
VIN
-0.5 to 6.0 V
-0.5 to 6.0 V
Storage Temperature
Operating Temperature
ESD
-65°C to + 150°C
-40°C to + 85°C
>2,000 volts
10kΩ
REXT (±1%)
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
Supply Voltage
VDD
3.0
3.3
3.6
V
Supply current
IDD
IDD
25
30
6
mA VDD = 3.3V
Power Save Current
Input Digital High
Input Digital Low
Crystal Frequency
mA VDD = 3.3V, PD = 1, OEB = 0
VINH
VINL
2.0
15
V
V
Pins 7, 8, 9, 10
Pins 7, 8, 9, 10
0.8
27
MHz See Section 2.0 for Crystal Selection
3
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
PARAMETER
Crystal Frequency
SYMBOL
MIN
27
TYP
MAX
40
85
5
UNIT
CONDITIONS
MHz See Section 2.0 for Crystal Selection
MHz AC Coupled (FS0=1, FS1=1)
Clock Input Frequency
Power on Calibration time
72
ms
After VDD reaches 2.8V
NOTE: Calibration time = 16,000 clock cycles
Max Frequency Out
Max Frequency Out
Rise time
FOUT
FOUT
TR
575
285
675
340
MHz 624 MHz nominal FOUT (See Table 1)
MHz 312 MHz nominal FOUT (See Table 1)
350
350
ps
ps
CL = 5pF, RL = 100Ω, (20% - 80%)
CL = 5pF, RL = 100Ω, (20% - 80%)
Fall Time
TF
Duty cycle
45
55
%
ps
Ω
LVDS output
See Figure 3
Differential Output Skew
Output Loading
10
100
Output Voltage Swing
VOUT
VCM
250
1.0
450
1.4
-10
mV Magnitude of (OUTP-OUTN)
Common Mode Voltage
1.2
V
Output Short Circuit Current
-5.7
mA Current limit to ground, VDD or Vp to Vn
Cycle-to-Cycle Jitter
Cycle-to-Cycle Jitter
Accumulated Jitter
3
3
ps
ps
ps
ps
ps
ps
rms, at 624 MHz
rms, at 312 MHz
12
12
9
rms, at 624 MHz
Accumulated Jitter
rms, 312 MHz
Input Referenced Jitter
Input Referenced Jitter
rms at 622 MHz, See Figure 4
rms at 312 MHz, See Figure 4
9
4
XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
FIGURE 3. LVDS OUTPUT WAVEFORMS AND TEST CIRCUITS
LDVS Levels Test Circuit
LDVS Switching Test Circuit
OUTP
OUTP
50Ω
C
L = 5 pF
VOUT
VCM
VOUT
RL = 100Ω
CL = 5 pF
50Ω
OUTN
OUTN
LDVS Transition Time Waveform
OUTP
OUTN
50%
VCM (Differential)
50%
tskew
80%
80%
0V
0V (Differential)
VOUT
20%
20%
TR
TF
TABLE 1: FREQUENCY SELECTION TABLE
FS0
PIN 10
FS1
PIN 9
CRYSTAL OR CLOCK
FREQUENCY
INTERNAL
CAPACITOR
MULTIPLY
RATIO
OUTPUT
DIVIDE
OUTPUT
FREQUENCY
624 MHz
624 MHz
624 MHz
312 MHz
1
0
1
1
1
0
0
78.0 MHz Clock
39.0 MHz
NA
8x
1
1
1
2
12 pF
20 pF
20 pF
16x
32x
32x
19.5 MHz
0
19.5 MHz
NOTES:
1. Use Parallel Fundamental mode crystal
2. FS0 has an internal 50KΩ pull-up resistor to VDD
3. FS1 has an internal 50KΩ pull-down resistor to GND
TABLE 2: POWER-DOWN AND OUTPUT TRI-STATE SELECTION TABLE
PD
OE
STATUS
NOTES:
PIN 8 PIN 7
1. “X" = Don't care
1
0
X
1
Outputs tri-stated and chip Powered-down
Output tri-stated
2. PD and OE have an internal 50KΩ pull-down resis-
tor to ground.
1.0 CALIBRATION
5
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
The XRT8020 synthesizer jitter performance is optimized by calibration of its Voltage Controlled Oscillator
(VCO) upon initial power application. This power ON calibration procedure is automatic and completely trans-
parent to the user. It is initiated automatically upon first application of VDD. In order to bring the center fre-
quency of the VCO close to the desired output frequency, the VCO bias current is adjusted via a current DAC
at initial power application. The center frequency of VCO is checked against input reference frequency and cal-
ibrated internally to the desired output frequency value. These bias voltage trim bits are then held in latches for
as long as the VDD is held above 2.7V (minimum specified operational value of VDD). The user should note
following important facts about this calibration procedure for proper operation of the XRT8020:
• For proper operation of the chip and to achieve lowest jitter, the user should follow layout guidelines as
described in the User Guide.
• An input crystal of appropriate frequency should be connected at XTAL1 and XTAL2 pins before power is
applied to the chip.
• All VDD pins should be tied to 3.3V ±10% simultaneously.
• The power supply should turn on without bouncing below 2.0V smoothly to its specified value in no more
than 50msec.
• The calibration takes place during VDD ramp up between 2.6V to 3V values. Once the VDD reaches and
maintains 3.0V, the chip retains the calibrated VCO bias voltages in internal latches for proper operation.
• To change a widely different value of crystal or input reference frequency, it is recommended to power
down the chip by bringing VDD to 0V and restarting after the change in frequency has occurred.
2.0 CRYSTAL SELECTION
It is recommended that a Fundamental Mode Crystal be used as the timing reference of the XRT8020. The fol-
lowing part has been qualified by EXAR:
CITIZEN Quartz Crystals
20 MHz : HCM49-20.000MABJT
40 MHz : HCM49-40.000MABJT
3.0 DATA AND PLOTS
All plots were recorded using the following parameters and test setup:
• VDD = 3.3 V
• 2” 100Ω Differential Transmission Lines (from LVDS outputs to receiver inputs)
• Fundamental Mode Crystal of 20 MHz
• Vref = 1.5 V (PECL Receiver)
FIGURE 4. INPUT REFERENCED JITTER CONNECTION DIAGRAM
Outp
Tektronix
P6330 Differential Probe
XRT8020
Channel 1
Channel 2
Outn
MAX9111ESA
20.0Mhz
Crystal
Tektronix
P6245 TDS 500/600
Tektronix
TDS7404
6
XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
FIGURE 5. SIMPLIFIED BLOCK DIAGRAM OF THE XRT8020 AND PECL RECEIVER
100ohm Transmission Lines
XRT8010/20
Clock Synthesizer
LVDS-To-PECL
Receiver
FIGURE 6. LVDS DIFFERENTIAL OUTPUT
LVDS Differential Outputs
Freq 640.1 MHz
Ampl 824.0 mV
Ch1 200 mV
M 500 pS
7
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
FIGURE 7. PECL DIFFERENTIAL OUTPUT
REV. 1.0.2
PECL Differential Outputs
Freq
640.0 MHz
Ampl
1.42 V
Ch1 500 mV
M 500 pS
8
XRT8020
REV. 1.0.2
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
FIGURE 8. PECL SINGLE-ENDED OUTPUTS (POSITIVE AND NEGATIVE OUTPUT REFERENCED TO GROUND)
PECL Single-Ended Outputs
POS Output
Freq(1) 640.3 MHz
Freq(2) 639.9 MHz
Ampl(1) 520.0 mV
Ampl(2) 528.0 mV
NEG Output
Ch1 200 mV
Ch2 200mV
M 500 pS
9
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
°
°
16-Lead QFN
XRT8020IL
-40 C to +85 C
PACKAGE DIMENSIONS
16 LEAD QUAD FLAT NO LEAD
(4 mm x 4 mm, 0.65 pitch QFN)
Rev. 1.01
θ
Note: the actual center pad
is metallic and the size (D2)
is device-dependent w/ a
typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
MAX
A
A1
A2
D
0.031
0.039
0.80
0.00
0.00
3.90
3.65
2.24
0.23
1.00
0.05
1.00
4.10
3.85
2.54
0.38
0.000
0.000
0.154
0.144
0.088
0.009
0.002
0.039
0.161
0.152
0.100
0.015
D1
D2
b
e
0.0256 BSC
0.65 BSC
L
0.014
0°
0.030
12°
0.35
0°
0.75
12°
θ
10
XRT8020
650 MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS
REV. 1.0.2
REVISIONS
P1.0.1 Accumulated output jitter in electrical specs changed from 25 ps @ 624MHz to 20 @ 622Mhz and
TBD to 20 ps @312Mhz. Pin 9 has internal a pull-down resistor instead of pull-up. Table 1 FS0 and FS1 bit
pattern changed.
P1.0.2 Changed typical jitter to 6ps and changed package to QFN
P1.0.3 Corrected package dimension dimension "e" to 0.65 mm BSC. Updated electrical tables. Added de-
scriptive sections on Calibration, Crystal Selection and Data and Plots.
1.0.0 Final Release. Added intrinsic jitter measurements to the electrical characteristics.
1.0.1 Changed the page numbering. Changed the QLP to QFN in the Features on page 1.
1.0.2 Changed the Package Drawing and Dimensions.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order
to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of
any circuits described herein, conveys no license under any patent or other right, and makes no represen-
tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for
illustration purposes and may vary depending upon a user’s specific application. While the information in
this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where
the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-
tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury
or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-
ration is adequately protected under the circumstances.
Copyright 2003 EXAR Corporation
Datasheet November 2003.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
11
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