74AC74SC_NL [FAIRCHILD]
Dual D-Type Positive Edge-Triggered Flip-Flop; 双D型正边沿触发触发器
| 型号： | 74AC74SC_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual D-Type Positive Edge-Triggered Flip-Flop |
| 文件： | 总10页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised February 2005
74AC74 • 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
Features
The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
■ ICC reduced by 50%
■ Output source/sink 24 mA
■ ACT74 has TTL-compatible inputs
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Ordering Code:
Package
Order Number
Package Description
Number
74AC74SC
M14A
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC74SC_NL
(Note 1)
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC74SJ
M14D
MTC14
MTC14
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC74MTC
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC74MTCX_NL
(Note 2)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC74PC
N14A
M14A
M14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT74SC
74ACT74SC_NL
(Note 1)
74ACT74SJ
M14D
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT74SJX_NL
(Note 2)
74ACT74MTC
74ACT74PC
MTC14
N14A
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JECED J-STD-020B.
Note 1: “_NL” indicates lead-free product (per JEDEC J-STD-020B).
Note 2: “_NL” indicates lead-free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009920
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Connection Diagram
Pin Descriptions
Pin Names
D1, D2
Description
Data Inputs
CP1, CP2
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
CD1, CD2
SD1, SD2
Q1, Q1, Q2, Q2
Logic Symbols
IEEE/IEC
Truth Table
(Each Half)
Inputs
Outputs
SD
CD
CP
D
Q
Q
L
H
L
H
L
X
X
X
X
X
X
H
L
H
L
L
H
H
H
L
H
H
H
H
H
H
H
L
L
H
L
X
Q0
Q0
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
LOW-to-HIGH Clock Transition
Q
(Q ) Previous Q (Q) before LOW-to-HIGH Transition of Clock
0
0
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2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions
Supply Voltage (VCC
DC Input Diode Current (IIK
VI 0.5V
)
0.5V to 7.0V
)
Supply Voltage (VCC
)
20 mA
20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI VCC 0.5V
ACT
DC Input Voltage (VI)
0.5V to VCC 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
VO 0.5V
)
0V to VCC
20 mA
20 mA
Operating Temperature (TA)
Minimum Input Edge Rate ( V/ t)
AC Devices
40 C to 85 C
VO VCC 0.5V
DC Output Voltage (VO)
DC Output Source
0.5V to VCC 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate ( V/ t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
65 C to 150 C
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140 C
Note 3: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH
2.1
2.1
3.15
3.85
0.9
V
0.1V
0.1V
IH
OUT
Level Input
Voltage
2.25
2.75
1.5
3.15
3.85
0.9
V
or V
CC
Maximum LOW
Level Input
Voltage
V
0.1V
0.1V
IL
OUT
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or V
CC
Minimum HIGH
Level Output
Voltage
OH
4.4
4.4
I
50 A
OUT
5.4
5.4
V
V or V
IL IH
IN
OH
OH
OH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
12 mA
24 m
V
V
24 m (Note 4)
V
Maximum LOW
Level Output
Voltage
0.002
0.001
0.001
OL
0.1
0.1
I
50
A
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
OL
IL
3.0
4.5
5.5
5.5
5.5
5.5
0.36
0.36
0.36
0.1
0.44
0.44
0.44
1.0
I
I
I
12 mA
24 mA
V
24 mA (Note 4)
V , GND
CC
I
I
I
I
(Note 6) Maximum Input Leakage Current
A
mA
mA
V
V
V
V
IN
I
Minimum Dynamic
Output Current (Note 5)
Maximum Quiescent
Supply Current
75
1.65V Maximum
3.85V Minimum
OLD
OHD
CC
OLD
OHD
IN
75
V
CC
5.5
2.0
20.0
A
(Note 6)
or GND
Note 4: All outputs loaded; thresholds on input associated with output under test.
Note 5: Maximum test duration 2.0 ms, one output loaded at a time.
Note 6: I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
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4
DC Electrical Characteristics for ACT
V
T
25 C
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
V
V
V
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
0.1V
0.1V
0.1V
0.1V
IH
OUT
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
or V
CC
Maximum LOW Level
Output Voltage
1.5
V
IL
OUT
1.5
or V
CC
Minimum HIGH Level
Output Voltage
4.49
5.49
I
50 A
OH
OUT
V
V or V
IL IH
IN
OH
OH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
I
24 mA
24 mA (Note 7)
V
Maximum LOW Level
Output Voltage
0.001
0.001
50
A
OL
OUT
0.1
0.1
V
V
or V
IH
IN
OL
OL
IL
4.5
5.5
0.36
0.36
0.44
0.44
I
I
24 mA
24 mA (Note 7)
I
I
Maximum Input
Leakage Current
Maximum
V
V
, GND
IN
I
CC
5.5
5.5
0.1
1.0
1.5
A
V
V
2.1V
CCT
I
CC
0.6
mA
I
/Input
CC
I
I
I
Minimum Dynamic
Output Current (Note 8)
Maximum Quiescent
Supply Current
5.5
5.5
75
75
mA
mA
V
V
V
1.65V Maximum
3.85V Minimum
OLD
OHD
CC
OLD
OHD
IN
V
CC
5.5
2.0
20.0
A
or GND
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
V
T
25 C
T
40 C to 85 C
50 pF
Min Max
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
(Note 9)
3.3
Units
L
Min
100
140
3.5
2.5
4.0
3.0
4.5
3.5
3.5
2.5
Typ
Max
f
Maximum Clock
Frequency
125
160
8.0
6.0
10.5
8.0
8.0
6.0
8.0
6.0
95
125
2.5
2.0
3.5
2.5
4.0
3.0
3.5
2.5
MAX
MHz
ns
5.0
t
Propagation Delay
or S to Q or Q
3.3
12.0
9.0
13.0
10.0
13.5
10.5
16.0
10.5
14.5
10.5
PLH
C
5.0
Dn
Dn
n
n
n
t
Propagation Delay
or S to Q or Q
3.3
12.0
9.5
PHL
ns
C
5.0
Dn
Dn
n
t
Propagation Delay
CP to Q or Q
3.3
13.5
10.0
14.0
10.0
PLH
ns
5.0
n
n
n
t
Propagation Delay
CP to Q or Q
3.3
PHL
ns
5.0
n
n
n
Note 9: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
5
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AC Operating Requirements for AC
V
T
25 C
T
40 C to 85 C
50 pF
Guaranteed Minimum
CC
A
A
C
50 pF
C
L
Symbol
Parameter
(V)
(Note 10)
3.3
Units
L
Typ
1.5
1.0
t
Set-up Time, HIGH or LOW
4.0
4.5
3.0
0.5
0.5
S
ns
ns
D
to CP
5.0
3.0
0.5
0.5
n
n
t
Hold Time, HIGH or LOW
to CP
3.3
2.0
1.5
H
D
5.0
n
n
t
CP or C or S
Dn
3.3
5.0
3.3
5.0
3.0
2.5
2.5
2.0
5.5
4.5
0
7.0
5.0
0
W
n
Dn
ns
ns
Pulse Width
t
Recovery Time
rec
C
or S to CP
0
0
Dn
Dn
Note 10: Voltage Range 3.3 is 3.3V 0.3V
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics for ACT
V
T
25 C
50 pF
Typ
T
A
40 C to 85 C
CC
A
C
C
50 pF
Max
Symbol
Parameter
(V)
Units
L
L
(Note 11)
Min
Max
Min
f
Maximum Clock
MAX
5.0
5.0
5.0
5.0
5.0
145
210
5.5
6.0
7.5
6.0
125
2.5
3.0
4.0
3.0
MHz
ns
Frequency
t
t
t
t
Propagation Delay
PLH
PHL
PLH
PHL
3.0
3.0
4.0
3.5
9.5
10.5
11.5
13.0.
11.5
C
or S to Q or Q
Dn n
Dn
n
n
Propagation Delay
or S to Q or Q
10.0
11.0
10.0
ns
C
Dn
Dn
n
Propagation Delay
CP to Q or Q
ns
n
n
n
Propagation Delay
CP to Q or Q
ns
n
n
n
Note 11: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements for ACT
V
T
25 C
50 pF
T
A
40 C to 85 C
C 50 pF
L
CC
A
C
Symbol
Parameter
(V)
Units
L
(Note 12)
Typ
Guaranteed Minimum
t
Set-up Time, HIGH or LOW
S
H
5.0
5.0
1.0
3.0
1.0
3.5
ns
ns
D
to CP
n
n
t
Hold Time, HIGH or LOW
to CP
0.5
1.0
D
n
n
t
t
CP or C or S
n Dn Dn
W
5.0
5.0
3.0
2.5
5.0
0
6.0
0
ns
ns
Pulse Width
Recovery Time
rec
C
or S to CP
Dn
Dn
Note 12: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Typ
4.5
35.0
Units
pF
Conditions
C
C
Input Capacitance
V
V
OPEN
5.0V
IN
CC
CC
Power Dissipation Capacitance
pF
PD
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6
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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