74ACT174SCXR [FAIRCHILD]
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16;
| 型号： | 74ACT174SCXR |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, CMOS, PDSO16, 0.150 INCH, MS-012, SOIC-16 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised October 2000
74AC174 • 74ACT174
Hex D-Type Flip-Flop with Master Reset
General Description
Features
The AC/ACT174 is a high-speed hex D-type flip-flop. The
device is used primarily as a 6-bit edge-triggered storage
register. The information on the D inputs is transferred to
storage during the LOW-to-HIGH clock transition. The
device has a Master Reset to simultaneously clear all flip-
flops.
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
■ ACT174 has TTL-compatible inputs
Ordering Code:
Order Number Package Number
Package Description
74AC174SC
74AC174SJ
M16A
M16D
MTC16
N16E
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC174MTC
74AC174PC
74ACT174SC
74ACT174SJ
74ACT174MTC
74ACT174PC
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M16A
M16D
MTC16
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0–D5
CP
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
MR
Q0–Q5
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS009935
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Functional Description
Truth Table
The AC/ACT174 consists of six edge-triggered D-type flip-
flops with individual D inputs and Q outputs. The Clock
(CP) and Master Reset (MR) are common to all flip-flops.
Each D input’s state is transferred to the corresponding flip-
flop’s output following the LOW-to-HIGH Clock (CP) transi-
tion. A LOW input to the Master Reset (MR) will force all
outputs LOW independent of Clock or Data inputs. The AC/
ACT174 is useful for applications where the true output
only is required and the Clock and Master Reset are com-
mon to all storage elements.
Inputs
Output
MR
L
CP
D
X
H
L
Q
L
X
H
H
L
H
H
L
X
Q
H = HIGH Voltage Level
L = LOW Voltage Level
= LOW-to-HIGH Transition
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
O = −0.5V
)
0V to VCC
V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
V = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to V CC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
±50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
VOUT = 0.1V
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.1
2.1
3.15
3.85
0.9
2.25
2.75
1.5
3.15
3.85
0.9
V
or VCC − 0.1V
VIL
Maximum LOW Level
Input Voltage
VOUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH Level
Output Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
V
IN = VIL or VIH
IOH = −12 mA
OH = −24 mA
IOH = −24 mA (Note 2)
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
V
V
I
VOL
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
0.1
0.1
IOUT = 50 µA
0.1
0.1
VIN = VIL or VIH
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA (Note 2)
VI = VCC
V
IIN
Maximum Input
5.5
±0.1
±1.0
µA
(Note 4)
IOLD
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
or GND
5.5
5.5
75
mA
mA
V
OLD = 1.65V Max
VOHD = 3.85V Min
IN = VCC
IOHD
−75
ICC
V
5.5
4.0
40.0
µA
(Note 4)
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
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DC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
VIH
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
1.5
2.0
0.8
0.8
4.4
5.4
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
VIN = VIL or VIH
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
IOH = −24 mA
I
I
OH = −24 mA (Note 5)
OUT = 50 µA
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
0.1
0.1
VIN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
IOL = 24 mA
IOL = 24 mA (Note 5)
IIN
Maximum Input
Leakage Current
Maximum
5.5
5.5
±0.1
±1.0
µA
VI = VCC, GND
VI = VCC − 2.1V
ICCT
0.6
1.5
mA
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
−75
5.5
4.0
40.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
T
C
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
L = 50 pF
VCC
(V)
C
Symbol
Parameter
Units
(Note 7)
Min
Typ
100
125
9.0
6.0
8.5
6.0
9.0
7.0
Max
Min
Max
fMAX
Maximum Clock
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
90
100
2.0
1.5
2.0
1.5
2.5
1.5
70
100
1.5
1.0
1.5
1.0
2.0
1.5
MHz
ns
Frequency
tPLH
tPHL
tPHL
Propagation Delay
CP to Qn
11.5
8.5
12.5
9.5
Propagation Delay
CP to Qn
11.0
8.0
12.0
9.0
ns
Propagation Delay
MR to Qn
11.5
9.0
12.5
10.5
ns
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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AC Operating Requirements for AC
T
C
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
VCC
(V)
CL = 50 pF
Symbol
Parameter
Units
(Note 8)
Typ
2.5
2.0
1.0
0.5
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to CP
3.3
5.0
3.3
5.0
6.5
7.0
5.5
3.0
3.0
ns
ns
5.0
3.0
3.0
tH
Hold Time, HIGH or LOW
Dn to CP
tW
MR Pulse Width, LOW
3.3
5.0
3.3
5.0
3.3
5.0
1.0
1.0
1.0
1.0
0
5.5
5.0
5.5
5.0
2.5
2.0
7.0
5.0
7.0
5.0
2.5
2.0
ns
ns
ns
tW
CP Pulse Width
tREC
Recovery Time
MR to CP
0
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
T
C
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
VCC
(V)
CL = 50 pF
Symbol
Parameter
Units
(Note 9)
Min
Typ
Max
Min Max
fMAX
Maximum Clock
Frequency
5.0
5.0
5.0
5.0
165
200
7.0
7.0
6.5
140
1.5
1.5
1.5
MHz
ns
tPLH
tPHL
tPHL
Propagation Delay
CP to Qn
1.5
1.5
1.5
10.5
10.5
9.5
11.5
11.5
11.0
Propagation Delay
CP to Qn
ns
Propagation Delay
MR to Qn
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
T
C
A = +25°C
L = 50 pF
T
A = −40°C to +85°C
VCC
(V)
CL = 50 pF
Symbol
Parameter
Units
(Note 10)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
Dn to CP
5.0
5.0
0.5
1.5
1.5
2.0
ns
ns
tH
Hold Time, HIGH or LOW
Dn to CP
1.0
2.0
tW
MR Pulse Width, LOW
CP Pulse Width, HIGH or LOW
Recovery Time
5.0
5.0
1.5
1.5
3.0
3.0
3.5
3.5
ns
ns
tW
trec
5.0
−1.0
0.5
0.5
ns
MR to CP
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
pF
Conditions
CIN
Input Capacitance
4.5
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
85.0
pF
V
5
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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