74LCX373MSAX [FAIRCHILD]
Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs; 低电压八路透明锁存器，具有5V容限输入和输出
| 型号： | 74LCX373MSAX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs |
| 文件： | 总14页 (文件大小：325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1994
Revised October 2005
74LCX373
Low Voltage Octal Transparent Latch
with 5V Tolerant Inputs and Outputs
General Description
Features
The LCX373 consists of eight latches with 3-STATE outputs for
bus organized system applications. The device is designed for
5V tolerant inputs and outputs
2.3V–3.6V V specifications provided
CC
low voltage (3.3V or 2.5V) V
applications with capability of
CC
interfacing to a 5V signal environment.
8.0 ns t max (V
3.3V), 10 A I max
CC
PD
CC
The LCX373 is fabricated with an advanced CMOS technology
to achieve high speed operation while maintaining CMOS low
power dissipation.
Power-down high impedance inputs and outputs
Supports live insertion/withdrawal (Note )
24 mA output drive (V
3.0V)
CC
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
Human Body Model 2000V
Machine Model 200V
Leadless Pb-Free DQFN package
Note 1: To ensure the high-impedance state during power up or down, OE should be
tied to V through a pull-up resistor: the minimum value or the resistor is determined
CC
by the current-sourcing capability of the driver.
Ordering Code:
Package
Order Number
Package Description
Number
74LCX373WM
74LCX373SJ
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20D
74LCX373BQX
(Preliminary)
(Note 2)
MLP020B
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 4.5mm
74LCX373MSA
74LCX373MTC
MSA20
MTC20
MTC20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74LCX373MTCX_NL
(Note 3)
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 2: DQFN package available in Tape and Reel only.
Note 3: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS011995
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Logic Symbols
Pin Descriptions
Pin Names
Description
D –D
Data Inputs
0
7
LE
Latch Enable Input
OE
Output Enable Input
3-STATE Latch Outputs
O –O
0
7
IEEE/IEC
Truth Table
Inputs
Outputs
LE
OE
Dn
On
X
H
H
L
H
L
L
L
X
L
Z
L
H
X
H
O
0
H
L
Z
X
O
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
Connection Diagrams
Previous O before HIGH-to-LOW transition of Latch Enable
0
0
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
Functional Description
The LCX373 contains eight D-type latches with 3-STATE stan-
dard outputs. When the Latch Enable (LE) input is HIGH, data
on the D inputs enters the latches. In this condition the latches
n
are transparent, i.e. a latch output will change state each time
its D input changes. When LE is LOW, the latches store the
information that was present on the D inputs a setup time pre-
ceding the HIGH-to-LOW transition of LE. The 3-STATE stan-
dard outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2-state mode.
When OE is HIGH, the standard outputs are in the high imped-
ance mode but this does not interfere with entering new data
into the latches.
Pad Assignments for DQFN
(Top View)
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2
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings(Note 4)
Symbol
Parameter
Value
Conditions
Units
V
V
V
Supply Voltage
0.5 to 7.0
0.5 to 7.0
0.5 to 7.0
V
CC
DC Input Voltage
V
I
DC Output Voltage
Output in 3-STATE
0.5 Output in HIGH or LOW State (Note 5)
O
V
0.5 to V
CC
I
I
DC Input Diode Current
DC Output Diode Current
50
V
V
V
GND
GND
mA
mA
IK
I
50
50
OK
O
O
V
CC
I
I
I
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
50
mA
mA
mA
C
O
100
CC
GND
100
T
65 to 150
STG
Recommended Operating Conditions (Note 6)
Symbol
Parameter
Min
2.0
1.5
0
Max
3.6
Units
V
Supply Voltage
Operating
Data Retention
CC
V
V
V
3.6
V
V
Input Voltage
5.5
I
Output Voltage
HIGH or LOW State
3-STATE
0
V
CC
O
0
5.5
24
12
8
I
/I
Output Current
V
V
V
3.0V 3.6V
2.7V 3.0V
2.3V 2.7V
OH OL
CC
CC
CC
mA
T
Free-Air Operating Temperature
40
0
85
10
C
A
t/ V
Input Edge Rate, V
0.8V 2.0V, V
3.0V
ns/V
IN
CC
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will
define the conditions for actual device operation.
Note 5: I Absolute Maximum Rating must be observed.
O
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
V
T
40 C to 85 C
Max
CC
A
Symbol
Parameter
Conditions
Units
(V)
2.3 2.7
2.7 3.6
2.3 2.7
2.7 3.6
2.3 3.6
2.3
Min
1.7
2.0
V
V
V
HIGH Level Input Voltage
IH
V
V
LOW Level Input Voltage
HIGH Level Output Voltage
0.7
0.8
IL
I
I
I
I
I
I
I
I
I
I
100
A
V
CC
0.2
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
8 mA
1.8
2.2
2.4
2.2
12 mA
18 mA
24 mA
2.7
V
V
3.0
3.0
V
LOW Level Output Voltage
100
8 mA
A
2.3 3.6
2.3
0.2
0.6
OL
12 mA
16 mA
24 mA
2.7
0.4
3.0
0.4
3.0
0.55
5.0
I
I
Input Leakage Current
0
0
V
V
V
5.5V
5.5V
2.3 3.6
A
A
A
A
I
I
3-STATE Output Leakage
OZ
O
2.3 3.6
5.0
V
or V
IL
I
IH
I
I
Power-Off Leakage Current
Quiescent Supply Current
V or V
5.5V
or GND
0
10
10
10
OFF
CC
I
O
V
V
2.3 3.6
2.3 3.6
I
CC
3.6V V , V
5.5V (Note 7)
I
O
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4
DC Electrical Characteristics (Continued)
V
T
40 C to 85 C
CC
A
Symbol
Parameter
Increase in I per Input
Conditions
0.6V
Units
(V)
Min
Max
I
V
V
CC
2.3 3.6
500
A
CC
CC
IH
Note 7: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
40 C to 85 C, R
500
A
L
V
3.3V 0.3V
50pF
Max
V
2.7V
V
CC
2.5V 0.2V
30pF
Max
CC
CC
Symbol
Parameter
Units
C
C
50pF
C
L
L
L
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.3
Min
Max
9.0
9.0
9.5
9.5
9.5
9.5
8.5
8.5
Min
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
4.0
2.0
4.0
t
t
t
t
t
t
t
t
t
t
t
t
t
Propagation Delay
to O
8.0
8.0
8.5
8.5
8.5
8.5
7.5
7.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
1.5
3.3
9.6
9.6
PHL
ns
ns
ns
ns
D
PLH
PHL
PLH
PZL
PZH
PLZ
PHZ
S
n
n
Propagation Delay
LE to O
10.5
10.5
10.5
10.5
9.0
n
Output Enable Time
Output Disable Time
9.0
Setup Time, D to LE
ns
ns
ns
n
Hold Time, D to LE
n
H
LE Pulse Width
Output to Output Skew
(Note 8)
W
1.0
1.0
OSHL
OSLH
ns
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies
to any outputs switching in the same direction, either HIGH-to-LOW (t ) or LOW-to-HIGH (t ).
OSHL
OSLH
Dynamic Switching Characteristics
V
T
25 C
CC
A
Symbol
Parameter
Quiet Output Dynamic Peak V
Conditions
Units
(V)
3.3
2.5
3.3
2.5
Typical
0.8
V
V
C
C
C
C
50 pF, V
3.3V, V
0V
0V
0V
0V
OLP
OL
L
L
L
L
IH
IL
IL
V
V
30pF, V 2.5V, V
0.6
I
IL
Quiet Output Dynamic Valley V
50 pF, V
3.3V, V
30pF, V 2.5V, V
0.8
OLV
OL
IH
0.6
I
IL
Capacitance
Symbol
Parameter
Conditions
Open, V 0V or V
Typical
Units
C
C
C
Input Capacitance
Output Capacitance
V
7
8
pF
pF
pF
IN
CC
CC
CC
I
CC
V
V
3.3V, V 0V or V
I CC
OUT
PD
Power Dissipation Capacitance
3.3V, V 0V or V , f 10 MHz
25
I
CC
5
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AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (C includes probe and jig capacitance)
L
Test
Switch
t
, t
Open
PLH PHL
t
, t
6V at V
3.3 0.3V
2.5 0.2V
PZL PLZ
CC
V
x 2 at V
CC
CC
t
,t
GND
PZH PHZ
3-STATE Output High Enable and
Disable Times for Logic
Waveform for Inverting and Non-Inverting Functions
Setup Time, Hold Time and Recovery Time for Logic
Propagation Delay. Pulse Width and t Waveforms
rec
t
and t
fall
rise
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, t = t = 3ns)
r
f
VCC
Symbol
3.3V r 0.3V
1.5V
2.7V
1.5V
1.5V
2.5V r 0.2V
V
V
/2
mi
CC
V
1.5V
V
/2
mo
CC
V
V
0.3V
0.3V
V
0.3V
0.3V
V
OL
0.15V
0.15V
x
y
OL
OL
V
V
V
V
OH
OH
OH
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6
Schematic Diagram Generic for LCX Family
7
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Tape and Reel Specification
Tape Format for DQFN
Package
Tape
Number
Cavity
Cover Tape
Designator
Section
Leader (Start End)
Carrier
Cavities
125 (typ)
3000
Status
Empty
Filled
Status
Sealed
Sealed
Sealed
BQX
Trailer (Hub End)
75 (typ)
Empty
TAPE DIMENSIONS inches (millimeters)
REEL DIMENSIONS inches (millimeters)
Tape Size
A
13.0
B
0.059
C
0.512
D
0.795
N
2.165
W1
0.488
(12.4)
W2
0.724
(18.4)
12 mm
(330.0)
(1.50)
(13.00)
(20.20)
(55.00)
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8
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm
Package Number MLP020B
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
Package Number MSA20
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12
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
13
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION
As used herein:
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
2. A critical component is any component of a life support
device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of terms
Datasheet Identification Product Status
Definition
Advance Information
Formative or In Design This datasheet contains the design specifications for product develop-
ment. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data, and supplementary data will
be published at a later date. Fairchild Semiconductor reserves the right
to make changes at any time without notice in order to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice in order
to improve design.
This datasheet contains specifications on a product that has been dis-
continued by Fairchild Semiconductor. The datasheet is printed for ref-
erence information only.
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14
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