74VCX16601MTDX [FAIRCHILD]
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs; 低电压18位通用总线收发器具有3.6V容限输入和输出
| 型号： | 74VCX16601MTDX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs |
| 文件： | 总11页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 1998
Revised October 2004
74VCX16601
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16601 is an 18-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Features
■ 1.4V to 3.6V VCC supply operation
■ 3.6V tolerant inputs and outputs
■ tPD (A to B, B to A)
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. The clock can be con-
trolled by the clock-enable (CLKENAB and CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is HIGH. When LEAB is
LOW, the A data is latched if CLKAB is held at a HIGH-to-
LOW logic level. If LEAB is LOW, the A bus data is stored
in the latch/flip-flop on the LOW-to-HIGH transition of
CLKAB. When OEAB is LOW, the outputs are active. When
OEAB is HIGH, the outputs are in the high-impedance
state.
2.9 ns max for 3.0V to 3.6V VCC
■ Power-down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■ Static Drive (IOH/IOL
)
±24 mA @ 3.0V VCC
■ Uses patented noise/EMI reduction circuitry
■ Latchup performance exceeds 300 mA
■ ESD performance:
Human body model > 2000V
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, CLKBA and CLKENBA.
Machine model >200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
The VCX16601 is designed for low voltage (1.4V to 3.6V)
VCC applications with I/O capability up to 3.6V.
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
The VCX16601 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX16601GX
(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74VCX16601MTD
(Note 3)
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2004 Fairchild Semiconductor Corporation
DS500126
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Connection Diagrams
Pin Descriptions
Pin Assignment for TSSOP
Pin Names
Description
OEAB, OEBA
LEAB, LEBA
Output Enable Inputs (Active LOW)
Latch Enable Inputs
CLKAB, CLKBA
Clock Inputs
CLKENAB, CLKENBA Clock Enable Inputs
A1–A18
B1–B18
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
A2
A4
A1
A3
OEAB CLKENAB
B1
B3
B2
B4
LEAB
VCC
CLKAB
VCC
A6
A5
B5
B6
A8
A7
GND
GND
GND
VCC
GND
GND
GND
VCC
B7
B8
A10
A12
A14
A9
B9
B10
B12
B14
A11
A13
B11
B13
G
H
J
A16
A17
A15 OEBA CLKBA
A18
B15
B16
B17
LEBA CLKENBA B18
Truth Table
(Note 4)
Inputs
CLKENAB OEAB LEAB CLKAB An
Outputs
Bn
X
X
X
H
H
L
H
L
L
L
L
L
L
L
L
X
H
H
L
L
L
L
L
L
X
X
X
X
X
↑
X
L
Z
L
Pin Assignment for FBGA
H
X
X
L
H
B
0 (Note 5)
B0 (Note 5)
L
L
↑
H
X
X
H
L
L
B0 (Note 5)
B0 (Note 6)
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
(Top Thru View)
Note 4: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Note 5: Output level before the indicated steady-state input conditions
were established.
Note 6: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
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2
Logic Diagram
3
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Absolute Maximum Ratings(Note 7)
Recommended Operating
Conditions (Note 9)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Operating
1.4V to 3.6V
Outputs 3-Stated
−0.5V to +4.6V
−0.5 to VCC + 0.5V
−50 mA
Input Voltage
−0.3V to 3.6V
Outputs Active (Note 8)
DC Input Diode Current (IIK) VI < 0V
Output Voltage (VO)
Output in Active States
Output in 3-STATE
Output Current in IOH/IOL
0V to VCC
DC Output Diode Current (IOK
)
0.0V to 3.6V
V
V
O < 0V
−50 mA
+50 mA
O > VCC
V
V
V
V
CC = 3.0V to 3.6V
CC = 2.3V to 2.7V
CC = 1.65V to 2.3V
CC = 1.4V to 1.6V
±24 mA
±18 mA
DC Output Source/Sink Current
(IOH/IOL
)
±50 mA
±6 mA
DC VCC or Ground Current per
Supply Pin (ICC or Ground)
±2 mA
±100 mA
Free Air Operating Temperature (TA)
−40°C to +85°C
Storage Temperature Range (TSTG
)
−65°C to +150°C
Minimum Input Edge Rate (∆t/∆V)
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 7: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditions tables will define the condi-
tions for actual device operation.
Note 8: IO Absolute Maximum Rating must be observed.
Note 9: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
Conditions
Min
Max
Units
(V)
HIGH Level Input Voltage
2.7 - 3.6
2.3 - 2.7
2.0
1.6
V
1.65 - 2.3 0.65 x VCC
1.4 - 1.6
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
2.7 - 3.6
2.7
0.65 x VCC
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.8
0.7
V
0.35 - VCC
0.35 - VCC
VOH
I
I
I
I
I
I
I
I
I
I
I
I
OH = −100 µA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OH = −100 µA
OH = −6 mA
VCC - 0.2
2.2
3.0
2.4
3.0
2.2
2.3 - 2.7
2.3
VCC - 0.2
2.0
V
OH = −12 mA
OH = −18 mA
OH = −100 µA
OH = −6 mA
2.3
1.8
2.3
1.7
1.65 - 2.3
1.65
VCC - 0.2
1.25
OH = −100 µA
OH = −2 mA
1.4 - 1.6
1.4
VCC - 0.2
1.05
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4
DC Electrical Characteristics (Continued)
VCC
Symbol
VOL
Parameter
Conditions
Min
Max
Units
(V)
2.7 - 3.6
2.7
LOW Level Output Voltage
I
I
I
I
I
I
I
I
I
I
I
OL = 100 µA
OL = 12 mA
OL = 18 mA
OL = 24 mA
OL = 100 µA
OL = 12 mA
OL = 18 mA
OL = 100 µA
OL = 6 mA
0.2
0.4
3.0
0.4
3.0
0.55
0.2
2.3 - 2.7
2.3
0.4
V
2.3
0.6
1.65 - 2.3
1.65
0.2
0.3
OL = 100 µA
OL = 2 mA
1.4 - 1.6
1.4
0.2
0.35
±5.0
II
Input Leakage Current
0V ≤ VI ≤ 3.6V
2.7 - 3.6
µA
µA
µA
µA
µA
IOZ
3-STATE Output Leakage
0V ≤ VO ≤ 3.6V
VI = VIH or VIL
1.4 - 3.6
±10.0
IOFF
ICC
Power Off Leakage Current
Quiescent Supply Current
0V ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
0
10.0
20.0
1.4 - 3.6
1.4 - 3.6
2.7 - 3.6
V
V
CC ≤ (VI, VO) ≤ 3.6V (Note 10)
IH = VCC − 0.6V
±20.0
750
∆ICC
Increase in ICC per Input
Note 10: Outputs disabled or 3-STATE only.
5
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AC Electrical Characteristics (Note 11)
VCC
TA = −40°C to + 85°C
Figure
Symbol
fMAX
Parameter
Conditions
Units
(V)
Min
250
200
100
80.0
0.8
Max
Number
Maximum Clock Frequency
C
L = 30 pF
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
MHz
CL = 15 pF
C
tPHL
tPLH
Propagation Delay
Bus-to-Bus
L = 30 pF, RL = 500Ω
2.9
3.5
Figures 1,
2
1.0
ns
ns
ns
ns
ns
1.5
7.0
C
L = 15 pF, RL = 2kΩ
L = 30 pF, RL = 500Ω
1.0
14.0
Figures 7,
8
tPHL
tPLH
Propagation Delay
Clock-to-Bus
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
0.8
1.0
1.5
1.0
3.5
4.4
Figures 1,
2
8.8
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
17.6
Figures 7,
8
tPHL
tPLH
Propagation Delay
LE-to-Bus
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
0.8
1.0
1.5
1.0
3.5
4.4
Figures 1,
2
8.8
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
17.6
Figures 7,
8
tPZL
tPZH
Output Enable Time
Output Disable Time
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
0.8
1.0
1.5
1.0
3.8
4.9
Figures 1,
3, 4
9.8
C
L = 15 pF, RL = 2kΩ
L = 30 pF, RL = 500Ω
19.6
Figures 7,
9, 10
tPLZ
tPHZ
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
0.8
1.0
1.5
1.0
3.7
4.2
Figures 1,
3, 4
7.6
C
L = 15 pF, RL = 2kΩ
L = 30 pF, RL = 500Ω
15.2
Figures 7,
9, 10
tS
Setup Time
Hold Time
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
1.5
1.5
2.5
3.0
1.0
1.0
1.0
2.0
1.5
1.5
4.0
4.0
ns
ns
ns
ns
Figure 6
Figure 6
Figure 5
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
tH
C
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
tW
Pulse Width
C
C
L = 15 pF, RL = 500Ω
L = 30 pF, RL = 500Ω
tOSHL
tOSLH
Output to Output Skew
(Note 12)
C
0.5
0.5
0.75
1.5
C
L = 15 pF, RL = 2kΩ
Note 11: For CL = 50pF, add approximately 300ps to the AC maximum specification.
Note 12: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
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6
Dynamic Switching Characteristics
VCC
T
A = +25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
Typical
0.25
0.6
Quiet Output Dynamic Peak VOL
C
C
C
L = 30 pF, VIH = VCC, VIL = 0V
V
0.8
VOLV
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
L = 30 pF, VIH = VCC, VIL = 0V
L = 30 pF, VIH = VCC, VIL = 0V
−0.25
−0.6
−0.8
1.5
V
V
VOHV
1.9
2.2
Capacitance
TA = +25°C
Symbol
Parameter
Conditions
Units
CIN
Input Capacitance
VI = 0V or VCC
CC = 1.8V, 2.5V, or 3.3V
VI = 0V or VCC
CC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz
6.0
pF
V
CI/O
Output Capacitance
,
7.0
pF
pF
V
CPD
Power Dissipation Capacitance
20.0
V
CC = 1.8V, 2.5V or 3.3V
7
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AC Loading and Waveforms (V 3.3V ± 0.3V to 1.8V ± 0.15V)
CC
FIGURE 1. AC Test Circuit
TEST
SWITCH
tPLH, tPHL
tPZL, tPLZ
Open
6V at VCC = 3.3V ± 0.3V;
VCC x 2 at VCC = 2.5V ± 0.2V; 1.8V ± 0.15V
tPZH, tPHZ
GND
FIGURE 2. Waveform for Inverting and
Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
rec Waveforms
FIGURE 6. Setup Time, Hold Time and Recovery Time
for Low Voltage Logic
t
VCC
Symbol
3.3V ± 0.3V
1.5V
2.5V ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
VCC/2
VCC/2
V
OL + 0.3V
V
OL + 0.15V
V
OL + 0.15V
VY
V
OH − 0.3V
V
OH − 0.15V
VOH − 0.15V
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8
AC Loading and Waveforms (V 1.5V ± 0.1V)
CC
TEST
SWITCH
t
PLH, tPHL
Open
VCC x 2 at VCC = 1.5 ± 0.1V
GND
t
PZL, tPLZ
tPZH, tPHZ
FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and Non-inverting Functions
FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V ± 0.1V
Vmi
Vmo
VX
VCC/2
VCC/2
V
OL + 0.1V
VY
VOH − 0.1V
9
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Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
(Preliminary)
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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11
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