74VCXH162244_05 [FAIRCHILD]

Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26ohm Series Resistor in Outputs; 低电压16位缓冲器/线路与Bushold和26ohm串联电阻输出驱动器
74VCXH162244_05
型号: 74VCXH162244_05
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Low Voltage 16-Bit Buffer/Line Driver with Bushold and 26ohm Series Resistor in Outputs
低电压16位缓冲器/线路与Bushold和26ohm串联电阻输出驱动器

驱动器
文件: 总8页 (文件大小:139K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
January 2000  
Revised June 2005  
74VCXH162244  
Low Voltage 16-Bit Buffer/Line Driver with Bushold  
and 26: Series Resistor in Outputs  
General Description  
Features  
1.4V to 3.6V VCC supply operation  
The VCXH162244 contains sixteen non-inverting buffers  
with 3-STATE outputs to be employed as a memory and  
address driver, clock driver, or bus oriented transmitter/  
receiver. The device is nibble (4-bit) controlled. Each nibble  
has separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
3.6V tolerant control inputs and outputs  
Bushold on data inputs eliminates the need for external  
pull-up/pull-down resistors  
26 series resistors in outputs  
tPD  
The VCXH162244 data inputs include active bushold cir-  
cuitry, eliminating the need for external pull-up resistors to  
hold unused or floating data inputs at a valid logic level  
3.3 ns max for 3.0V to 3.6V VCC  
Static Drive (IOH/IOL  
)
The 74VCXH162244 is also designed with 26 series  
resistors in the outputs. This design reduces line noise in  
applications such as memory address drivers, clock driv-  
ers, and bus transceivers/transmitters.  
12 mA @ 3.0V VCC  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 300 mA  
ESD performance:  
The 74VCXH162244 is designed for low voltage (1.4V to  
3.6V) VCC applications with output capability up to 3.6V.  
Human body model 2000V  
The 74VCXH162244 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Machine model 200V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74VCXH162244MTD  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
[TUBES]  
MTD48  
MTD48  
74VCXH162244MTX  
(Note 1)  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
[TAPE and REEL]  
Note 1: Use this Order Number to receive devices in Tape and Reel.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Input (Active LOW)  
Bushold Inputs  
I0–I15  
O0–O15  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
DS500231  
www.fairchildsemi.com  
Connection Diagram  
Truth Tables  
Inputs  
Outputs  
OE1  
L
I0–I3  
L
O0–O3  
L
H
Z
L
H
H
X
Inputs  
OE2  
Outputs  
O4–O7  
I4–I7  
L
L
L
H
X
L
H
Z
H
Inputs  
OE3  
Outputs  
O8–O11  
I8–I11  
L
L
L
H
X
L
H
Z
H
Inputs  
OE4  
Outputs  
O12–O15  
I12–I15  
L
L
L
H
X
L
H
Z
H
H
L
HIGH Voltage Level  
LOW Voltage Level  
X
Z
Immaterial (HIGH or LOW, inputs may not float)  
High Impedance  
Functional Description  
The 74VCXH162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4 bits) controlled  
with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain  
full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable (OEn) input. When OEn is LOW, the outputs  
are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not inter-  
fere with entering new data into the inputs.  
Logic Diagram  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 2)  
Recommended Operating  
Conditions (Note 4)  
Supply Voltage (VCC  
)
0.5V to 4.6V  
DC Input Voltage (VI)  
OEn  
Power Supply  
0.5V to 4.6V  
Operating  
1.4V to 3.6V  
1.2V to 3.6V  
0.3V to VCC  
I0 I15  
0.5V to VCC 0.5V  
Data Retention Only  
Input Voltage  
Output Voltage (VO)  
Outputs 3-STATE  
Outputs Active (Note 3)  
DC Input Diode Current (IIK  
VI 0V  
0.5V to 4.6V  
Output Voltage (VO)  
Output in Active States  
Output in 3-STATE  
0.5V to VCC 0.5V  
0V to VCC  
)
0.0V to 3.6V  
50 mA  
Output Current in IOH/IOL  
VCC 3.0V to 3.6V  
DC Output Diode Current (IOK  
VO 0V  
)
12 mA  
8 mA  
50 mA  
50 mA  
VCC 2.3V to 2.7V  
VO VCC  
VCC 1.65V to 2.3V  
VCC 1.4V to 1.6V  
3 mA  
DC Output Source/Sink Current  
(IOH/IOL  
2 mA  
)
50 mA  
Free Air Operating Temperature (TA)  
Minimum Input Edge Rate ( t/ V)  
VIN 0.8V to 2.0V, VCC 3.0V  
40 C to 85 C  
DC VCC or GND Current per  
Supply Pin (ICC or GND)  
100 mA  
10 ns/V  
Note 2: The Absolute Maximum Ratings are those values beyond which  
the safety of the device cannot be guaranteed. The device should not be  
operated at these limits. The parametric values defined in the Electrical  
Characteristics tables are not guaranteed at the Absolute Maximum Rat-  
ings. The Recommended Operating Conditionstable will define the condi-  
tions for actual device operation.  
Storage Temperature Range (TSTG  
)
65 C to 150 C  
Note 3: I Absolute Maximum Rating must be observed.  
O
Note 4: Floating or unused control inputs must be held HIGH or LOW.  
DC Electrical Characteristics  
V
CC  
Symbol  
Parameter  
HIGH Level Input Voltage  
Conditions  
Min  
Max  
Units  
(V)  
V
V
V
2.7 - 3.6  
2.3 - 2.7  
2.0  
1.6  
IH  
V
1.65 - 2.3 0.65  
V
V
CC  
1.4 - 1.6  
2.7 - 3.6  
2.3 - 2.7  
1.65 - 2.3  
1.4 - 1.6  
2.7 - 3.6  
2.7  
0.65  
CC  
LOW Level Input Voltage  
HIGH Level Output Voltage  
0.8  
0.7  
IL  
V
0.35  
0.35  
V
V
CC  
CC  
I
I
I
I
I
I
I
I
I
I
I
I
100  
A
V
- 0.2  
CC  
OH  
OH  
OH  
OH  
OH  
OH  
OH  
OH  
OH  
OH  
OH  
OH  
OH  
6 mA  
8 mA  
2.2  
3.0  
2.4  
2.2  
12 mA  
3.0  
100  
A
2.3 - 2.7  
2.3  
V
- 0.2  
CC  
4 mA  
6 mA  
8 mA  
100  
2.0  
1.8  
1.7  
V
2.3  
2.3  
A
A
1.65 - 2.3  
1.65  
V
- 0.2  
CC  
3 mA  
100  
1.25  
- 0.2  
1.4 - 1.6  
1.4  
V
CC  
1 mA  
1.05  
3
www.fairchildsemi.com  
DC Electrical Characteristics (Continued)  
V
CC  
Symbol  
Parameter  
Conditions  
Min  
Max  
Units  
(V)  
2.7 - 3.6  
2.7  
V
LOW Level Output Voltage  
I
100  
A
0.2  
0.4  
0.55  
0.8  
0.2  
0.4  
0.6  
0.2  
0.3  
0.2  
0.35  
5.0  
5.0  
OL  
OL  
I
6 mA  
8 mA  
12 mA  
OL  
I
3.0  
OL  
I
3.0  
OL  
I
100  
A
2.3 - 2.7  
2.3  
OL  
I
6 mA  
8 mA  
100  
V
OL  
I
2.3  
OL  
I
A
A
1.65 - 2.3  
1.65  
1.4 - 1.6  
1.4  
OL  
I
3 mA  
100  
OL  
I
OL  
I
1 mA  
OL  
I
Input Leakage Current  
Control Pins  
Data Pins  
0
V
3.6V  
V or GND  
CC  
1.4 - 3.6  
1.4 - 3.6  
3.0  
I
I
A
A
V
V
V
V
V
V
V
I
I
Bushold Input Minimum  
Drive Hold Current  
0.8V  
2.0V  
0.7V  
1.6V  
0.57V  
1.07V  
75  
75  
I(HOLD)  
IN  
IN  
IN  
IN  
IN  
IN  
3.0  
2.3  
45  
2.3  
45  
1.65  
1.65  
3.6  
25  
25  
I
Bushold Input Over-Drive  
Current to Change State  
(Note 5)  
(Note 6)  
(Note 5)  
(Note 6)  
(Note 5)  
(Note 6)  
450  
450  
300  
300  
200  
200  
I(OD)  
3.6  
2.7  
A
A
2.7  
1.95  
1.95  
I
3-STATE Output Leakage  
0
V
3.6V  
or V  
OZ  
O
2.7 - 3.6  
10.0  
V
V
IH  
I
IL  
I
Power-OFF Leakage Current  
Quiescent Supply Current  
0
(V  
V
)
3.6V  
0
10.0  
20.0  
20.0  
750  
A
A
A
A
OFF  
O
I
V
V
V
or GND  
2.7 - 3.6  
2.7 - 3.6  
2.7 - 3.6  
CC  
I
CC  
(V  
)
O
3.6V (Note 7)  
0.6V  
CC  
IH  
I
Increase in I per Input  
V
CC  
CC  
CC  
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.  
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.  
Note 7: Outputs disabled or 3-STATE only.  
www.fairchildsemi.com  
4
AC Electrical Characteristics (Note 8)  
V
T
40 C to 85 C  
Figure  
CC  
A
Symbol  
Parameter  
Propagation Delay  
Conditions  
Units  
(V)  
Min  
Max  
3.3  
Number  
t
t
C
30 pF, R  
500  
3.3 0.3  
2.5 0.2  
1.8 0.15  
1.5 0.1  
0.8  
1.0  
1.5  
1.0  
PHL  
PLH  
L
L
Figures  
1, 2  
3.8  
ns  
7.6  
C
C
30 pF, R  
30 pF, R  
500  
500  
15.2  
Figures  
5, 6  
L
L
t
t
Output Enable Time  
Output Disable Time  
3.3 0.3  
2.5 0.2  
1.8 0.15  
1.5 0.1  
0.8  
1.0  
1.5  
1.0  
3.8  
5.1  
PZL  
PZH  
L
L
Figures  
1, 3, 4  
ns  
9.8  
C
C
30 pF, R  
30 pF, R  
500  
500  
19.6  
Figures  
5, 7, 8  
L
L
t
t
3.3 0.3  
2.5 0.2  
1.8 0.15  
1.5 0.1  
0.8  
1.0  
1.5  
1.0  
3.6  
4.0  
PLZ  
PHZ  
L
L
Figures  
1, 3, 4  
ns  
ns  
7.2  
14.4  
Figures  
5, 7, 8  
t
t
Output-to-Output Skew  
(Note 9)  
C
C
30 pF, R  
30 pF, R  
500  
500  
3.3 0.3  
2.5 0.2  
1.8 0.15  
1.5 0.1  
0.5  
0.5  
OSHL  
OSLH  
L
L
0.75  
1.5  
L
L
Note 8: For C  
50 F, add approximately 300 ps to the AC maximum specification.  
P
L
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The  
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t  
) or LOW-to-HIGH (t  
).  
OSLH  
OSHL  
Dynamic Switching Characteristics  
V
T
25 C  
Typical  
CC  
A
Symbol  
Parameter  
Conditions  
Units  
(V)  
1.8  
2.5  
3.3  
1.8  
2.5  
3.3  
1.8  
2.5  
3.3  
V
V
V
Quiet Output Dynamic Peak V  
C
C
C
30 pF, V  
30 pF, V  
30 pF, V  
V
V
V
, V  
, V  
, V  
0V  
0V  
0V  
0.15  
0.25  
0.35  
0.15  
0.25  
0.35  
1.55  
2.05  
2.65  
OLP  
OL  
L
L
L
IH  
IH  
IH  
CC  
CC  
CC  
IL  
IL  
IL  
V
Quiet Output Dynamic Valley V  
Quiet Output Dynamic Valley V  
OLV  
OL  
V
V
OHV  
OH  
Capacitance  
T
25 C  
A
Symbol  
Parameter  
Conditions  
1.8, 2.5V or 3.3V, V 0V or V  
CC  
Units  
Typical  
6.0  
C
Input Capacitance  
Output Capacitance  
Power Dissipation Capacitance  
V
pF  
pF  
pF  
IN  
CC  
I
C
C
V
V
0V or V , V  
CC  
1.8V, 2.5V or 3.3V  
7.0  
OUT  
PD  
I
I
CC  
0V or V , f 10 MHz, V  
CC  
1.8V, 2.5V or 3.3V  
20.0  
CC  
5
www.fairchildsemi.com  
AC Loading and Waveforms (V 3.3V r 0.3V to 1.8V r 0.15V)  
CC  
TEST  
SWITCH  
tPLH, tPHL  
Open  
tPZL, tPLZ  
6V at VCC 3.3 0.3V;  
VCC x 2 at VCC 2.5 0.2V; 1.8 0.15V  
tPZH, tPHZ  
GND  
FIGURE 1. AC Test Circuit  
FIGURE 2. Waveform for Inverting and Non-Inverting Functions  
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic  
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic  
VCC  
Symbol  
3.3V 0.3V  
1.5V  
2.5V 0.2V  
VCC/2  
1.8V 0.15V  
VCC/2  
Vmi  
Vmo  
VX  
1.5V  
VCC/2  
VCC/2  
VOL 0.3V  
VOH 0.3V  
VOL 0.15V  
VOH 0.15V  
VOL 0.15V  
VOH 0.15V  
VY  
www.fairchildsemi.com  
6
AC Loading and Waveforms (V 1.5V r 0.1V)  
CC  
TEST  
SWITCH  
tPLH, tPHL  
Open  
VCC x 2 at VCC 1.5V 0.1V  
GND  
t
PZL, tPLZ  
tPZH, tPHZ  
FIGURE 5. AC Test Circuit  
FIGURE 6. Waveform for Inverting and Non-Inverting Functions  
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic  
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic  
VCC  
Symbol  
1.5V 0.1V  
Vmi  
Vmo  
VX  
VCC/2  
VCC/2  
VOL 0.1V  
VOH 0.1V  
VY  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Package Number MTD48  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
8

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