FAN3278TMX_技术文档

January 2011

FAN3278

30V PMOS-NMOS Bridge Driver

Description

Features

The FAN3278 dual 1.5A gate driver is optimized to drive

.

8V to 27V Optimum Operating Range

a

high-side P-channel MOSFET and a low-side

Drives High-Side PMOS and Low-Side NMOS in

Motor Control or Buck Step-Down Applications

N-channel MOSFET in motor control applications

operating from a voltage rail up to 27V. Internal circuitry

limits the voltage applied to the gates of the external

MOSFETs to 13V maximum. The driver has TTL input

thresholds and provides buffer and level translation from

logic inputs. Internal circuitry prevents the output

switching devices from operating if the V_DDsupply

voltage is below the IC operation level. Internal 100kΩ

resistors bias the non-inverting output LOW and the

inverting output to V_DDto keep the external MOSFETs

off during startup intervals when logic control signals

may not be present.

.

Output Drive-Voltage Magnitude Limited: < 13V

for V_DDup to 30V

Biases Each Load Device OFF with a 100kΩ

Resistor when V_DDBelow Operating Level

.

Low-Voltage TTL Input Thresholds

Peak Gate Drives at 12V: +1.5A Sink, -1.0A Source

Internal Resistors Hold Driver Off When

No Inputs Present

.

8-Lead SOIC Package

The FAN3278 driver incorporates MOSFET devices for

the final output stage, providing high current throughout

the MOSFET turn-on / turn-off transition to minimize

switching loss. The internal gate-drive regulators

provide optimum gate-drive voltage when operating

from a rail of 8V to 27V. The FAN3278 can be driven

from a voltage rail of less than 8V; however, its gate

drive current is reduced.

Rated from –40°C to +125°C Ambient

Applications

.

Motor Control with PMOS / NMOS Half-Bridge

Configuration

Buck Converters with High-Side PMOS Device;

100% Duty Cycle Operation Possible

The FAN3278 has two independent ENABLE pins that

default to ON if not connected. If the ENABLE pin for

non-inverting channel A is pulled LOW, OUTA is forced

LOW. If the ENABLE pin for inverting channel B is

pulled LOW, OUTB is forced HIGH. If an input is left

unconnected, internal resistors bias the inputs such that

the external MOSFETs are OFF.

Logic-Controlled Load Circuits with High-Side

PMOS Switch

Figure 1. Typical Application

FAN3278 • Rev. 1.0.0

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Ordering Information

Input

Threshold

Packing

Method

Part Number

Logic

2,500 Units on

Tape & Reel

FAN3278TMX

Non-Inverting Channel and Inverting Channel with Dual Enable

TTL

Figure 2. Typical 3-Phase Blower Motor Drive Application

FAN3278 • Rev. 1.0.0

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2

Pin Configuration

Figure 3. Pin Configuration (Top View)

Thermal Characteristics⁽¹⁾

Package

(2)

(3)

(4)

(5)

(6)

Unit

_JL

_JT

_JA

_JB

_JT

40

31

89

43

3

°C/W

8-Pin Small-Outline Integrated Circuit (SOIC)

Notes:

1. Estimates derived from thermal simulation; actual values depend on the application.

2. Theta_JL (_JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads

(including any thermal pad) that are typically soldered to a PCB.

3. Theta_JT (_JT): Thermal resistance between the semiconductor junction and the top surface of the package,

assuming it is held at a uniform temperature by a top-side heatsink.

4. Theta_JA (Θ_JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,

and airflow. The value given is for natural convection with no heatsink using a 2S2P board, as specified in

JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.

5. Psi_JB (_JB): Thermal characterization parameter providing correlation between semiconductor junction

temperature and an application circuit board reference point for the thermal environment defined in Note 4. For

the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.

6. Psi_JT (_JT): Thermal characterization parameter providing correlation between the semiconductor junction

temperature and the center of the top of the package for the thermal environment defined in Note 4.

Pin Definitions

Pin# Name

Description

1

8

3

2

4

7

ENA Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds.

ENB Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds.

GND Ground. Common ground reference for input and output circuits.

INA

INB

Input to Channel A.

Input to Channel B.

Gate Drive Output A: Held LOW unless required input is present and V_DDis above the internal

voltage threshold where the IC is functional.

OUTA

Gate Drive Output B (inverted from the input). Held HIGH unless the required input is present

and V_DDis above the internal voltage threshold where the IC is functional.

5

6

OUTB

VDD Supply Voltage. Provides power to the IC.

FAN3278 • Rev. 1.0.0

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Output Logic

FAN3278 (Channel A)

FAN3278 (Channel B)

ENA

INA

OUTA

ENB

INB

OUTB

0

0⁽⁷⁾

0

1

0

0⁽⁷⁾

1

0

1

0

1

1⁽⁷⁾

0⁽⁷⁾

1

1⁽⁷⁾

0⁽⁷⁾

1

Note:

7. Default input signal if no external connection is made.

Block Diagram

V_DD

100k

1

2

8

7

ENB

ENA

INA

13V

OUTA

LS

Predriver

100k

Low-Side

Drive

Regulator

6

VDD

3

GND

High-Side

Drive

Regulator

100k

HS

5

Predriver

OUTB

INB

4

100k

V_DD- 13V

Figure 4. Block Diagram

FAN3278 • Rev. 1.0.0

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Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol

V_DD

Parameter

Min.

Max.

Unit

V

VDD to PGND

-0.3

30.0

V_EN

ENA, ENB to GND

INA, INB to GND

OUTA, OUTB to GND

GND - 0.3 V_DD+ 0.3

+260

V

V_IN

V

V_OUT

T_L

V

Lead Soldering Temperature (10 Seconds)

Junction Temperature

ºC

T_J

-55

-65

2

+150

T_STG

Storage Temperature

Human Body Model, JEDEC JESD22-A114

Charged Device Model, JEDEC JESD22-C101

Electrostatic Discharge

Protection Level

ESD

kV

2

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol

V_DD

Parameter

Min.

8

Max.

27

Unit

V

Supply Voltage Range

V_EN

Enable Voltage (ENA, ENB)

Input Voltage (INA, INB)

0

V_DD

V

V_IN

0

V_DD

V

T_A

Operating Ambient Temperature

-40

+125

°C

FAN3278 • Rev. 1.0.0

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Electrical Characteristics

Unless otherwise noted, V_DD=12V and T_J=-40°C to +125°C. Currents are defined as positive into the device (I_sink) and

negative out of the device (I_source).

Symbol

Supply

V_DD

Parameter

Conditions

Min.

Typ. Max. Unit

Optimum Operating Range⁽⁸⁾

8

27

V

Supply Current Inputs / EN Not

Connected

I_DD

1.3

2.0

mA

V_ON

V_HYS

Input⁽⁹⁾

V_IL

Turn-On Voltage⁽⁹⁾

INA=ENA=V_DD, INB=ENB=0V

3.8

10

V

Turn-On / Turn-Off Hysteresis ⁽⁹⁾

mV

INx Logic Low Threshold

INx Logic High Threshold

Logic Hysteresis Voltage

0.8

0.4

0.8

1.1

1.80

0.7

V

V_IH

2.25

1.0

V_HYS

Enable

V_ENL

V_ENH

V_HYS

R_PU

Enable Logic Low Threshold

EN from 5V to 0V

EN from 0V to 5V

1.2

1.60

0.7

100

44

V

Enable Logic High Threshold

Logic Hysteresis Voltage⁽¹⁰⁾

2.25

V

Enable Pull-Up Resistance

kΩ

ns

t_D1

Propagation A Delay, EN Rising⁽¹¹⁾

Propagation A Delay, EN Falling⁽¹¹⁾

Propagation B Delay, EN Rising⁽¹¹⁾

Propagation B Delay, EN Falling⁽¹¹⁾

0 - 5V_IN, 1V/ns Slew Rate

0 – 5V_IN, 1V/ns Slew Rate

0 - 5V_IN, 1V/ns Slew Rate

0 – 5V_IN, 1V/ns Slew Rate

70

60

70

60

t_D2

33

t_D2

39

t_D1

29

Continued on the following page…

Timing Diagrams

90%

Output

10%

Input

or

Enable

V_INH

V_INL

t_D1

t_D2

t_FALL

t_RISE

Figure 5. Non-Inverting

Figure 6. Inverting

FAN3278 • Rev. 1.0.0

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Electrical Characteristics (Continued)

Unless otherwise noted, V_DD=12V and T_J=-40°C to +125°C. Currents are defined as positive into the device (I_sink) and

negative out of the device (I_source).

Symbol

Output

Parameter

Conditions

Min. Typ. Max. Unit

I_{PK_OFF}OUT Current, Peak, Turn-Off⁽¹⁰⁾

C_LOAD=0.1µF, f=1kHz

1.5

A

I_{PK_ON}

I_OFF

OUT Current, Peak, Turn-On⁽¹⁰⁾

-1.0

OUT at V_DD, C_LOAD=0.1µF,

f=1kHz

OUT Current, Mid-Voltage, Turn-Off⁽¹⁰

1.0

A

OUT at V_DD/2, C_LOAD=0.1µF,

f=1kHz

I_ON

OUT Current, Mid-Voltage, Turn-On⁽¹⁰⁾

-0.5

V_OUTA

V_OUTB

V_OUTA

V_OUTB

OUTA Drive Voltage

V_DD=27V, INA=“HI”

V_DD=10V, INB=“HI”

V_DD=6V, C_LOAD=0.1µF

11

13

V

OUTB Drive Voltage, V_DD– V_OUTB

OUTA Drive Voltage

6.5

7.0

4.2

10.3

6.8

13.7

17

V

OUTB Drive Voltage, V_DD– V_OUTB

V

R_{O_A_SINK}OUTA Sink Impedance (Turn-Off)⁽¹⁰⁾

Ω

R_{O_A_SRC}OUTA Source Impedance (Turn-On)⁽¹⁰⁾V_DD=6V, C_LOAD=0.1µF

R_{O_B_SINK}OUTB Sink Impedance (Turn-On)⁽¹⁰⁾

V_DD=6V, C_LOAD=0.1µF

R_{O_B_SRC}OUTB Source Impedance (Turn-Off)⁽¹⁰⁾V_DD=6V, C_LOAD=0.1µF

Ω

t_ON,N

t_OFF,N

t_ON,P

t_OFF,P

t_D1

Output A Rise Time⁽¹¹⁾

C_LOAD=1000pF to GND

C_LOAD=1000pF to V_DD

0 - 5V_IN, 1V/ns Slew Rate

30

15

30

15

70

60

ns

mA

Output A Fall Time⁽¹¹⁾

Output B Fall Time⁽¹¹⁾

8

21

Output B Rise Time⁽¹¹⁾

8

Output Propagation Delay On⁽¹¹⁾

Output Propagation Delay Off⁽¹¹⁾

Output Reverse Current Withstand⁽¹⁰⁾

45

t_D2

35

I_RVS

500

Notes:

8. The internal gate-drive regulators provide optimum gate-drive voltage when operating from a rail of 8V to 27V.

The FAN3278 can be driven from a voltage rail of less than 8V; however, with reduced gate drive current.

9. EN inputs have near-TTL thresholds (refer to the ENABLE section).

10. Not tested in production.

11. See the Timing Diagrams of Figure 5 and Figure 6.

FAN3278 • Rev. 1.0.0

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Typical Performance Characteristics

Typical characteristics are provided at T_A=25°C and V_DD=12V unless otherwise noted.

Figure 7. I_DD(Static) vs. Supply Voltage⁽¹²⁾

Figure 8. I_DD(Static) vs. Temperature⁽¹²⁾

Figure 10. I_DD(1nF Load) vs. Frequency

Figure 9. I_DD(No Load) vs. Frequency

Figure 11. Input Thresholds vs. Temperature

FAN3278 • Rev. 1.0.0

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Typical Performance Characteristics

Typical characteristics are provided at T_A=25°C and V_DD=12V unless otherwise noted.

Figure 12. Propagation Delays vs. Temperature

Figure 13. Propagation Delays vs. Temperature

Figure 14. Rise and Fall Times vs. Temperature

Figure 15. Rise and Fall Times vs. Temperature

Figure 16. Gate Drive Voltage vs. Temperature

Figure 17. Gate Drive Voltage vs. Temperature

Note:

12. For any inverting inputs pulled LOW, non-inverting inputs pulled HIGH, or outputs driven HIGH; static I_DD

increases by the current flowing through the corresponding pull-up/down resistor, shown in Figure 4.

FAN3278 • Rev. 1.0.0

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Applications Information

Input Thresholds

The FAN3278 driver has TTL input thresholds and

provides buffer and level translation functions from

logic inputs. The input thresholds meet industry-

standard TTL-logic thresholds, independent of the V_DD

voltage, and there is

a

hysteresis voltage of

approximately 0.4V. These levels permit the inputs to

be driven from a range of input logic signal levels for

which a voltage over 2V is considered logic HIGH. The

driving signal for the TTL inputs should have fast rising

and falling edges with a slew rate of 6V/µs or faster, so

a rise time from 0 to 3.3V should be 550ns or less.

With reduced slew rate, circuit noise could cause the

driver input voltage to exceed the hysteresis voltage

and retrigger the driver input inadvertently.

Figure 18. Non-Inverting Startup Waveforms

Static Supply Current

In the I_DD(static) typical performance characteristics

(see Figure 7 and Figure 8), the curve is produced with

all inputs / enables floating (OUTA is LOW, OUTB is

HIGH) and indicates the lowest static I_DDcurrent for the

tested configuration. For other states, additional current

flows through the 100k resistors on the inputs and

outputs, shown in the block diagram (see Figure 4). In

these cases, the static I_DDcurrent is the value obtained

from the curves plus this additional current.

Figure 19 illustrates startup waveforms for inverting

channel B. At power-up, the driver output for channel B

is tied to V_DDthrough an internal 100kΩ resistor until

V_DDreaches the voltage where the device starts

operating, then OUTB operates out of phase with INB.

Gate Drive Regulator

FAN3278 incorporates internal regulators to regulate the

gate drive voltage. The output pin slew rate is

determined by this gate drive voltage and the load on

the output. It is not user adjustable, but a series resistor

can be added if a slower rise or fall time is needed at

the MOSFET gate.

Startup Operation

The FAN3278 startup logic is optimized to drive a ground-

referenced N-channel MOSFET with channel A and a

V_DD-referenced P-channel MOSFET with channel B.

The optimum operating voltage of the FAN3278 is 8V to

27V. It has an internal “watchdog” circuit that provides a

loose UVLO turn-on voltage (V_ON) of approximately 3.8V

with a small hysteresis of about 10mV. However, it is

recommended that V_DDis greater than 4.75V in all

application circuits.

Figure 19. Inverting Startup Waveforms

It is possible, during startup, before V_DDhas reached

approximately 4.5V, that the output pulse width may

take a few switching cycles to reach the full duty-cycle

of the input pulse. This is due to internal propagation

delays affecting the operation with higher switching

frequency (e.g. >100kHz) and slow V_DDramp-up (e.g.

<20V/ms). For this reason, it is recommended that V_DD

should be greater than 4.75V before any INA or INB

signals are present.

When the V_DDsupply voltage is below the level needed

to operate the internal circuitry, the outputs are biased

to hold the external MOSFETs in OFF state. Internal

100kΩ resistors bias the non-inverting output LOW and

the inverting output to V_DDto keep the external

MOSFETs off during startup intervals when input control

signals may not be present.

For high-frequency applications (several hundred kHz

up to 1MHz), where the above recommendation of V_DD

> 4.75V is not possible, the use of ENABLES to

actively hold the outputs LOW until V_DD> 4.75V

assures the driver output pulse width follows the input

from 4.75V up to 28V.

Figure 18 shows startup waveforms for non-inverting

channel A. At power-up, the driver output for channel A

remains LOW until V_DDreaches the voltage where the

device starts operating, then OUTA operates in-phase

with INA.

FAN3278 • Rev. 1.0.0

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best results, make connections to all pins as short

and direct as possible.

V_DDBypass Capacitor Guidelines

To enable this IC to turn a device on quickly, a local

high-frequency bypass capacitor, C_BYP, with low ESR

and ESL should be connected between the VDD and

GND pins with minimal trace length. This capacitor is in

addition to bulk electrolytic capacitance of 10µF to 47µF

commonly found on driver and controller bias circuits.

.

The turn-on and turn-off current paths should be

minimized, as discussed above.

Thermal Guidelines

Gate drivers used to switch MOSFETs and IGBTs at

high frequencies can dissipate significant amounts of

power. It is important to determine the driver power

dissipation and the resulting junction temperature in the

application to ensure the part is operating within

acceptable temperature limits.

A typical criterion for choosing the value of C_BYPis to

keep the ripple voltage on the V_DDsupply to ≤5%. This

is often achieved with a value ≥20 times the equivalent

load capacitance C_EQV, defined as Q_GATE/V_DD. Ceramic

capacitors of 0.1µF to 1µF or larger are common

choices, as are dielectrics, such as X5R and X7R, with

stable temperature characteristics and high pulse

current capability.

The total power dissipation in a gate driver is the sum of

two components, P_GATEand P_DYNAMIC

:

P_TOTAL=P_GATE+ P_DYNAMIC

(1)

If circuit noise affects normal operation, the value of

C_BYPmay be increased to 50-100 times the C_EQVor C_BYP

may be split into two capacitors. One should be a larger

value, based on equivalent load capacitance, and the

other a smaller value, such as 1-10nF, mounted closest

to the VDD and GND pins to carry the higher-frequency

components of the current pulses. The bypass capacitor

must provide the pulsed current from both of the driver

channels and, if the drivers are switching

simultaneously, the combined peak current sourced

from the C_BYPcan be twice as large as when a single

channel is switching.

Gate Driving Loss: The most significant power loss

results from supplying gate current (charge per unit

time) to switch the load MOSFET on and off at the

switching frequency. The power dissipation that results

from driving a MOSFET with a specified gate-source

voltage, V_GS, with gate charge, Q_G, at switching

frequency, f_SW, is determined by:

P_GATE=Q_G• V_GS• f_SW

(2)

This needs to be calculated for each P-channel and N-

channel MOSFET where the Q_Gis likely to be different.

Dynamic Pre-drive / Shoot-through Current: Power loss

resulting from internal current consumption under

dynamic operating conditions, including pin pull-up /

pull-down resistors, can be obtained using the “I_DD(No-

Load) vs. Frequency” graphs in Figure 9 to determine

the current I_DYNAMICdrawn from V_DDunder actual

operating conditions.

Layout and Connection Guidelines

The FAN3278 gate driver incorporates fast-reacting

input circuits, short propagation delays, and powerful

output stages capable of delivering current peaks over

1.5A to facilitate fast voltage transition times. The

following layout and connection guidelines are strongly

recommended:

P_DYNAMIC=I_DYNAMIC• V_DD

(3)

.

Keep high-current output and power ground paths

separate from logic and enable input signals and

signal ground paths. This is especially critical when

dealing with TTL-level logic thresholds at driver

inputs and enable pins.

Once the power dissipated in the driver is determined,

the driver junction rise with respect to circuit board can

be evaluated using the following thermal equation,

_JB

assuming

was determined for a similar thermal

design (heat sinking and air flow):

.

Keep the driver as close to the load as possible to

minimize the length of high-current traces. This

reduces the series inductance to improve high-

speed switching, while minimizing the loop area

that can couple EMI to the driver inputs and

surrounding circuitry.



T_J=P_TOTAL

where:

•

_JB+ T_B

(4)

T_J=driver junction temperature

_JB

=(psi) thermal characterization parameter relating

temperature rise to total power dissipation

.

If the inputs to a channel are not externally

connected, the internal 100k resistors indicated

on block diagrams command a low output on

channel A and a high output on channel B. In noisy

environments, it may be necessary to tie inputs of

an unused channel to VDD or GND using short

traces to prevent noise from causing spurious

output switching.

T_B=board temperature in location defined in

Note 1 under Thermal Resistance table.

As an example of a power dissipation calculation,

consider an application driving two MOSFETs (one P-

channel and one N-channel, both with a gate charge of

60nC each) with V_GS=V_DD=12V. At

a

switching

frequency of 200kHz, the total power dissipation is:

P_GATE=60nC • 12V • 200kHz • 2=0.288W

P_DYNAMIC=1.65mA • 12V =0.020W

P_TOTAL=0.308W

(5)

(6)

(7)

Many high-speed power circuits can be susceptible

to noise injected from their own output or other

external sources, possibly causing output mis-

triggering. These effects can be obvious if the

circuit is tested in breadboard or non-optimal circuit

layouts with long input, enable, or output leads. For

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11

The SOIC-8 package has a junction-to-board thermal

Test Circuit



characterization parameter of _JB=43°C/W. In a system

application, the localized temperature around the device

is a function of the layout and construction of the PCB

along with airflow across the surfaces. To ensure

reliable operation, the maximum junction temperature of

the device must not exceed the absolute maximum

rating of 150°C; with 80% derating, T_Jwould be limited

to 120°C. Rearranging Equation 4 determines the board

temperature required to maintain the junction

temperature below 120°C:



T_B=T_J- P_TOTAL

•

(8)

(9)

JB

T_B=120°C – 0.308W • 43°C/W=107°C

Figure 20. Quasi-Static I_OUT/ V_OUTTest Circuit

Differences between FAN3278 and FAN3268

FAN3278 and FAN3268 are pin-compatible to each other and are designed to drive one P-Channel and one

N-channel MOSFET in applications such as battery-powered compact fan / pump DC motor drives. However, there

are key differences, highlighted in Table 1.

Table 1. Differences between FAN3278 and FAN3268

FAN3278

FAN3268

27V Operating Maximum

30V Absolute Maximum

18V Operating Maximum

20V Absolute Maximum

Supply Voltage

Yes, since the maximum operating V_DDcan No gate drive regulator is needed. The

be as high as 27V, the gate voltage to the gate drive voltage is V_DDand the

external MOSFETs is limited to about 13V. FAN3268 switches rail-to-rail.

Gate Drive Regulator

The optimum operating range is 8V to 27V.

After the IC turns on at about 3.8V, the

output tracks V_DDup to the regulated

voltage rail of about 11~13V. Below 8V of

4.1V is the UVLO turn-off voltage

which is the minimum operating

V_DD, the FAN3278 operates, but (a) slower voltage.

and (b) with limited gate drive voltage until

it reaches around 8V.

Minimum Operating

Voltage

The IC starts operating approximately at

3.8V which acts as a loose UVLO

Has the tight UVLO threshold of 4.5V

on / 4.1V off. Incorporates “smart

threshold. It incorporates a “smart startup” startup” (outputs held OFF before IC is

Startup

feature where the outputs are held OFF

before the IC starts operating.

fully operational at the UVLO

threshold).

Compound MillerDrive™ architecture

in the final output stage to provide a

more efficient gate drive current during

the Miller plateau stage of the turn-

on/turn-off switching transition.

Output Gate Drive

Architecture

Standard MOS-based output structure with

gate drive clamp.

OUTB Gate Drive

Current Strength

Optimized for P-channel: The turn-OFF

(1.5 A) is stronger than turn-ON (1.0A).

P-channel turn-ON (2.4A) is stronger

than turn-OFF (1.6A).

FAN3278 • Rev. 1.0.0

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Table 2. Related Products

Gate

Part

Input

Threshold

Type

Drive⁽¹³⁾

Logic

Package

Number

(Sink / Src)

FAN3111C Single 1A +1.1A / -0.9A

FAN3111E Single 1A +1.1A / -0.9A

FAN3100C Single 2A +2.5A / -1.8A

FAN3100T Single 2A +2.5A / -1.8A

CMOS

External⁽¹⁴⁾

CMOS

TTL

Single Channel of Dual-Input/Single-Output

SOT23-5, MLP6

Single Non-Inverting Channel with External Reference SOT23-5, MLP6

Single Channel of Two-Input/One-Output

SOT23-5, MLP6

SOIC8, MLP8

Single Channel of Two-Input/One-Output

FAN3226C Dual 2A

FAN3226T Dual 2A

FAN3227C Dual 2A

FAN3227T Dual 2A

FAN3228C Dual 2A

FAN3228T Dual 2A

FAN3229C Dual 2A

FAN3229T Dual 2A

+2.4A / -1.6A

CMOS

TTL

Dual Inverting Channels + Dual Enable

CMOS

TTL

Dual Non-Inverting Channels + Dual Enable

Dual Channels of Two-Input/One-Output, Pin Config.1

Dual Channels of Two-Input/One-Output, Pin Config.2

CMOS

TTL

CMOS

TTL

Non-Inverting Channel (NMOS) and Inverting Channel

(PMOS) + Dual Enables

FAN3268T Dual 2A

+2.4A / -1.6A

TTL

SOIC8

30V Non-Inverting (NMOS) and Inverting (PMOS) +

Dual Enable

FAN3278T Dual 2A

+1.4A / -1.0A

TTL

SOIC8

FAN3223C Dual 4A

FAN3223T Dual 4A

FAN3224C Dual 4A

FAN3224T Dual 4A

FAN3225C Dual 4A

FAN3225T Dual 4A

+4.3A / -2.8A

CMOS

TTL

Dual Inverting Channels + Dual Enable

Dual Non-Inverting Channels + Dual Enable

Dual Channels of Two-Input/One-Output

Single Inverting Channel + Enable

SOIC8, MLP8

CMOS

TTL

CMOS

TTL

FAN3121C Single 9A +9.7A / -7.1A

FAN3121T Single 9A +9.7A / -7.1A

FAN3122T Single 9A +9.7A / -7.1A

FAN3122C Single 9A +9.7A / -7.1A

Notes:

CMOS

TTL

Single Inverting Channel + Enable

CMOS

TTL

Single Non-Inverting Channel + Enable

13. Typical currents with OUT at 6V and V_DD=12V.

14. Thresholds proportional to an externally supplied reference voltage.

www.fairchildsemi.com

FAN3278 • Rev. 1.0.0

13

Physical Dimensions

5.00

4.80

A

0.65

3.81

8

5

B

1.75

6.20

5.80

4.00

3.80

5.60

1

4

PIN ONE

INDICATOR

1.27

(0.33)

M

0.25

C B A

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.10

0.25

0.19

C

1.75 MAX

0.10

C

0.51

0.33

OPTION A - BEVEL EDGE

0.50

0.25

x 45°

R0.10

GAGE PLANE

OPTION B - NO BEVEL EDGE

0.36

NOTES: UNLESS OTHERWISE SPECIFIED

8°

0°

0.90

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

SEATING PLANE

(1.04)

0.406

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

DETAIL A

SCALE: 2:1

Figure 21. 8-Lead, Small-Outline Integrated Circuit (SOIC)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,

specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FAN3278 • Rev. 1.0.0

www.fairchildsemi.com

14

FAN3278 • Rev. 1.0.0

www.fairchildsemi.com

15


型号：	FAN3278TMX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	30V PMOS-NMOS Bridge Driver 30V PMOS- NMOS桥驱动器驱动器
文件：	总15页 (文件大小：458K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FAN3278TMX [FAIRCHILD]

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