FAN3506 [FAIRCHILD]
PC SMPS Secondary Side Control IC; PC开关电源二次侧控制IC
| 型号： | FAN3506 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | PC SMPS Secondary Side Control IC |
| 文件： | 总16页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FAN3506
PC SMPS Secondary Side Control IC
Features
Description
• Few External Components
The FAN3506 is complete housekeeping circuitry for use in
the secondary side of PC SMPS (Switched Mode Power
Supply). It contains various functions, which are over
voltage protection including two extra protection inputs,
power supply on/off delay control and power good signal
generator. Especially, it contains a programmable shunt
regulator for output feedback and the reference voltage is
trimmed to ±2%. The FAN3506 is available in 16-DIP.
• Low Voltage Operation (Vcc_min=4.5V)
• Over Voltage Protection for 3.3V/5V/12V Output
• Two Protection Inputs (PT1, PT2)
• Fault Protection Output with Open Collector
• Power Supply on/off Delay Time Control (PSON)
• Latch Function Controlled by PSON and Protection
• Power Good Signal Generator with Hysteresis
• 300ms(Typ) Power Good Delay
16-DIP
• Programmable Shunt Regulator Trimmed to ±2%
• 16-Pin Dual In-line Package (16-DIP-300)
1
Block Diagram
FPO
5
V
CC
V33
1
V5 V12
4
2
3
lchg
PG
R1
R5
R3
R4
V
CC
R9 R11
9
R7
R8
V
CC
_
_
_
+
PT1
+
+
+
+
_
13
14
Q3
R10
R12
COMP4
3.9V
+
+
_
S
R
COMP6
Q
1.32V~1.26V
PT2
Q1
R6
R2
1.8V~1.2V
1.26V
Q2
V
CC
_
V
CC
V
CC
+
lil
COMP5
V
CC
loff
V
CC
lon
PSON
IK
15
V
CC
7
_
+
+
_
+
_
1.32V~1.26V
1.26V
COMP3
COMP2
3.2V
16
1.8V~0.6V
1.4V
VREF
6
8
TPSON
11
PGI
12
GND
10
TPG
Rd
Rev. 1.0.2
©2002 Fairchild Semiconductor Corporation
FAN3506
Pin Description
No
1
Name
V33
V5
I/O
Function
+3.3V Output Voltage of SMPS Secondary Side
+5V Output Voltage of SMPS Secondary Side
+12V Output Voltage of SMPS Secondary Side
I
I
I
2
3
V12
Supply Voltage. +5Vsb(+5V Standby Supply) is Recommended for Vcc.
The Operating Range is 4.5V~15V. Vcc=5V, Ta=25°C at test.
4
5
V
I
CC
Fault Protection Output(FPO) With Open Collector Structure. This Signal Controls the
Primary Switch(PWM IC) Through an Opto-coupler. Maximum Current Rating is 20mA.
When FPO = "Low", the Main SMPS is Operational and if FPO = "High", the Main SMPS
is Turned-off.
FPO
Rd
O
OFF Delay Resistor. This Block is Made up of a Buffer With Vout = 1.258V. A Resistor
Should be Connected to the Pin6 for Determination of Off Delay Current. The
Recommended Value of Rd Resistor is 28kΩ at Ctpson=0.22uF. The off Delay Time is
Gotten by Following Equation. Toff = [ Ctpson * (V8max-VthL) ] / (1.258V/Rrd)
6
7
-
I
Power Supply On/Off (Remote On/Off) Input. It is TTL Operation and its Threshold
Voltage is 1.4V. The Maximum Voltage of Pin7 is About 3.9V(Typ), With ABsolutely
Maximum Voltage, 5.25v. If Pson Is Low, Fpo Is Low, Too. That Means The main SMPS
is Operation(Active). When PSON is High, then FPO is High and the Main SMPS is off.
PSON
Power Supply On/Off Delay. Ton/Toff = 24ms/8ms(Typ) with Ctpson=0.22uF &
Rd=28kΩ. Its High/Low Threshold Voltages 1.8V/0.6V and the Maximum Voltage After
Full Charging is About 2.2V. So Vcharge = VthH = 1.8V and Vdischg = V8max - VthL =
1.6V.
8
TPSON
-
Each Delay Time is Decided by the Following Equations, Ton = (Ctpson*VthH) / Ion, Toff
= [Ctpson*(V8max-VthL)] / (Vrd/Rrd) .
Power Good Signal Output with Open Collector. The Maximum Current Rating is 20mA.
PG High Means that the Power is Good for Operation and PG low Means Power Fail.
9
PG
TPG
PGI
O
-
PG Delay. Td = 300ms(Typ) with Ctpg=2.2uF. The Threshold Voltage is 1.8V and the
Delay Time is Decided by the Following Equation, Td = (Ctpg * Vth) / Ichg = 1.8Ctpg /
Ichg.
10
11
Power Good Signal Input. Its Threshold Voltage is 1.26V When the PGI Voltage Drops
From High to Low.
I
12
13
14
GND
PT1
PT2
-
I
I
Ground
Protection Input 1. This can be Used for an Adjustable OVP or Another Protection Input.
Protection Input 2. This can be Used for an Adjustable OVP or Another Protection Input.
Cathode of the Programmable Shunt Regulator. Absolute Min/Max Current Rating is
1mA/30mA.
15
16
IK
I
I
Reference of Programmable Shunt Regulator. This Circuit is Prepared for Feedback of
Output Voltage as it Equals to KA431(LM431). It is Trimmed to ±2%.
V
REF
2
FAN3506
Absolute Maximum Ratings
Parameter
Symbol
Value
4.5 ~ 15
20
Unit
V
Supply Voltage
V
CC
FPO (Fault Protection Output) Voltage
FPO Maximum Current
PGI Maximum Voltage
PG Output Maximum Current
Cathode Voltage
VFPO
IFPO
Vpgi
Io(PG)
Vka
V
20
mA
V
20
20
mA
V
20
Cathode Current for IK
Power Dissipation
IK
1 ~ 30
1
mA
W
P
D
Operating Temperature Range
Storage Temperature
T
-25 ~ +80
-65 ~ +150
°C
°C
OPR
T
STG
Electrical Characteristics
(V
CC
= 5V, T = 25°C, unless otherwise specified)
a
Parameter
Symbol
Test Conditions
Min. Typ. Max. Unit
PROTECTION SECTION
OVP Detecting Voltage for 3.3V
OVP Detecting Voltage for 5V
OVP Detecting Voltage for 12V
Protection Input Voltage 1
Protection Input Voltage 2
V
V
33
OVP
PSON=0V
3.9
5.7
4.1
6.1
4.3
6.5
V
V
V
V
V
V
5
OVP
PSON=0V
PSON=0V
PSON=0V
PSON=0V
12
OVP
13.6 14.3 15.0
1.21 1.26 1.31
1.21 1.26 1.31
V 1
pt
V 2
pt
POWER SUPPLY ON/OFF SECTION (PSON)
PSON Input Threshold Voltage
PSON Input Open Voltage
V
V
PSON=0V : 0V to 2V
PSON : Open
1
2
1.4
-
1.8
5.25
-1
V
V
th
ih
PSON Input Low Current
lil
PSON=0V
0
-
mA
uA
V
PSON Delay Charging Current
Buffer Output Voltage
lon
PSON=TPSON=0V
lsink=45uA, 200uA
PSON=0V
-10
-16
-24
VRd
1.21 1.26 1.31
Pin8 Clamping Voltage
V
2.0
1.6
0.4
16
4
2.2
1.8
0.6
26
2.4
2.0
0.8
36
14
0.4
1
V
8max
VthH
VthL
Ton
High Threshold for On/Off Delay (Note1)
Low Threshold for On/Off Delay (Note2)
Power Supply ON Delay Time (Note3)
Power Supply OFF Delay Time (Note4)
FPO Saturation Voltage
TPSON : 0V to 2.2V
TPSON : 2.2V to 0V
Cpin8=0.22µF, Rd=28kΩ
Cpin8=0.22µF, Rd=28kΩ
V
V
msec
msec
V
Toff
8
V
(FPO) lo=10mA
sat
-
0.2
0.01
FPO Leakage Current
lleak(FPO) FPO=20V
0
uA
3
FAN3506
Electrical Characteristics (Continued)
(V = 5V, T = 25°C, unless otherwise specified)
CC
a
Parameter
Symbol
Test Conditions
Min. Typ. Max. Unit
POWER GOOD SECTION
PGI Threshold Voltage
V33 Under Voltage Level
V5 Under Voltage Level
V12 Under Voltage Level
Pin10 Clamping Voltage
V
PGI : 1.5V to 1V
V33 : 3.3V to 2V
V5 : 5V to 3.5V
V12 : 12V to 9V
TPG : Open
1.21 1.26 1.31
V
V
pgi
V 33
uv
2.66
4.1
9.8
3.4
1.5
0.3
-9
2.8
4.3
2.94
4.5
V 5
uv
V
V 12
uv
10.3 10.8
V
V10
3.9
1.8
0.6
-15
300
1
4.4
2.1
0.9
-23
V
max
PG Delay Comparator Threshold Voltage Vth(TPG) TPG : 0V to 2.5V
V
PG Delay Comparator Hysteresis Voltage
Charging Current for PG Delay
PG Delay Time
HY
lchg
Td(PG)
Tr
TPG : 2.5V to 0V
TPG = 0V
V
uA
Cpin10 = 2.2uF
Cpin9 = 0.1uF
Cpin9 = 0.1uF
100
-
500 msec
PG Output Rising Time (Note5)
PG Output Falling Time (Note6)
PG Output Saturation Voltage
PG Output Leakage Current
-
-
usec
usec
V
Tf
-
1
Vsat(PG) lsink = 15mA
lleak(PG) V(PG) = 20V
-
0.2
0.01
0.4
1
0
uA
PROGRAMMABLE SHUNT REGULATOR (KA431) SECTION
Reference Input Voltage
Load Regulation
V
IK = V
REF
, IK = 1mA
2.45 2.50 2.55
V
ref
Vref
∆Vref/∆T
lsink
IK = 1mA to 10mA
-
-
5
4.5
25
1
15
17
-
mV
mV
mA
MHz
Temperature Stability (Note7)
Output Sinking Current Capability
Gain Bandwidth (Note8)
TOTAL DEVICE
Ta = -25 ~ +85°C
-
10
-
GBW
GV = 1
-
Supply Current
Icc
PSON = 2V
-
3
8
mA
Note :
1. Power Supply ON Delay (PSON :High → Low). Power Supply is Active when PSON is Low.
2. Power Supply OFF Delay (PSON :Low → High). Power Supply is Off when PSON is High.
3. Ton = (Cpin8 * Von) / lon = (Cpin8 * VthH) / lon
4. Toff = (Cpin8 * Voff) / loff = [Cpin8 * (V8max - VthL)] / (VRd / Rd)
5,6,7,8 : These parameters, although guaranteed, are but not 100% tested in production.
4
FAN3506
Block Description & Application Hints
1. OVP Block
V5
2
V33
1
V12
3
R5
R1
R3
VCC
+
+
+
+
PT1 13
SET of Latch
PT2
14
+
_
COMP1
R2
R4
R6
1.26V
OVP function is simply realized by connecting Pin1, Pin2, Pin3 to each secondary output. R1,2,3,4,5,6 are internal resistors of
the IC. Each OVP level is determined by resistor ratio and the typical values are 4V/6.1V/14.2V.
- OVP Detecting voltage for +3.3V
. Vovp33 = (R1+R2)/R2 * 1.26V = 4.1V(Typ)
- OVP Detecting voltage for +5V
. Vovp5 = (R3+R4)/R4 * 1.26V = 6.1V(Typ)
- OVP Detecting voltage for +12V
. Vovp12 = (R5+R6)/R6 * 1.26V = 14.3V(Typ)
Especially, Pin13 & Pin14 are prepared for extra OVP inputs or another protection signal, respectively. That is, if you want
over voltage protection of extra output voltage, then you can make a function with two external resistors.
- Threshold Voltage of Protection Input 1 : Vpt1 = 1.26V
- Threshold Voltage of Protection Input 2 : Vpt1 = 1.26V
OVP function operates without delay time. In the case of OVP, system designer should know a fact that the main power can be
dropped after a little time because of system delay, even if FPO is triggered by OVP.
So when the OVP level is tested with a set, you should check the secondary outputs(+3.3V/+5V/+12V) and FPO(Pin5)
simultaneously. you can know the each OVP level as checking each output voltage in just time that FPO is triggered from low
to high.
5
FAN3506
2. PSON & ON /OFF Delay Block
FPO
5
Ton
Toff
PSON
FPO
OVP
S
Q
Q1
R
VCC
VCC
lon
lil
VCC
VCC
VCC
+
_
loff
_
+
VCC
+
1.26V
COMP2
3.2V
COMP3
_
1.4V
1.5V ~ 0.6V
PG
11
7
8
TPSON
Rd
PSON
R1
27K
C1
103
PSON & On/Off Delay Block is controlled by a Microprocessor.
If a high signal is supplied to the PSON(Pin7), the output of COMP2 becomes high status. The output signal is transferred to
On/Off delay block and PG block.
If no signal is supplied to Pin7, Pin7 maintains high status(=3.2V) for the internal pull-up resistor.
When PSON is high, it produces FPO(Pin5) "High" signal after OFF delay time (about 8ms) for stabilizing system.
Then, all outputs (+3.3V, +5V, +12V) are grounded.
When PSON is changed to "Low", it produces FPO "Low" signal after ON delay time (about 26ms) for stabilizing the
system.
If PSON is low, then FPO is low. That means the main SMPS is Active(operational). When PSON is high, FPO is high and the
main SMPS is turned-off.
On/Off Delay Time can be calculated by following equation. 0.22uF Capacitor is recommended for following equations.
- Ton = (Ctpson*VthH)/Ion=(0.22uF*1.8V)/16uA = 26ms
- Toff = [Ctpson*(V8max-VthL)] / Ioff = [Ctpson*(V8max-VthL)] / (VRd/Rd)
Because Ion current for charging is fixed by internal current source, On delay time is varied by the capacitor value. On the con-
trary, Off Delay time is decided by the Rd value. If the Rd is 27K(Recommended) and the Delay capacitor valuse is 0.22uF,
Toff is 8ms(Typ).
6
FAN3506
3. Latch & FPO Output
OVP
L
SET
L
RESET
Qn+1
Qn+1
Qn
H
L
H
L
Qn
L
L
L
H
H
H
L
L
H
H
H
H
+5Vsb
7
PWM IC
(KA38XX)
PC800-1
2
1
R8
1K
FPO
6
Q100
OVP
PSON
Q1
PC800-2
Power Good Signal Generator circuits generate "On & Off" signal depending on the status of output voltage to prevent the
malfunctions of following systems like microprocessor and etc. from unstable outputs at power on & off .
At Power On, it produces PG "High" signal after some delay (300ms_Typ) for stabilizing outputs.
At power Off, it produces PG "Low" signal without delay by sensing the status of power source for protecting following
systems. COMP6 creates PG "Low" without delay when +5V output falls to less than 4.3V to prevent some malfunction at
transient status, thus it improves system stability. FAN3506 detects the Under Voltage level of three
outputs(+3.3V/+5V/+12V) and PGI, respectively.
- UV Deducing Level of +3.3V : Vuv33 = 2.8V(Typ)
- UV Deducing Level of +5V : Vuv5 = 4.3V(Typ)
- UV Deducing Level of +12V : Vuv12 = 10.3V(Typ)
- UV Deducing Level of PGI : Vpgi = 1.26V(Typ)
When PSON signal is high, it generates PG "Low" signal without delay. It means that PG becomes "Low" before main power
is grounded. PG delay time(Td(PG)) is determined by capacitor value, threshold voltage of COMP6 and the charging current
and its equation is as following.
Td(PG) = (Ctpg * VthH) / Ichg = 300ms(Typ)
7
FAN3506
4. Programmable Shunt Regulator
V5
2
IK
V12
3
15
PC300-1
VREF
16
R1
0.11k
R3
10k
R4
39k
IK
15
PWM IC
(KA38XX)
R2
1k
8
C1
103
1
2
C2
224
16
VREF
PC300-2
R5
4.7k
R6
1k
The core of the circuit equals to KA431(LM431) and Vref1 is trimmed to ±2% (2.45V ~ 2.55V) and it is for corrective output
voltages (+5V/+12V). + 5V/ + 12V output voltages are determined by the resistor ratio of R3, R4, R5, R6.
A photo coupler is used in order to control PWM IC in the primary side. R1 determines the bias current of the shunt regulator
and 110Ω is appropriate value. The resistor value can be changed by set condition and requirements.
C1 and R2 , C2 are the compensation circuit for stability.
8
FAN3506
Typical Application Circuit
PC300-1
39K
10K
0.11K
#1
+3.3V
+5V
V33
V5
VREF
224
1K
+5Vsb
103
IK
1K
5K
F
A
N
3
5
0
6
+12V
V12
Vcc
PT2
PT1
PT2
PC800-1
PT1
GND
PGI
1K
Det
FPO
27K
FPO
V =12V
Z
Rd
2.2uF
20K
+
PSON
Micom
TPG
PG
224
TPSON
Micom
[ Complete Housekeeping Circuit using the FAN3506 ]
L
7
+3.3V/+5V/+12V
I
PWM IC
O
8
(KA38XX)
+
1
2
PC300-2
Q100
PC800-2
9
FAN3506
Typical Performance Characteristics
Figure 1. Temperature Stability for VRd
Figure 2. Buffer Output Voltage vs. IRd
Figure 4. Current Stability of Vref
Figure 3. Temperature Stability for Vref
Figure 5. OVP Detecting Voltage for 3.3V
Figure 6. OVP Detecting Voltage for 5V
10
FAN3506
Typical Performance Characteristics (Continued)
Figure 7. OVP Detecting Voltage for 12V
Figure 8. Protection Input Voltage 1,2
Figure 10. High/Low Threshold of On/Off Delay
Figure 9. PSON Input Threshold Voltage
Figure 12. PGI Threshold Voltage
Figure 11. FPO Saturation Voltage
11
FAN3506
Typical Performance Characteristics (Continued)
Figure 14. V5 Under Voltage Level
Figure 13. V33 Under Voltage Level
Figure 16. High/Low Threshold of
PG Delay COMP
Figure 15. V12 Under Voltage Level
Figure 18. Supply Current of V
Figure 17. PG Saturation Voltage
CC
12
FAN3506
Typical Performance Characteristics (Continued)
Figure 19. Power Supply On/Off Delay Time
Figure 20. PG Delay Time
13
FAN3506
Mechanical Dimensions
Package
Dimensions in millimeters
16-DIP
6.40 ±0.20
0.252 ±0.008
#1
#16
#8
#9
3.25 ±0.20
0.128 ±0.008
0.38
MIN
7.62
0.300
0.014
3.30 ±0.30
0.130 ±0.012
5.08
MAX
0.200
14
FAN3506
Ordering Information
Product Number
Package
16-DIP
Operating Temperature
FAN3506
-25°C ~ +85°C
15
FAN3506
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
11/15/02 0.0m 001
Stock#DSxxxxxxxx
2002 Fairchild Semiconductor Corporation
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