FAN5240MSA [FAIRCHILD]
Dual Switching Controller, Current-mode, 345kHz Switching Freq-Max, PDSO28, QSOP-28;
| 型号： | FAN5240MSA |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual Switching Controller, Current-mode, 345kHz Switching Freq-Max, PDSO28, QSOP-28 开关 光电二极管 |
| 文件： | 总3页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Application Bulletin
AB-27
Layout Guidelines for the FAN5240, PWM Controller for AMD Mobile
Athlon™ and Mobile Duron™ Processors
---Ron Lenk, Senior Staff Applications Engineer
10/10/01
Athlon and Duron are trademarks of Advanced Micro Devices, Inc.
AB-27 Rev. 0.2
1
Summary
The FAN5240 PWM Controller for AMD’s Mobile Athlon and Mobile Duron
processors is pinned out in such a way as to make good layout practices easy. A sample
layout is shown, and recommendations for other connections and for grounds are
detailed.
The FAN5240 is Pinned Out for Ease of Layout
The FAN5240 is designed to power the core of AMD’s Mobile Athlon and Mobile Duron CPUs.
The pin assignments for the IC have been made in such a way as to make the layout of the power
components especially easy, using SO-8 packages for the power MOSFETs. A sample of a recommended
layout is shown in Figure 1.
VIN
VOUT
Q2
Q1
L2
Q3
FAN5240
Q5
L1
Q4
Q6
0.3”
Figure 1. Sample Layout for Converter.
Legend: Light gray areas are top-side power plane. Dark gray traces are internal layer.
In this Figure, corresponding to the circuit of Figure 1 in the FAN5240 datasheet, all components
are assumed to be surface mount, and so the power connections are on the top layer, shown in light gray.
The connections to the gates of the MOSFETs, shown in dark gray, are done on an internal layer, through
vias (not shown) to a signal layer immediately adjacent to a ground plane layer. This is done both to
prevent contamination of other signals with the high frequency gate drive, as well as to prevent gate
bounce.
AB-27 Rev. 0.2
2
As can be seen, the entire power sector of the design can be done in a very compact area. The two
slices of the converter are symmetrically placed, top and bottom. The source of the high-side MOSFET
faces the drains of the low-side MOSFETs, allowing a single pour to pick up this node. It is then wrapped
around to the input to the inductor, and the outputs of the inductors face each other and the output
capacitors, allowing this also to be a single pour. This can then be continued over to the power pins of the
CPU, which should be as close as possible to the converter.
The gate drive pins of the FAN5240 are configured in such a way that the traces to the SO8
MOSFETs need not cross each other; the IC should be oriented as shown relative to the MOSFETs.
Other Layout Recommendations
• Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the FAN5240 to the
FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the
inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and,
because it is switching at such a high voltage and frequency, it is very difficult to suppress.
• In general, all of the noisy switching lines should be kept away from the quiet analog section of the
FAN5240. That is, traces that connect to pins 7 through 21 should be kept far away from the traces that
connect to pins 1 through 6, and pins 23 through 27. The VSEN+ and VSEN- pins in particular should be
run as a pair, side by side, on a signal plane isolated from the power plane by a ground.
• Place the 0.1µF decoupling capacitors as close to the FAN5240 pins as possible. Extra lead length on
these reduces their ability to suppress noise.
• There should be a solid layer dedicated to ground. The ground plane should be broken into two parts, a
small signal ground and a power ground. There should be only a single connection point between the two.
• Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition,
placement of a 0.1µF decoupling cap right on the drain of each high side MOSFET helps to suppress some
of the high frequency switching noise on the input of the DC-DC converter.
• Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply
instantaneous current to the load in the event of a current transient. Additional space between the output
capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC
converter’s performance under severe load transient conditions, causing higher voltage deviation. The
remote sense pins (pins 16 and 17) should be attached as closely as possible to the CPU.
• A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-
11.
AB-27 Rev. 0.2
3
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