FAN5355UC07X [FAIRCHILD]
1A / 0.8A, 3MHz Digitally Programmable TinyBuckTM Regulator; 1A / 0.8A ， 3MHz的数字可编程TinyBuckTM稳压器
| 型号： | FAN5355UC07X |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 1A / 0.8A, 3MHz Digitally Programmable TinyBuckTM Regulator |
| 文件： | 总27页 (文件大小：1995K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2008
FAN5355
1A / 0.8A, 3MHz Digitally Programmable TinyBuckTM Regulator
Features
Description
The FAN5355 device is a high-frequency, ultra-fast transient
response, synchronous step-down DC-DC converter
optimized for low-power applications using small, low-cost
inductors and capacitors. The FAN5355 supports up to
800mA or 1A(1) load current.
91% Efficiency at 3MHz
800mA or 1A Output Current(1)
2.7V to 5.5V Input Voltage Range
6 or 7-bit VOUT Programmable from 0.75 to 1.975V
3MHz Fixed-Frequency Operation
Excellent Load and Line Transient Response
Small Size, 1μH Inductor Solution
±2% PWM DC Voltage Accuracy
35ns Minimum On-Time
The device is ideal for mobile phones and similar portable
applications powered by a single-cell Lithium-Ion battery. With
an output voltage range adjustable via I2C™ interface from
0.75V to 1.975V, the device supports low-voltage DSPs and
processors, core power supplies in smart phones, PDAs, and
handheld computers.
The FAN5355 operates at 3MHz (nominal) fixed switching
frequency using either its internal oscillator or external SYNC
frequency.
High-Efficiency, Low-Ripple, Light-Load PFM
Smooth Transition between PWM and PFM
37μA Operating PFM Quiescent Current
During light-load conditions, the regulator includes a PFM
mode to enhance light-load efficiency. The regulator
transitions smoothly between PWM and PFM modes with no
glitches on VOUT. Normal PFM (NPFM) mode offers the lowest
quiescent current, at the expense of setpoint accuracy.
Enhanced PFM (EPFM) mode features higher accuracy, as
well as a 25kHz minimum PFM frequency, designed to
prevent the regulator from operating in the audible range. In
shutdown, the current consumption is reduced to less than
2μA, using software shutdown (EN = 1 with EN_DCDC = 0),
and less than 200nA in hardware shutdown (EN = 0).
Software Selectable 25kHz Minimum PFM Frequency
Prevents Audible Noise in PFM Mode
I2C™-Compatible Interface up to 3.4Mbps
Pin-Selectable or I2C™ Programmable Output Voltage
On-the-Fly External Clock Synchronization
10-lead MLP (3 x 3mm) or 12-bump CSP Packages
The serial interface is compatible with Fast/Standard and
High-Speed mode I2C specifications, allowing transfers up to
3.4Mbps. This interface is used for dynamic voltage scaling
with 12.5mV voltage steps, for reprogramming the mode of
operation (PFM or Forced PWM), or to disable/enable the
output voltage.
Applications
SmartReflex™-Compliant Power Supply
Split Supply DSPs and μP Solutions OMAP™, XSCALE™
Cell Phones, Smart Phones, PDAs, Digital Cameras, and
Portable Media Players
The chip's advanced protection features include short-circuit
protection and current and temperature limits. During a
sustained over-current event, the IC shuts down and restarts
after a delay to reduce average power dissipation into a fault.
Micro DC-DC Converter Modules
Handset Graphic Processors (NVIDIA®, ATI)
During start-up, the IC controls the output slew rate to
minimize input current and output overshoot at the end of soft-
start. The IC maintains a consistent soft-start ramp, regardless
of output load during start-up.
I2C is a trademark of Philips Corporation.
SmartReflex and OMAP are trademarks of Texas Instruments.
XSCALE is a trademark of Intel Corporation.
The FAN5355 is available in 10-lead MLP (3x3mm) and
12-bump CSP packages.
NVIDIA is a registered trademark of NVIDIA Corporation.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
www.fairchildsemi.com
Ordering Information
Slave
Address LSB
Power-up
Defaults
VOUT Programming
Order Number (4) Option
Package (4)
A1
0
A0
0
DAC
MIN.
0.7500
0.7500
0.7500
0.7500
1.1875
0.7500(3)
0.7500(3)
MAX. VSEL0 VSEL1
FAN5355UC00X
FAN5355MP00X
FAN5355UC02X
FAN5355UC03X
FAN5355UC06X
FAN5355UC07X
FAN5355MP07X
00
00
6
6
6
6
6
7
7
1.5375
1.5375
1.4375(2)
1.5375
1.9750
1.9750
1.9750
1.05
1.05
1.05
1.00
1.80
1.05
1.05
1.35
1.35
1.20
1.20
1.80
1.35
1.35
WLCSP-12, 2.23x1.46mm
MLP-10, 3x3mm
0
0
02
1
0
WLCSP-12, 2.23x1.46mm
WLCSP-12, 2.23x1.46mm
WLCSP-12, 2.23x1.46mm
WLCSP-12, 2.23x1.46mm
MLP-10, 3x3mm
03
0
0
06(1)
07(1)
07(1)
0
0
1
1
1
1
Notes:
1. Option 06 and 07 is rated for 1A output current. All other options are rated for 800mA output current.
2. VOUT is limited to the maximum voltage for all VSEL codes greater than the maximum VOUT listed.
3. VOUT may be programmed down 100mV for option 07. Performance below 0.75V is not guaranteed.
4.
All packages are “green” per JEDEC: J-STD-020B standard. The “X” designator specifies tape and reel packaging.
Typical Application
AVIN
PVIN
VIN
Q1
Q2
CIN
EN
VSEL
SYNC
VOUT
SW
L OUT
MODULATOR
COUT
SDA
SCL
PGND
VOUT
AGND
Figure 1. Typical Application
Component
Description
1μH nominal
Vendor
Parameter
Min. Typ. Max.
Units
μH
L(5)
0.7
1.0
1.2
Murata LQM31P
or FDK MIPSA2520
L1 (LOUT
)
DCR (series R)
100
mΩ
0603 (1.6x0.8x0.8)
10μF X5R or better
Murata or equivalent
GRM188R60G106ME47D
COUT
CIN
C(6)
C(6)
5.6
3.0
10.0
4.7
12.0
5.6
μF
μF
0603 (1.6x0.8x0.8)
4.7μF X5R or better
Murata or equivalent
GRM188R60J475KE19D
Table 1. Recommended External Components
Notes:
5. Minimum L incorporates both tolerance, temperature, and partial saturation effects (L decreases with increasing current).
6. Minimum C is a function of initial tolerance, maximum temperature, and the effective capacitance being reduced due to
frequency, dielectric, and voltage bias effects.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
2
www.fairchildsemi.com
Pin Configuration
PVIN
AVIN
SDA
SW
1
2
3
4
5
10
9
A1
B1
C1
D1
A2
B2
C2
A3
B3
C3
D3
A3
B3
C3
D3
A2
B2
C2
D2
A1
B1
C1
D1
PGND
AGND
EN
PAD
8
AGND
SCL
7
D2
VSEL
VOUT
6
Top View
Bottom View
Top View
Figure 2. WLCSP- 12, 2.23x1.46mm
Figure 3. MLP10, 3x3mm
Pin Definitions
Pin #
Name Description
WLCSP
A1, B1
A2
MLP
9
Power GND. Power return for gate drive and power transistors. Connect to AGND on PCB. The
connection from this pin to the bottom of CIN should be as short as possible.
PGND
SW
10
1
Switching Node. Connect to output inductor.
Power Input Voltage. Connect to input power source. The connection from this pin to CIN should be as
short as possible.
A3
PVIN
Sync. When toggling and SYNC_EN bit is HIGH, the regulator synchronizes to the frequency on this pin.
In PWM mode, when this pin is statically LOW or statically HIGH, or when its frequency is outside of the
specified capture range, the regulator’s frequency is controlled by its internal 3MHz clock.
B2
N/A
SYNC
Analog Input Voltage. Connect to input power source as close as possible to the input bypass
capacitor.
B3
C1
2
AVIN
Analog GND. This is the signal ground reference for the IC. All voltage levels are measured with respect
to this pin.
8, PAD
AGND
Enable. When this pin is HIGH, the circuit is enabled. When LOW, quiescent current is minimized. This
pin should not be left floating.
C2
C3
D1
7
3
6
EN
SDA
SDA. I2C interface serial data.
Output Voltage Monitor. Tie this pin to the output voltage. This is a signal input pin to the control circuit
and does not carry DC current.
VOUT
Voltage Select. When HIGH, VOUT is set by VSEL1. When LOW, VOUT is set by VSEL0. This behavior
D2
D3
5
4
VSEL
SCL
can be overridden through I2C register settings. This pin should not be left floating.
SCL. I2C interface serial clock.
Note:
7. All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum
quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I2C control is unused, tie SDA and SCL to AVIN.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
3
www.fairchildsemi.com
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings
are stress ratings only.
Symbol Parameter
Min.
-0.3
Max.
6.5
AVIN + 0.3(8)
Units
V
AVIN, SW, PVIN Pins
VCC
Other Pins
-0.3
V
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
3.5
1.5
KV
KV
°C
ESD
Electrostatic Discharge Protection Level
TJ
TSTG
TL
Junction Temperature
–40
–65
+150
+150
+260
Storage Temperature
°C
Lead Soldering Temperature, 10 Seconds
°C
Note:
8. Lesser of 6.5V or VCC+0.3V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding
them or designing to absolute maximum ratings.
Symbol Parameter
Min.
2.7
Max.
5.5
Units
V
VIN
f
Supply Voltage
Frequency Range
2.7
3.3
MHz
V
VSW
TA
TJ
SDA and SCL Voltage Swing(9)
Ambient Temperature
Junction Temperature
2.5
–40
–40
+85
+125
°C
°C
Note:
9. The I2C interface operates with tHD;DAT = 0 as long as the pull-up voltage for SDA and SCL is less than 2.5V. If voltage
swings greater than 2.5V are required (for example if the I2C bus is pulled up to VIN), the minimum tHD;DAT must be
increased to 80ns. Most I2C masters change SDA near the midpoint between the falling and rising edges of SCL, which
provides ample tHD;DAT
.
Dissipation Ratings(10)
(11)
Package
RθJA
Power Rating at TA ≤ 25°C
Derating Factor > TA = 25ºC
Molded Leadless Package (MLP)
Wafer-Level Chip-Scale Package (WLCSP)
49ºC/W
2050mW
900mW
21mW/ºC
9mW/ºC
110ºC/W
Notes:
10. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any
allowable ambient temperature is PD = [TJ(max) - TA ] / θJA.
11. This thermal data is measured with high-K board (four-layer board according to JESD51-7 JEDEC standard).
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
4
www.fairchildsemi.com
Electrical Specifications
VIN = 3.6V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40°C to +85°C, unless otherwise
noted. Typical values are at TA = 25°C. Circuit and components according to Figure 1.
Symbol Parameter
Power Supplies
Conditions
Min.
Typ.
Max.
Units
VIN
Input Voltage Range
2.7
5.5
150
50
V
IO = 0mA, EPFM Mode, FPFM = 25kHz
IO = 0mA, NPFM Mode
IO = 0mA, 3MHz PWM Mode
EN = GND
110
37
μA
μA
mA
IQ
Quiescent Current
4.8
0.1
2.0
2.0
I SD
Shutdown Supply Current
μA
EN = VIN, EN_DCDC bit = 0,
SDA = SCL = VIN
0.1
VIN Rising
VIN Falling
2.40
2.15
250
2.60
2.30
300
V
V
VUVLO
Under-Voltage Lockout Threshold
Under-Voltage Lockout Hysteresis
2.00
200
VUVHYST
mV
ENABLE, VSEL, SDA, SCL, SYNC
VIH
VIL
IIN
HIGH-Level Input Voltage
LOW-Level Input Voltage
Input Bias Current
1.2
V
V
0.4
Input tied to GND or VIN
0.01
1.00
μA
Power Switch and Protection
VIN = 3.6V, CSP Package
VIN = 3.6V, MLP Package
VIN = 2.7V, MLP Package
VDS = 6V
145
165
200
RDS(ON)P
P-channel MOSFET On Resistance
mΩ
ILKGP
P-channel Leakage Current
1
μA
VIN = 3.6V, CSP Package
VIN = 3.6V, MLP Package
75
95
RDS(ON)N
N-channel MOSFET On Resistance
mΩ
V
IN = 2.7V, MLP Package
101
ILKGN
RDIS
N-channel Leakage Current
VDS = 6V
1
μA
Discharge Resistor for Power-down
Sequence
Options 03, 06, 07
15
50
Ω
2.7V ≤ VIN ≤ 4.2V, All Options Except 06
and 07
1150
1350
1350
1600
ILIMPK
P-MOS Current Limit
2.7V ≤ VIN ≤ 5.5V, All Options Except 06
and 07
mA
1050
1300
1600
1800
2.7V ≤ VIN ≤ 4.2V, 06 and 07 Option
1550
150
20
TLIMIT
THYST
Thermal Shutdown
°C
°C
Thermal Shutdown Hysteresis
Frequency Control
fSW
Oscillator Frequency
2.65
2.7
20
3.00
3.0
3.35
3.3
80
MHz
MHz
%
fSYNC
Synchronization Range
DSYNC
fSYNCVAL
fPFM(MIN)
Synchronization Duty Cycle
SYNC Frequency Rejection
Minimum PFM Frequency
1.6
4.3
MHz
kHz
EPFM Mode, ILOAD = 0
25
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
5
www.fairchildsemi.com
Electrical Specifications (Continued)
VIN = 3.6V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40°C to +85°C, unless otherwise
noted. Typical values are at TA = 25°C. Circuit and components according to Figure 1
Symbol Parameter
Output Regulation
Conditions
Min.
Typ.
Max.
Units
IOUT(DC) = 0, Forced PWM, VOUT = 1.35V
–1.5
–2
1.5
2
%
%
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.5375,
IOUT(DC) = 0 to 800mA, Forced PWM
Option 00
Option 02
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.5375,
–1.5
–1.5
–2
3.5
1.5
2
%
%
%
I
OUT(DC) = 0 to 800mA, NPFM Mode
IOUT(DC) = 0, Forced PWM, VOUT = 1.20V
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.4375,
IOUT(DC) = 0 to 800mA, Forced PWM
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.4375,
IOUT(DC) = 0 to 800mA, NPFM Mode
–1.5
–1.5
–2
3.5
1.5
2
%
%
%
IOUT(DC) = 0, Forced PWM, VOUT = 1.20V
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.5375,
IOUT(DC) = 0 to 800mA, Forced PWM
Option 03
Option 06
Option 07
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.5375,
IOUT(DC) = 0 to 800mA, NPFM Mode
–1.5
3.5
%
VOUT
VOUT Accuracy
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.5375,
IOUT(DC) = 0 to 800mA, EPFM Mode
–0.5
–1.5
–2
2
1.5
2
%
%
%
IOUT(DC) = 0, Forced PWM, VOUT = 1.800V
2.7V ≤ VIN ≤ 5.5V, VOUT from 1.185 to 1.975,
I
OUT(DC) = 0 to 1A, Forced PWM
2.7V ≤ VIN ≤ 5.5V, VOUT from 1.185 to 1.975,
IOUT(DC) = 0 to 1A, NPFM Mode
–1.5
3.5
%
2.7V ≤ VIN ≤ 5.5V, VOUT from 1.185 to 1.975,
IOUT(DC) = 0 to 1A, EPFM Mode
–0.5
–1.5
–2
2
1.5
2
%
%
%
IOUT(DC) = 0, Forced PWM, VOUT = 1.35V
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.6875,
I
OUT(DC) = 0 to 1A, Forced PWM
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.6875,
IOUT(DC) = 0 to 1A, NPFM Mode
–1.5
–0.5
3.5
2
%
%
2.7V ≤ VIN ≤ 5.5V, VOUT from 0.75 to 1.6875,
IOUT(DC) = 0 to 1A, EPFM Mode
ΔVOUT
ΔILOAD
Load Regulation
Line Regulation
I
OUT(DC) = 0 to 800mA, Forced PWM
–0.5
0
%/A
%/V
ΔVOUT
2.7V ≤ VIN ≤ 5.5V, IOUT(DC) = 300mA
ΔV
IN
PWM Mode, VOUT = 1.35V
PFM Mode, IOUT(DC) = 10mA
2.2
20
mVP-P
mVP-P
VRIPPLE
Output Ripple Voltage
Continued on the following page…
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
6
www.fairchildsemi.com
Electrical Specifications (Continued)
VIN = 3.6V, EN = VIN, VSEL = VIN, SYNC = GND, VSEL0(6) bit = 1, CONTROL2[4:3] = 00. TA = -40°C to +85°C, unless otherwise
noted. Typical values are at TA = 25°C. Circuit and components according to Figure 1.
Symbol Parameter
DAC
Conditions
Min.
Typ.
Max.
Units
Option 07
7
6
Bits
Bits
LSB
Resolution
All Other Options
Differential Nonlinearity
Monotonicity Assured by Design
0.8
Timing
I2CEN
EN HIGH to I2C Start
250
μs
μs
RLOAD = 75Ω, Transition from 1.0 to 1.5375V
tV(L-H)
VOUT LOW to HIGH Settling
7
V
OUT Settled to within 2% of Setpoint
Soft-Start
Option 06
170
140
210
180
RLOAD > 5Ω, to VOUT = 1.8000V
LOAD > 5Ω, to VOUT = Power-up Default
μs
μs
Regulator Enable
to Regulated
VOUT
tSS
All Other
Options
R
VSLEW
Soft-start VOUT Slew Rate(12)
18.75
V/ms
Note:
12. Option 06 slew rate is 35.5V/ms during the first 16μs of soft-start.
AVIN
PVIN
VIN
Q1
Q2
CIN
7-bit
DAC
REF
EN
VSEL
SYNC
SDA
VOUT
SW
I2C
SOFT START
FPWM
L OUT
INTERFACE
AND LOGIC
COUT
MODULATOR
EN_REG
CLK
SCL
PGND
VOUT
AGND
3 MHz Osc
Figure 4. Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
7
www.fairchildsemi.com
I2C Timing Specifications
Guaranteed by design.
Symbol Parameter
Conditions
Min.
Typ.
Max.
Units
Standard mode
100
400
kHz
kHz
kHz
kHz
μs
μs
μs
ns
ns
μs
ns
ns
ns
μs
ns
ns
ns
μs
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
pF
Fast mode
fSCL
SCL Clock Frequency
High-Speed mode, CB < 100pF
High-Speed mode, CB < 400pF
Standard mode
3400
1700
4.7
1.3
4
Bus-free Time between STOP and
START Conditions
tBUF
Fast mode
Standard mode
START or Repeated START Hold
Time
tHD;STA
Fast mode
600
160
4.7
1.3
160
320
4
High-Speed mode
Standard mode
Fast mode
tLOW
SCL LOW Period
SCL HIGH Period
High-Speed mode, CB < 100pF
High-Speed mode, CB < 400pF
Standard mode
Fast mode
600
60
tHIGH
High-Speed mode, CB < 100pF
High-Speed mode, CB < 400pF
Standard mode
120
4.7
600
160
250
100
10
tSU;STA
Repeated START Setup Time
Data Setup Time
Fast mode
High-Speed mode
Standard mode
tSU;DAT
Fast mode
High-Speed mode
Standard mode
0
0
0
0
3.45
900
70
Fast mode
tHD;DAT
Data Hold Time(9)
SCL Rise Time
High-Speed mode, CB < 100pF
High-Speed mode, CB < 400pF
Standard mode
150
1000
300
80
20+0.1CB
Fast mode
20+0.1CB
tRCL
High-Speed mode, CB < 100pF
High-Speed mode, CB < 400pF
Standard mode
10
20
160
300
300
40
20+0.1CB
20+0.1CB
Fast mode
tFCL
SCL Fall Time
SDA Rise Time
High-Speed mode, CB < 100pF
High-Speed mode, CB < 400pF
Standard mode
10
20
80
20+0.1CB
20+0.1CB
1000
300
80
tRDA
Fast mode
Rise Time of SCL After a Repeated
START Condition and After ACK Bit
High-Speed mode, CB < 100pF
High-Speed mode, CB < 400pF
Standard mode
10
20
tRCL1
160
300
300
80
20+0.1CB
20+0.1CB
Fast mode
tFDA
SDA Fall Time
High-Speed mode, CB < 100pF
High-Speed mode, CB < 400pF
Standard mode
10
20
4
160
tSU;STO
CB
Stop Condition Setup Time
Fast mode
600
160
High-Speed mode
Capacitive Load for SDA and SCL
400
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
8
www.fairchildsemi.com
Timing Diagrams
tF
tSU;STA
tBUF
SDA
tR
TSU;DAT
tHD;STO
tHIGH
tHD;DAT
SCL
tLOW
tHD;STA
tHD;STA
REPEATED
START
START
STOP
START
Figure 5. I2C Interface Timing for Fast and Slow Modes
REPEATED
START
STOP
tFDA
tRDA
tSU;DAT
SDAH
tSU;STA
tRCL1
tFCL
tHIGH
tHD;DAT
note A
tRCL
tSU;STO
SCLH
tLOW
tHD;STA
REPEATED
START
= MCS Current Source Pull-up
= RP Resistor Pull-up
Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.
Figure 6. I2C Interface Timing for High-Speed Mode
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
9
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Typical Performance Characteristics
Unless otherwise specified, Auto-PWM/NPFM, VIN = 3.6V, TA = 25°C, and recommended components as specified in Table 1.
Efficiency
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
Auto PWM/NPFM
Forced PWM
Auto PWM/NPFM
Forced PWM
VIN = 3.6 V
VOUT = 1.35 V
VIN = 3.6 V
VOUT = 1.05 V
1
10
100
1000
1
10
100
1000
I LOAD Output Current (mA)
I LOAD Output Current (ma)
Figure 7. Efficiency vs. Load at VOUT = 1.05V
Figure 8. Efficiency vs. Load at VOUT = 1.35V
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
Auto PWM/NPFM
Forced PWM
VIN = 3.6 V
VOUT = 1.5 V
1
10
100
1000
I LOAD Output Current (ma)
Figure 9. Efficiency vs. Load at VOUT = 1.50V
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
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Typical Performance Characteristics
Unless otherwise specified, Auto-PWM/NPFM, VIN = 3.6V, TA = 25°C, and recommended components as specified in Table 1.
1.064
1.062
1.060
1.058
1.056
1.054
1.052
1.050
1.048
1.364
1.362
1.360
1.358
1.356
1.354
1.352
1.350
1.348
Auto PWM/NPFM
Forced PWM
Auto PWM/NPFM
Forced PWM
1
10
100
1000
1
10
100
1000
5.5
5.5
I LOAD Output Current (mA)
I LOAD Output Current (mA)
Figure 10. Load Regulation at VOUT = 1.05V
Figure 11. Load Regulation at VOUT = 1.35V
70
65
60
55
50
45
40
35
30
6.0
5.0
4.0
3.0
2.0
1.0
-
VSEL = 1.8V
VSEL = 0V
VSEL = 1.8V
VSEL = 0V
2.5
3.0
3.5
4.0
4.5
5.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VIN Input Voltage (V)
VIN Input Voltage (V)
Figure 12. Quiescent Current, ILOAD = 0, EN = 1.8V
Figure 13. Shutdown Current, ILOAD = 0, EN = 0
230
0.10%
0.05%
0.00%
-0.05%
-0.10%
210
190
170
150
130
110
90
P-Channel
N-Channel
-0.15%
VIN = 2.7V
VIN = 3.6V
-0.20%
VIN = 5.5V
70
-0.25%
-0.30%
50
30
-40
-20
0
20
40
60
80
2
2.5
3
3.5
4
4.5
5
Temperature (C)
VIN Input Voltage (V)
Figure 14. % VOUT Shift vs. Temperature (Normalized)
Figure 15. Output Stage RDS(ON) vs. VIN
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
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Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6V, VOUT = 1.35V, and load step tR = tF < 100ns.
Load Transient Response
Figure 16. 50mA to 400mA to 50mA, Forced PWM
Figure 17. 50mA to 400mA to 50mA, Auto PWM/NPFM
Figure 18. 400mA to 750mA to 400mA, Auto PWM/NPFM
Figure 19. 0mA to 125mA to 0mA, Auto PWM/NPFM
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
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Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6V.
VSEL Transitions
Figure 20. Single-Step, RLOAD = 6.2Ω
Figure 21. Single-Step, RLOAD = 6.2Ω
Figure 22. Single-Step, RLOAD = 50Ω
Figure 23. Single-Step, RLOAD = 50Ω
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
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Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6V.
VSEL Transitions
Figure 24. Single-Step from Forced PWM (MODE1=0),
RLOAD = 50Ω
Figure 25. Single Step, RLOAD = 6.2Ω
Figure 26. Single–Step from Auto PWM/PFM (MODE1=1),
RLOAD = 50Ω
© 2008 Fairchild Semiconductor Corporation
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Typical Performance Characteristics (Continued)
RLOAD is switched with N-channel MOSFET from VOUT to GND. VIN = 3.6V, initial VOUT = 1.35V, initial ILOAD = 0mA.
Short Circuit and Over-Current Fault Response
Figure 27. Metallic Short Applied at VOUT
Figure 28. Metallic Short Applied at VOUT
Figure 29. RLOAD = 660mΩ
Figure 30. RLOAD = 660mΩ
© 2008 Fairchild Semiconductor Corporation
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15
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Typical Performance Characteristics (Continued)
Unless otherwise specified, VIN = 3.6V.
Figure 31. SW-Node Jitter (Infinite Persistence),
Figure 32. SW-Node Jitter, External Synchronization
(Infinite Persistence), ILOAD = 200mA
I
LOAD = 200mA
70
60
IOUT=500mA
50
IOUT=150mA
IOUT=20mA
40
30
20
10
-
(10)
0.1
1.0
10.0
100.0
1,000.0
Frequency (KHz)
Figure 34. VIN Ripple Rejection (PSRR)
Figure 33. Soft-Start, RLOAD = 50Ω
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
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Circuit Description
Overview
Power-up, EN, and Soft-start
The FAN5355 is a synchronous buck regulator that typically
operates at 3MHz with moderate to heavy load currents. At
light load currents, the converter operates in power-saving
PFM mode. The regulator automatically transitions between
fixed-frequency PWM and variable-frequency PFM mode to
maintain the highest possible efficiency over the full range of
load current.
All internal circuits remain de-biased and the IC is in a very
low quiescent current state until the following are true:
1.
VIN is above its rising UVLO threshold, and
2. EN is HIGH.
At that point, the IC begins a soft-start cycle, its I2C interface is
enabled, and its registers loaded with their default values.
The FAN5355 uses a very fast non-linear control architecture
to achieve excellent transient response with minimum-sized
external components.
The FAN5355 integrates an I2C-compatible interface, allowing
transfers up to 3.4Mbps. This communication interface can be
used to:
During the initial soft-start, VOUT ramps linearly to the setpoint
programmed in the VSEL register selected by the VSEL pin.
The soft start features a fixed output voltage slew rate of
18.75V/ms, and achieves regulation approximately 90μs after
EN rises. PFM mode is enabled during soft-start until the
output is in regulation, regardless of the MODE bit settings.
This allows the regulator to start into a partially charged output
without discharging it; in other words, the regulator does not
allow current to flow from the load back to the battery.
1. Dynamically re-program the output voltage in 12.5mV
increments.
2. Reprogram the mode of operation to enable or disable
PFM mode.
As soon as the output has reached its setpoint, the control
forces PWM mode for about 85μs to allow all internal control
circuits to calibrate.
3. Control voltage transition slew rate.
4. Control the frequency of operation by synchronizing to an
external clock.
Symbol
Description
Value (μs)
Time from EN to start of
soft-start ramp
5. Enable / disable the regulator.
For more details, refer to the I2C Interface and Register
Description sections.
tSSDLY
25
Opt 06
Others
16 +(VSEL–0.7) X 53
(VSEL–0.1) X 53
VOUT ramp start to
regulation
tREG
PWROK (CONTROL2[5])
rising from tREG
tPOK
tCAL
11
10
Output Voltage Programming
Regulator stays in PWM
mode during this time
Option VOUT Equation
00, 02,
03
VOUT = 0.75 + NVSEL •12.5mV
(1)
Table 2. Soft-Start Timing (see Figure 35)
VOUT = 0.100 + NVSEL • 25mV
for NVSEL = 0 to 23
EN
TREG
07
(2)
(3)
VSEL
VOUT = 0.675 +
for NVSEL > 23
NVSEL − 23 •12.5mV
TSSDLY
VOUT
TCAL (FPWM)
VOUT = 1.1875 + NVSEL •12.5mV
06
0
TPOK
PWROK
where NVSEL is the decimal value of the setting of the VSEL
register that controls VOUT
.
Figure 35. Soft-start Timing
Note:
13. Option 02 maximum voltage is 1.4375V (see Table 3).
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
17
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VSEL
Dec Hex
VSEL
Dec Hex VOUT
VSEL Value
Dec Binary Hex
VOUT
02
VOUT
0.1000
0.1250
0.1500
0.1750
0.2000
0.2250
0.2500
0.2750
0.3000
0.3250
0.3500
0.3750
0.4000
0.4250
0.4500
0.4750
0.5000
0.5250
0.5500
0.5750
0.6000
0.6250
0.6500
0.6750
0.6875
0.7000
0.7125
0.7250
0.7375
0.7500
0.7625
0.7750
0.7875
0.8000
0.8125
0.8250
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
00, 03
0.7500
0.7625
0.7750
0.7875
0.8000
0.8125
0.8250
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
06
0
1
2
3
4
5
6
7
8
9
00
01
02
03
04
05
06
07
08
09
64 00
65 01
66 02
67 03
68 04
69 05
70 06
71 07
72 08
73 09
74 0A
75 0B
76 0C
77 0D
78 0E
79 0F
80 10
81 11
82 12
83 13
84 14
85 15
86 16
87 17
88 18
89 19
90 1A
91 1B
92 1C
93 1D
94 1E
95 1F
96 20
97 21
98 22
99 23
100 24
101 25
102 26
103 27
104 28
105 29
106 2A
107 2B
108 2C
109 2D
110 2E
111 2F
112 30
113 31
114 32
115 33
116 34
117 35
118 36
119 37
120 38
121 39
122 3A
123 3B
124 3C
125 3D
126 3E
127 3F
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
1.6125
1.6250
1.6375
1.6500
1.6625
1.6750
1.6875
1.7000
1.7125
1.7250
1.7375
1.7500
1.7625
1.7750
1.7875
1.8000
1.8125
1.8250
1.8375
1.8500
1.8625
1.8750
1.8875
1.9000
1.9125
1.9250
1.9375
1.9500
1.9625
1.9750
0
1
2
3
4
5
6
7
8
9
000000 00
000001 01
000010 02
000011 03
000100 04
000101 05
000110 06
000111 07
001000 08
001001 09
0.7500
0.7625
0.7750
0.7875
0.8000
0.8125
0.8250
0.8375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4375
1.4375
1.4375
1.4375
1.4375
1.4375
1.4375
1.4375
1.1875
1.2000
1.2125
1.2250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
1.6125
1.6250
1.6375
1.6500
1.6625
1.6750
1.6875
1.7000
1.7125
1.7250
1.7375
1.7500
1.7625
1.7750
1.7875
1.8000
1.8125
1.8250
1.8375
1.8500
1.8625
1.8750
1.8875
1.9000
1.9125
1.9250
1.9375
1.9500
1.9625
1.9750
10 0A
11 0B
12 0C
13 0D
14 0E
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
25 19
26 1A
27 1B
28 1C
29 1D
30 1E
31 1F
32 20
33 21
34 22
35 23
36 24
37 25
38 26
39 27
40 28
41 29
42 2A
43 2B
44 2C
45 2D
46 2E
47 2F
48 30
49 31
50 32
51 33
52 34
53 35
54 36
55 37
56 38
57 39
58 3A
59 3B
60 3C
61 3D
62 3E
63 3F
10 001010 0A
11 001011 0B
12 001100 0C
13 001101 0D
14 001110 0E
15 001111 0F
16 010000 10
17 010001 11
18 010010 12
19 010011 13
20 010100 14
21 010101 15
22 010110 16
23 010111 17
24 011000 18
25 011001 19
26 011010 1A
27 011011 1B
28 011100 1C
29 011101 1D
30 011110 1E
31 011111 1F
32 100000 20
33 100001 21
34 100010 22
35 100011 23
36 100100 24
37 100101 25
38 100110 26
39 100111 27
40 101000 28
41 101001 29
42 101010 2A
43 101011 2B
44 101100 2C
45 101101 2D
46 101110 2E
47 101111 2F
48 110000 30
49 110001 31
50 110010 32
51 110011 33
52 110100 34
53 110101 35
54 110110 36
55 110111 37
56 111000 38
57 111001 39
58 111010 3A
59 111011 3B
60 111100 3C
61 111101 3D
62 111110 3E
63 111111 3F
Table 3. VSEL vs. VOUT for Options 00, 02, 03, 06
Table 4. VSEL vs. VOUT for Option 07
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
18
www.fairchildsemi.com
“create demand” for a pulse if no pulse had been required
for 40μs. The minimum frequency limit circuit takes effect
with load currents below about 3.5mA. Above that load
point, the natural PFM period is less than 40μs. This circuit
only activates when ILOAD is greater than ~3.5mA. If the load
remains above 3.5mA, there is no quiescent current penalty
for EPFM mode and there is some accuracy advantage.
Software Enable
The EN_DCDC bit, VSELx[7] can be used to enable the
regulator in conjunction with the EN pin. Setting EN_DCDC
with EN HIGH begins the soft-start sequence described
above.
EN_DCDC Bit
EN Pin
I2C
REGULATOR
NPFM allows the switching frequency (fSW) to go as low as
required to support the load current. This achieves a lower
quiescent current than EPFM, but sacrifices up to ±15mV of
DC accuracy when compared to EPFM or PWM modes. As
shown in Table 6, EPFM and NPFM modes have the same
frequency when the load is above 4mA. If the load is above
4mA, EPFM is the preferred mode, since it has tighter DC
regulation with the same efficiency.
0
1
1
0
0
1
0
1
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
Table 5. EN_DCDC Behavior
Light-Load (PFM) Operation
EPFM can only be enabled by setting the MODE_CTRL
bits to 11. In versions with MODE_CTRL disabled (see
Table 12), the PFM mode is NPFM.
The FAN5355 offers both a Normal PFM (NPFM) and
Enhanced PFM (EPFM) mode. NPFM is normally used
when the load current is very low and when quiescent
current must be minimized. EPFM provides more accurate
DC regulation and limits the minimum frequency to 25kHz
typical to prevent operation in the audio band.
Mode
EPFM
NPFM
IQUIESCENT typical at ILOAD = 0
DC Accuracy
110μA
Better
38μA
Good
VOUT ripple is identical in both modes (less than 20mV), and
both modes feature very fast response to load transients.
fSW at ILOAD = 0
25 kHz
> 33 kHz
to 0 Hz
> 33 kHz
fSW at ILOAD > 3.5mA
The FAN5355 incorporates
modulation that ensures:
a single-pulse, light-load
Table 6. PFM Modes Comparison
PFM mode can be disabled by writing to the mode control
bits: CONTROL1[3:0] (see Table 12 for details).
Smooth transitions between PFM and PWM modes
Minimum frequency, of 25kHz typical, to avoid audible
Switching Frequency Control and
Synchronization
The nominal internal oscillator frequency is 3MHz. The
regulator runs at its internal clock frequency until these
conditions are met:
noise (EPFM only)
Single-pulse operation for low ripple
Predictable PFM entry and exit currents.
PFM begins after the inductor current has become
discontinuous, crossing zero during the PWM cycle in 32
consecutive cycles. PFM exit occurs when discontinuous
current mode (DCM) operation cannot supply sufficient
current to maintain regulation. During PFM mode, the
inductor current ripple is about 40% higher than in PWM
mode. The load current required to exit PFM mode is
thereby about 20% higher than the load current required to
enter PFM mode, providing sufficient hysteresis to prevent
“mode chatter.”
1. EN_SYNC bit, CONTROL1[5], is set; and
2. A valid frequency appears on the SYNC pin.
CONTROL2
FSYNC Valid
PLL_MULT fSYNC Divider
Min.
2.25
1.13
0.75
0.56
Typ.
3.00
1.50
1.00
0.75
Max.
4.00
2.00
1.33
1.00
00
01
10
11
1
2
3
4
While PWM ripple voltage is typically less than 4mVP-P,
PFM ripple voltage can be up to 30mVP-P during very light
load. To prevent significant undershoot when a load
transient occurs, the initial DC setpoint for the regulator in
PFM mode is set 10mV higher than in PWM mode. This
offset decays to about 5mV after the regulator has been in
PFM mode for ~100μs. The maximum instantaneous
voltage in PFM is 30mV above the setpoint.
Table 7.SYNC Frequency Validation for fOSC(INTERNAL)=3.0MHz
If the EN_SYNC is set and SYNC fails validation, the
regulator continues to run at its internal oscillator frequency.
The regulator is functional if fSYNC is valid, as defined in
Table 7, but its performance is compromised if fSYNC is
outside the fSYNC window in the Electrical Specifications.
In Enhanced PFM (EPFM) mode, the regulator maintains a
minimum frequency of 25kHz (typical) to prevent audible
noise being generated by the external components. To
achieve this, the regulator turns on the low-side MOSFET to
When CONTROL1[3:2] = 00 and the VSEL line is LOW, the
converter operates according to the MODE0 bit,
CONTROL1[0], with synchronization disabled regardless of
the state of the EN_SYNC and HW_nSW bits.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
19
www.fairchildsemi.com
setpoint and is typically 7μs for a full-range transition (from
00000 to 11111 for 6-bit DAC options). The PWROK bit,
CONTROL2[5], goes LOW until the transition is complete
Output Voltage Transitions
The IC regulates VOUT to one of two setpoint voltages, as
determined by the VSEL pin and the HW_nSW bit.
and VOUT settled. This typically occurs ~2μs after tV(L-H)
.
VSEL Pin HW_nSW Bit VOUT Setpoint(14)
PFM
It is good practice to reduce the load current before making
positive VSEL transitions. This reduces the time required to
make positive load transitions and avoids current–limit-
induced overshoot.
0
1
x
1
1
0
VSEL0
VSEL1
VSEL1
Allowed
Per MODE1
Per MODE1
tV(L-H)
Table 8. VOUT Setpoint and Mode Control MODE_CTRL,
CONTROL1[3:2] = 00
VHIGH
98% VHIGH
Note:
14. Option 07 uses VSELx[6:0] to set VOUT, while all other
options use VSELx[5:0].
VOUT
VLOW
If HW_nSW =0, VOUT transitions are initiated through the
following sequence:
VSEL
1. Write the new setpoint in VSEL1.
tPOK(L-H)
PWROK
2. Write desired transition rate in DEFSLEW,
CONTROL2[2:0], and set the GO bit in CONTROL2[7].
Figure 37. Single-Step VOUT Transition
If HW_nSW =1, VOUT transitions are initiated either by
changing the state of the VSEL pin or by writing to the VSEL
register selected by the VSEL pin.
All positive VOUT transitions inhibit PFM until the transition is
complete, which occurs at the end of tPOK(L-H)
.
Positive Transitions
When transitioning to a higher VOUT, the regulator can
perform the transition using multi-step or single-step mode.
Negative Transitions
When moving from VSEL=1 to VSEL=0, the regulator
enters PFM mode, regardless of the condition of the SYNC
pin or MODE bits, and remains in PFM until the transition is
completed. Reverse current through the inductor is blocked,
and the PFM minimum frequency control inhibited, until the
new setpoint is reached, at which time the regulator
resumes control using the mode established by
MODE_CTRL. The transition time from VHIGH to VLOW is
controlled by the load current and output capacitance as:
Multi-step Mode:
The internal DAC is stepped at a rate defined by
DEFSLEW, CONTROL2[2:0], ranging from 000 to 110. This
mode minimizes the current required to charge COUT and
thereby minimizes the current drain from the battery when
transitioning. The PWROK bit, CONTROL2[5], remains
LOW until about 1.5μs after the DAC completes its ramp.
VHIGH − VLOW
VHIGH
tV(H−L) = COUT
•
(4)
ILOAD
VHIGH
VOUT
VLOW
VSEL
VOUT
VSEL
tPOK(L-H)
VLOW
tV(L-H)
PWROK
Figure 36. Multi-step VOUT Transition
Single-step Mode:
tPOK(L-H)
PWROK
Used if DEFSLEW, CONTROL2[2:0] = 111. The internal
DAC is immediately set to the higher voltage and the
regulator performs the transition as quickly as its current
limit circuit allows, while avoiding excessive overshoot.
Figure 38. Negative VOUT Transition
Figure 37 shows single-step transition timing. tV(L-H) is the
time it takes the regulator to settle to within 2% of the new
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
20
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Slave Address
Protection Features
In Table 10, A1 and A0 are according to the Ordering
Information table on page 2.
Current Limit / Auto-Restart
The regulator includes cycle-by-cycle current limiting, which
prevents the instantaneous inductor current from exceeding
~1350mA.
7
6
5
4
3
2
1
0
1
0
0
1
0
A1
A0
R/W
The IC enters “fault” mode after sustained over-current. If
current limit is asserted for more than 32 consecutive cycles
(about 20μs), the IC returns to shutdown state and remains
in that condition for ~80μs. After that time, the regulator
attempts to restart with a normal soft-start cycle. If the fault
has not cleared, it shuts down ~10μs later.
Table 10. I2C Slave Address
Bus Timing
As shown in Figure 39, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
next SCL rising edge.
If the fault is a short circuit, the initial current limit is ~30% of
the normal current limit, which produces a very small drain
on the system power source.
Data change allowed
Thermal Protection
When the junction temperature of the IC exceeds 150°C,
the device turns off all output MOSFETs and remains in a
low quiescent current state until the die cools to 130°C
before commencing a normal soft-start cycle.
SDA
TH
TSU
SCL
Under-Voltage Lockout (UVLO)
The IC turns off all MOSFETs and remains in a very low
quiescent current state until VIN rises above the UVLO
threshold.
Figure 39. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a “START” condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 40.
I2C Interface
The FAN5355’s serial interface is compatible with standard,
fast, and HS mode I2C bus specifications. The FAN5355’s
SCL line is an input and its SDA line is a bi-directional open-
drain output; it can only pull down the bus when active. The
SDA line only pulls LOW during data reads and when
signaling ACK. All data is shifted in MSB (bit 7) first.
THD;STA
Slave Address
MS Bit
SDA
SCL
SDA and SCL are normally pulled up to a system I/O power
supply (VCCIO), as shown in Figure 1. If the I2C interface is
not used, SDA and SCL should be tied to AVIN to minimize
quiescent current consumption.
Figure 40. Start Bit
A transaction ends with a “STOP” condition, which is
defined as SDA transitioning from 0 to 1 with SCL HIGH, as
shown in Figure 41.
Addressing
Slave Releases
Master Drives
FAN5355 has four user-accessible registers:
tHD;STO
ACK(0) or
NACK(1)
Address
SDA
SCL
7
6
5
4
3
2
1
0
VSEL0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
VSEL1
CONTROL1
CONTROL2
Figure 41. Stop Bit
Table 9. I2C Register Addresses
During a read from the FAN5355 (Figure 44), the master
issues a “Repeated Start” after sending the register
address, and before resending the slave address. The
“Repeated Start” is a 1 to 0 transition on SDA while SCL is
HIGH, as shown in Figure 42.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
21
www.fairchildsemi.com
High-Speed (HS) Mode
Read and Write Transactions
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) modes are identical, except the bus speed
for HS mode is 3.4MHz. HS mode is entered when the bus
master sends the HS master code 00001XXX after a start
condition. The master code is sent in FS mode (less than
400kHz clock) and slaves do not ACK this transmission.
The following figures outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
Master Drives Bus
defined as
and
Slave Drives Bus
.
All addresses and data are MSB first.
The master then generates a repeated start condition
(Figure 42) that causes all slaves on the bus to switch to HS
mode. The master then sends I2C packets, as described
above, using the HS mode clock rate and timing.
Symbol Definition
S
START, see Figure 40.
ACK. The slave drives SDA to 0 to acknowledge the
preceding packet.
A
The bus remains in HS mode until a stop bit (Figure 41) is
sent by the master. While in HS mode, packets are
separated by repeated start conditions (Figure 42).
NACK. The slave sends a 1 to NACK the preceding
packet.
A
R
P
Repeated START, see Figure 42.
Slave Releases
tSU;STA
tHD;STA
STOP, see Figure 41.
ACK(0) or
NACK(1)
SLADDR
MS Bit
SDA
SCL
Table 11. I2C Bit Definitions for Figure 43 - Figure 44
Figure 42. Repeated Start Timing
0
0
0
7 bits
8 bits
8 bits
Data
S
Slave Address
0
A
Reg Addr
A
A
P
Figure 43. Write Transaction
0
0
0
1
7 bits
Slave Address
8 bits
7 bits
8 bits
Data
S
0
A
Reg Addr
A
R
Slave Address
1
A
A
P
Figure 44. Read Transaction
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
22
www.fairchildsemi.com
Register Descriptions
Default Values
Each option of the FAN5355 (see Ordering Information on page 2) has different default values for the some of the register bits.
Table 12 defines both the default values and the bit’s type (as defined in Table 13) for each available option.
VSEL0
VSEL1
Option
00
7
1
1
1
1
1
6
1
1
1
1
1
5
0
0
0
0
1
4
1
1
1
1
1
3
1
1
0
1
0
2
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
VOUT
1.05
1.05
1.00
1.05
1.80
Option
00
7
1
1
1
1
1
6
1
1
1
1
1
5
1
1
1
1
1
4
1
0
0
1
1
3
2
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
VOUT
1.35
1.20
1.20
1.35
1.80
0
0
0
0
0
02
02
03
03
07
07
06
06
CONTROL1
CONTROL2
Option
00, 02
03
7
6
0
0
0
5
0
0
0
4
1
1
1
3
0
0
0
2
0
0
0
1
0
0
0
0
0
0
0
Option
00, 02
03
7
6
0
0
0
5
0
0
0
4
0
0
0
3
2
1
1
1
1
0
1
1
1
1
0
1
0
0
0
0
0
0
1
1
1
06, 07
06, 07
Table 12. Default Values and Bit Types for VSEL and CONTROL Registers
#
#
#
Active bit. Changing this bit changes the behavior of the converter, as described below.
Disabled. Converter logic ignores changes made to this bit. Bit can be written to and read-back.
Read-only. Writing to this bit through I2C does not change the read-back value, nor does it change converter behavior.
Table 13. Bit Type Definitions for Table 12.
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
23
www.fairchildsemi.com
Bit Definitions
The following table defines the operation of each register bit. Superscript characters define the default state for each option.
Superscripts 0,2,3,6,7 signify the default values for options 00, 02, 03, 06, and 07, respectively. A signifies the default for all options.
Bit Name
VSEL0
Value Description
Register Address: 00
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL1. A write to bit 7 in either
register establishes the EN_DCDC value.
0
EN_DCDC
7
1A
Device enabled when EN pin is HIGH, disabled when EN is LOW.
Reserved 0,2,3,6
or DAC6 7
Has no effect in options 00, 02, 03, 06, and defaults to 1. In option 07, it is the MSB of the 7-bit DAC value to set
6
Table
12
VOUT
.
6-bit DAC value to set VOUT. The six LSBs of the 7-bit value for option 07.
DAC[5:0]
5:0
VSEL1
Register Address: 01
Device in shutdown regardless of the state of the EN pin. This bit is mirrored in VSEL0. A write to bit 7 in either
register establishes the EN_DCDC value.
0
EN_DCDC
7
1A
Device enabled when EN pin is HIGH, disabled when EN is LOW.
Reserved 0,2,3,6
or DAC6 7
Has no effect in options 00, 02, 03, 06, and defaults to 1. In option 07, it is the MSB of the 7-bit DAC value to set
6
Table
12
VOUT
.
6-bit DAC value to set VOUT. The six LSBs of the 7-bit value for option 07.
DAC[5:0]
5:0
CONTROL1
Register Address: 02
100,2,5,6 Vendor ID bits. Writing to these bits has no effect on regulator operation. These bits can be used to distinguish
between vendors via I2C.
7:6
5
Reserved
003
0A
Disables external signal on SYNC from affecting the regulator.
EN_SYNC
HW_nSW
When a valid frequency is detected on SYNC, the regulator synchronizes to it and PFM is disabled, except
when MODE = 00, VSEL pin = LOW, and HW_nSW = 1.
1
0
1A
00A
01
10
11
0A
1
VOUT is controlled by VSEL1. Voltage transitions occur by writing to the VSEL1, then setting the GO bit.
VOUT is programmed by the VSEL pin. VOUT = VSEL1 when VSEL is HIGH, and VSEL0 when VSEL is LOW.
Operation follows MODE0, MODE1.
4
NPFM with automatically transitions to PWM, regardless of VSEL.
3:2 MODE_CTRL
PFM disabled (forced PWM), regardless of VSEL.
EPFM (FSW(MIN) = 25kHz) with automatically transitions to PWM, regardless of VSEL.
PFM disabled (forced PWM) when regulator output is controlled by VSEL1.
NPFM with automatic transitions to PWM when regulator output is controlled by VSEL1.
1
0
MODE1
MODE0
0A
1
NPFM with automatic transitions to PWM when VSEL is LOW. Changing this bit has no effect on the operation
of the regulator.
CONTROL2
Register Address: 03
0A
1
This bit has no effect when HW_nSW = 1. At the end of a VOUT transition, this bit is reset to 0.
Starts a VOUT transition if HW_nSW = 0.
7
6
5
GO
0A
When the regulator is disabled, VOUT is not discharged.
When the regulator is disabled, VOUT discharges through an internal pull-down.
VOUT is not in regulation or is in current limit.
OUTPUT_
DISCHARGE
1
0
PWROK
(read only)
1
VOUT is in regulation.
00A
01
fSW = fSYNC when synchronization is enabled.
fSW = 2 X fSYNC when synchronization is enabled.
fSW = 3 X fSYNC when synchronization is enabled.
fSW = 4 X fSYNC when synchronization is enabled.
4:3 PLL_MULT
10
11
000
001
010
011
100
101
110
V
V
V
V
V
V
V
OUT slews at 0.15mV/μs during positive VOUT transitions.
OUT slews at 0.30mV/μs during positive VOUT transitions.
OUT slews at 0.60mV/μs during positive VOUT transitions.
OUT slews at 1.20mV/μs during positive VOUT transitions.
OUT slews at 2.40mV/μs during positive VOUT transitions.
OUT slews at 4.80mV/μs during positive VOUT transitions.
OUT slews at 9.60mV/μs during positive VOUT transitions.
2:0 DEFSLEW
111A Positive VOUT transitions use single-step mode (see Figure 37).
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
24
www.fairchildsemi.com
Physical Dimensions
BALL A1
INDEX AREA
E
A
0.50
B
D
(Ø0.25)
Cu PAD
0.03 C
1.00
A1
2X
(Ø0.35)
0.50
SOLDER MASK
OPENING
0.03 C
TOP VIEW
2X
RECOMMENDED LAND PATTERN (NSMD)
0.06 C
0.332±0.018
0.250±0.025
0.625
0.539
0.05 C
D
C
SEATING PLANE
SIDE VIEWS
(X)+/-.018
0.005
12 X Ø0.315 +/- .025
C A B
0.50
A. NO JEDEC REGISTRATION APPLIES
B. DIMENSIONS ARE IN MILLIMETERS.
D
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C
B
A
0.50
D
DATUM C, THE SEATING PLANE, IS DEFINED
BY THE SPHERICAL CROWNS OF THE BALLS.
(Y)+/-.018
F
FOR DIMENSIONS D, E, X, AND Y SEE
PRODUCT DATASHEET.
1
2
3
F. BALL COMPOSITION: Sn95.5Ag3.9Cu0.6
SAC405 ALLOY
BOTTOM VIEW
G. DRAWING FILENAME: MKT-UC012AArev2
Figure 45. 12-Bump WLCSP, 0.5mm Pitch
Product-Specific Dimensions
Product
D
E
X
Y
FAN5355UC
2.230 +/-0.030
1.460 +/-0.030
0.230
0.365
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
25
www.fairchildsemi.com
Physical Dimensions
10
6
3.0
A
B
0.10 C
2.25
2.40
2.00
2X
3.0
0.23
0.10 C
0.50
0.02
0.25
2X
D
1
5
TOP VIEW
0.8 MAX
0.10
C
RECOMMENDED LAND PATTERN
(0.20)
0.08 C
0.05
0.00
C
SEATING
PLANE
SIDE VIEW
±0.10
(3.00
)
2.40
(0.38)
PIN #1 IDENT
5
1
±0.10
(3.00
)
1.40
0.55±0.10
E
0.30
0.20
10
6
0.5
0.10
0.05
C A B
C
2.0
BOTTOM VIEW
A. CONFORMS TO JEDEC REGISTRATION MO-229,
VARIATION WEED-5 EXCEPT WHERE NOTED
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. LAND PATTERN DIMENSIONS ARE NOMINAL
REFERENCE VALUES ONLY
E. NOT COMPLIANT
MLP10ArevB
Figure 46. 10-pin, 3x3mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
26
www.fairchildsemi.com
© 2008 Fairchild Semiconductor Corporation
FAN5355 • Rev. 1.0.4
27
www.fairchildsemi.com
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