FAN6754WAMRMY [FAIRCHILD]
Highly Integrated Green-Mode PWM Controller Brownout and VLimit Adjustment by HV Pin; 高度集成绿色模式PWM控制器掉电及平上限调整通过HV引脚
| 型号： | FAN6754WAMRMY |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Highly Integrated Green-Mode PWM Controller Brownout and VLimit Adjustment by HV Pin |
| 文件： | 总15页 (文件大小：961K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Febuary 2013
FAN6754WA
Highly Integrated Green-Mode PWM Controller
Brownout and VLimit Adjustment by HV Pin
Features
Description
The highly integrated FAN6754WA PWM controller
provides several features to enhance the performance
of flyback converters. To minimize standby power
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High-Voltage Startup
AC Input Brownout Protection with Hysteresis
Monitor HV to Adjust VLimit
consumption,
a
proprietary Green-Mode function
provides off-time modulation to continuously decrease
the switching frequency under light-load conditions.
Low Operating Current: 1.5 mA
Linearly Decreasing PWM Frequency to 22 kHz
Frequency Hopping to Reduce EMI Emission
Fixed PWM Frequency: 65 kHz
Under zero-load and very light-load conditions,
FAN6754WA saves PWM pulses by entering "deep"
Burst Mode. Burst Mode enables the power supply to
meet international power conservation requirements.
Peak-Current-Mode Control
FAN6754WA also integrates
a
frequency-hopping
function that helps reduce EMI emission of a power
supply with minimum line filters. The built-in
synchronized slope compensation helps achieve stable
peak-current control. To keep constant output power
limit over universal AC input range, the current limit is
adjusted according to AC line voltage detected by the
HV pin. The gate output is clamped at 13 V to protect
the external MOSFET from over-voltage damage.
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Internal Open-Loop Protection
GATE Output Maximum Voltage Clamp: 13 V
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP)
Programmable Over-Temperature Protection (OTP)
Internal Latch Circuit (OVP, OTP)
Other protection functions include AC input brownout
protection with hysteresis, sense pin short-circuit
protection, and VDD over-voltage protection. For over-
temperature protection, an external NTC thermistor can
be applied to sense the external switcher’s temperature.
When VDD OVP or OTP are activated, an internal latch
circuit is used to latch-off the controller. The Latch Mode
is reset when the VDD supply is removed.
Open-Loop Protection (OLP); Restart for
FAN6754WAMRMY, Latch for FAN6754WAMLMY
.
.
SENSE Short-Circuit Protection (SSCP)
Built-in 8 ms Soft-Start Function
FAN6754WA is available in an 8-pin SOP package.
Applications
General-purpose switch-mode power supplies (SMPS)
and flyback power converters, including:
.
Power Adapters
Ordering Information
Operating
Temperature Range
Part Number
Package
Packing Method
FAN6754WAMRMY
FAN6754WAMLMY
-40 to +105°C
8-Pin, Small Outline Package (SOP)
Tape & Reel
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
1
www.fairchildsemi.com
Application Diagram
Figure 1. Typical Application
Internal Block Diagram
Figure 2. Functional Block Diagram
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
2
Marking Information
F - Fairchild Logo
Z - Plant Code
X - 1-Digit Year Code
Y - 1-Digit Week Code
TT - 2-Digit Die Run Code
T - Package Type (M=SOP)
P - Y: Package (Green)
M - Manufacture Flow Code
ZXYTT
6754MR
WATPM
ZXYTT
6754ML
WATPM
Figure 3. Top Mark
Pin Configuration
SOP-8
GND
FB
1
2
3
4
8
7
6
5
GATE
VDD
SENSE
RT
NC
HV
Figure 4. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
Ground. This pin is used for the ground potential of all the pins. A 0.1 µF decoupling capacitor
placed between VDD and GND is recommended.
1
GND
Feedback. The output voltage feedback information from the external compensation circuit is fed
into this pin. The PWM duty cycle is determined by this pin and the current-sense signal from Pin
6. FAN6754WA performs open-loop protection (OLP); if the FB voltage is higher than a threshold
voltage (around 4.6 V) for more than 56 ms, the controller latches off the PWM.
2
3
4
FB
NC
HV
No Connection
High-Voltage Startup. This pin is connected to the line input via a 1N4007 and 200 k resistor
to achieve brownout and high/low line compensation. Once the voltage on the HV pin is lower
than the brownout voltage, PWM output turns off. High/low line compensation dominates the
cycle-by-cycle current limiting to achieve constant output power limiting with universal input.
Over-Temperature Protection. An external NTC thermistor is connected from this pin to GND.
The impedance of the NTC decreases at high temperatures. Once the voltage on the RT pin
drops below the threshold voltage, the controller latches off the PWM. If RT pin is not connected
to an NTC resistor for Over-Temperature Protection, a 100 k resistor is recommend to connect
the RT pin to the GND pin. This pin is limited by an internal clamping circuit.
5
RT
Current Sense. This pin is used to sense the MOSFET current for the current-mode PWM and
current limiting.
6
7
8
SENSE
VDD
Supply Voltage. IC operating current and MOSFET driving current are supplied using this pin.
This pin is connected to an external bulk capacitor of typically 47 µF. The threshold voltages for
turn-on and turn-off are 17 V and 10 V, respectively. The operating current is lower than 2 mA.
Gate Drive Output. The totem-pole output driver for the power MOSFET. It is internally clamped
below 13 V.
GATE
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VVDD
VFB
Parameter
Min.
Max.
30
Unit
V
DC Supply Voltage(1,2)
FB Pin Input Voltage
-0.3
-0.3
-0.3
7.0
V
VSENSE
VRT
SENSE Pin Input Voltage
RT Pin Input Voltage
7.0
V
7.0
V
VHV
HV Pin Input Voltage
500
400
150
+125
+150
+260
V
Power Dissipation (TA＜50°C)
PD
mW
Thermal Resistance (Junction-to-Air)
Operating Junction Temperature
Storage Temperature Range
JA
TJ
C/W
C
-40
-55
TSTG
TL
C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
Human Body Model;
C
5000
2000
JESD22-A114
Electrostatic Discharge Capability,
All Pins Except HV Pin
ESD
V
Charged Device Model;
JESD22-C101
Notes:
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD with HV pin: CDM=1250 V and HBM=500 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
RHV
HV Startup Resistor
150
200
250
k
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
4
Electrical Characteristics
VDD=15 V and TA=25C unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VDD Section
VOP
Continuously Operating Voltage
24
18
11
7.5
V
V
V
V
VDD-ON Start Threshold Voltage
VDD-OFF Minimum Operating Voltage
VDD-OLP IDD-OLP Off Voltage
16
9
17
10
5.5
6.5
Threshold Voltage on VDD Pin for
VDD-LH
3.5
4.0
4.5
V
Latch-Off Release Voltage
Threshold Voltage on VDD Pin for
VDD-AC Disable AC Recovery to Avoid
Startup Failed
VDD-OFF
+2.8
VDD-OFF
+3.3
VDD-OFF
+3.8
V
IDD-ST
Startup Current
VDD-ON – 0.16 V
30
µA
Operating Supply Current,
PWM Operation
VDD=20 V, FB=3 V Gate
Open
IDD-OP1
1.5
1.0
2.0
mA
Operating Supply Current,
Gate Stop
IDD-OP2
VDD=20 V, FB=3 V
1.5
90
mA
µA
Operating Current at PWM-Off
Phase Under Latch-Off
Conduction
ILH
VDD=5 V
30
60
Internal Sink Current Under Latch-
Off Conduction
IDD-OLP
170
24
200
25
230
26
µA
V
VDD-OLP+0.1 V
VDD-OVP VDD Over-Voltage Protection
V
DD Over-Voltage Protection
tD-VDDOVP
75
165
255
µs
Debounce Time
HV Section
VAC=90 V(VDC=120 V),
VDD=0 V
IHV
Supply Current from HV Pin
Leakage Current after Startup
2.0
3.5
1
5.0
20
mA
µA
HV=700 V, VDD=VDD-
OFF+1 V
IHV-LC
DC Source Series
R=200 k to HV Pin
See Equation 1
VAC-OFF Brown-out Threshold
VAC-ON Brown-in Threshold
92
102
112
V
V
DC Source Series
R=200 kΩ to HV Pin
See Equation 2
104
6
114
12
124
18
DC Source Series
R=200 kΩ to HV Pin
VAC-ON - VAC-OFF
V
VAC
FB > VFB-N
FB < VFB-G
220
650
20
tS-CYCLE Line Voltage Sample Cycle
tH-TIME Line Voltage Hold Period
µs
µs
ms
ms
FB > VFB-N
FB < VFB-G
65
75
85
tD-AC-OFF PWM Turn-off Debounce Time
180
235
290
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
5
Figure 5. Brownout Circuit
Figure 6. Brownout Behavior
Figure 7. VDD-AC and AC Recovery
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
6
Electrical Characteristics (Continued)
VDD=15 V and TA=25C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
Oscillator Section
61
±3.7
12.0
19
65
±4.2
13.5
22
69
±4.7
15.0
25
Center Frequency
Hopping Range
fOSC
Frequency in Normal Mode
kHz
tHOP
fOSC-G
fDV
Hopping Period
ms
kHz
%
Green-Mode Frequency
Frequency Variation vs. VDD Deviation
VDD=11 V to 22 V
5
fDT
Frequency Variation vs. Temperature Deviation
5
%
TA=-40 to +105C
Feedback Input Section
AV
Input Voltage to Current-Sense Attenuation
Input Impedance
1/4.5
14
1/4.0
16
1/3.5
18
V/V
kΩ
V
ZFB
VFB-OPEN Output High Voltage
FB Pin Open
4.8
4.3
50
5.0
4.6
56
5.2
4.9
62
VFB-OLP FB Open-Loop Trigger Level
V
tD-OLP
Delay Time of FB Pin Open-Loop Protection
ms
Pin, FB Voltage
2.6
±3.7
2.1
2.8
±4.2
2.3
3.0
±4.7
2.5
V
kHz
V
(FB=VFB-N
)
VFB-N
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
Hopping Range
Pin, FB Voltage
(FB=VFB-G
)
VFB-G
Hopping Range
±1.27
1.9
±1.45 ±1.62 kHz
VFB-ZDCR FB Threshold Voltage for Zero-Duty Recovery
VFB-ZDC FB Threshold Voltage for Zero-Duty
2.1
2.0
2.3
2.2
V
V
1.8
Continued on the following page…
PWM Frequency
fOSC
fOSC-G
VFB-ZDC VFB-ZDCR
VFB-G
VFB-N
VFB
Figure 8. VFB vs. PWM Frequency
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
7
Electrical Characteristics (Continued)
VDD=15 V and TA=25C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
Current-Sense Section
tPD
Delay to Output
100
280
250
330
ns
ns
tLEB
Leading-Edge Blanking Time
230
VDC=122 V, Series
R=200 k to HV
VLimit-L
Current Limit at Low Line (VAC=86 V)
0.43
0.46
0.39
0.49
0.42
V
V
VDC=366 V, Series
R=200 kΩ to HV
VLimit-H
VSSCP
Current Limit at High Line (VAC=259 V)
0.36
Threshold Voltage for Sense Short-Circuit Protection
0.03
4.0
60
0.05
4.4
120
8
0.07
4.8
180
9
V
tON-SSCP On Time for VSSCP Checking
µs
µs
ms
tD-SSCP Delay for Sense Short-Circuit Protection
VSENSE<0.05 V
tSS
Soft-Start Time
Startup Time
7
GATE Section
DCYMAX Maximum Duty Cycle
VGATE-L Gate Low Voltage
86
89
92
%
V
1.5
VDD=15 V, IO=50 mA
VDD=12 V, IO=50 mA
VDD=15 V
VGATE-H Gate High Voltage
IGATE-SINK Gate Sink Current(4)
8
V
300
mA
IGATE-
SOURCE
Gate Source Current(4)
250
mA
VDD=15 V, GATE=6 V
tr
tf
ns
ns
Gate Rising Time
Gate Falling Time
VDD=15 V, CL=1 nF
VDD=15 V, CL=1 nF
100
50
VGATE-
CLAMP
V
µA
V
Gate Output Clamping Voltage
V
DD=22 V
9
13
17
RT Section
IRT
Output Current from RT Pin
92
100
108
0.7 V ＜ VRT ＜ 1.05 V, after
12 ms Latch Off
VRTTH1
VRTTH2
1.000 1.035 1.070
Over-Temperature Protection Threshold
Voltage
V
RT ＜ 0.7 V, After 100 µs
Latch Off
RTTH2 ＜ VRT ＜ VRTTH1
FB > VFB-N
RTTH2 ＜ VRT ＜ VRTTH1
FB < VFB-G
RT< VRTTH2, FB > VFB-N
0.65
14
0.70
16
0.75
18
V
tD-OTP1
ms
µs
V
40
51
62
Over-Temperature Latch-Off Debounce
V
110
320
185
605
260
890
tD-OTP2
VRT< VRTTH2, FB < VFB-G
Note:
4. Guaranteed by design.
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
8
Typical Performance Characteristics
Figure 10. Operation Supply Current (IDD-OP1
vs. Temperature
)
Figure 9. Startup Current (IDD-ST) vs. Temperature
Figure 11. Start Threshold Voltage (VDD-ON
)
Figure 12. Minimum Operating Voltage (VDD-OFF
vs. Temperature
)
vs. Temperature
Figure 13. Supply Current Drawn from HV Pin (IHV
vs. Temperature
)
Figure 14. HV Pin Leakage Current After Startup
(IHV-LC) vs. Temperature
Figure 15. Frequency in Normal Mode (fOSC
)
Figure 16. Maximum Duty Cycle (DCYMAX
vs. Temperature
)
vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
9
Typical Performance Characteristics (Continued)
Figure 17. FB Open-Loop Trigger Level (VFB-OLP
vs. Temperature
)
Figure 18. Delay Time of FB Pin Open-Loop
Protection (tD-OLP) vs. Temperature
Figure 19. VDD Over-Voltage Protection (VDD-OVP
vs. Temperature
)
Figure 20. Output Current from RT Pin (IRT
vs. Temperature
)
Figure 21. Over-Temperature Protection Threshold
Voltage (VRTTH1) vs. Temperature
Figure 22. Over-Temperature Protection Threshold
Voltage (VRTTH2) vs. Temperature
Figure 23. Brownin (VAC-ON) vs. Temperature
Figure 24. Brownout (VAC-OFF) vs. Temperature
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
10
Functional Description
Startup Current
Gate Output / Soft Driving
For startup, the HV pin is connected to the line input
through an external diode and resistor; RHV, (1N4007 /
200 kΩ recommended). Peak startup current drawn
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
13 V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
from the HV pin is (VAC× 2 ) / RHV and charges the hold-
up capacitor through the diode and resistor. When the
VDD capacitor level reaches VDD-ON, the startup current
switches off. At this moment, the VDD capacitor only
supplies the FAN6754WA to keep the VDD until the
auxiliary winding of the main transformer provides the
operating current.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 8ms soft-start
circuit significantly reduces the startup current spike and
output voltage overshoot.
Operating Current
Operating current is around 1.5 mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
FAN6754WA inserts a synchronized, positive-going,
ramp at every switching cycle.
Green-Mode Operation
The proprietary Green-Mode function provides off-time
modulation to reduce the switching frequency in light-
load and no-load conditions. VFB, which is derived from
the voltage feedback loop, is taken as the reference.
Once VFB is lower than the threshold voltage (VFB-N), the
switching frequency is continuously decreased to the
minimum Green-Mode frequency of around 22 kHz.
Constant Output Power Limit
When the SENSE voltage across sense resistor RSENSE
reaches the threshold voltage, around 0.46 V for low-
line condition, the output GATE drive is turned off after a
small delay, tPD. This delay introduces an additional
current proportional to tPD • VIN / LP. Since the delay is
nearly constant, regardless of the input voltage VIN,
higher input voltage results in larger additional power.
Therefore, the maximum output power at high line is
higher than that of low line. To compensate this
variation for a wide AC input range, a power-limiter is
controlled by the HV pin to solve the unequal power-limit
problem. The power limiter is fed to the inverting input of
the current limiting comparator. This results in a lower
current limit at high-line inputs than at low-line inputs.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current-sense signal and VFB, the feedback voltage.
When the voltage on the SENSE pin reaches around
VCOMP = (VFB–0.6)/4, the switch cycle is terminated
immediately. VCOMP is internally clamped to a variable
voltage around 0.46 V for low-line output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Brownout and Constant Power Limited by
the HV Pin
Unlike previous PWM controllers, the FAN6754WA HV
pin can detect the AC line voltage to perform brownout
protection and line compensation for power limit. Using
a fast diode and startup resistor to sample the AC line
voltage, the peak value refreshes and is stored in a
register at each sampling cycle. When internal update
time is met, this peak value is used for brownout and
current-limit level judgment. Equation (1) and (2)
calculate the level of brown-in or brownout converted to
RMS value. For power saving, FAN6754WA enlarges
the sampling cycle to lower the power loss from HV
sampling at light-load condition.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
17V and 10V, respectively. During startup, the hold-up
capacitor must be charged to 17 V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply VDD until the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 10 V during startup. This
UVLO hysteresis window ensures that hold-up capacitor
is adequate to supply VDD during startup.
(RHV 1.6)
VAC-ON (RMS) ( 0.9V
) / 2
(1)
(2)
1.6
(RHV 1.6)
VAC-OFF (RMS)( 0.81V
) / 2
1.6
where RHV is in k.
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
11
The HV pin can perform current limit to shrink the
tolerance of Over-Current Protection (OCP) under full
range of AC voltage, to linearly current limit curve, as
shown in Figure 25. FAN6754WA also shrinks the Vlimit
level by half to lower the I2RSENSE loss to increase the
heavy-load efficiency.
Thermal Protection
An NTC thermistor, RNTC, in series with resistor RA, can
be connected from the RT pin to ground. A constant
current, IRT, is output from the RT pin. The voltage on
the RT pin can be expressed as VRT=IRT • (RNTC + RPTC),
where IRT is 100 µA. At high ambient temperature, the
RNTC is smaller and so that VRT decreased. When VRT is
less than 1.035 V (VRTTH1), the PWM turns off after
16 ms (tD-OTP1). If VRT is less than 0.7 V (VRTTH2), the
PWM turns off after 185 µs (tD-OTP2). If the RT pin is not
connected to NTC resistor for over-temperature
protection, connecting a series one 100 k・ resistor to
ground to prevent from noise interference is
recommended. This pin is limited by an internal
clamping circuit.
0.47
0.46
0.45
0.44
0.43
0.42
0.41
0.4
0.39
0.38
Limited Power Control
100 120 140 160 180 200 220 240 260 280 300 320 340 360 380
The FB voltage is pulled HIGH once the power supply
cannot sustain the output load, such as during output-
short or overload conditions. If the FB voltage remains
DC Voltage on HV Pin (V)
Figure 25. Linearly Current Limit Curve
higher than a built-in threshold for longer than tD-OLP
,
PWM output is turned off. As PWM output is turned off,
VDD begins decreasing. When VDD goes below the turn-
off threshold (10 V) the controller is totally shut down
and VDD is continuously discharged to VDD-OLP (6.5 V) by
IDD-OLP to lower the average input power. This is called
two-level UVLO. VDD is cycled again. This protection
feature continues as long as the overloading condition
persists. This prevents the power supply from
overheating due to overloading conditions.
VDD Over-Voltage Protection (OVP)
VDD over-voltage protection prevents damage due to
abnormal conditions. If the VDD voltage exceeds the
over-voltage protection level (VDD-OVP) and lasts for
tD-VDDOVP, the PWM pulses are disabled and VDD begins
to drop. As VDD drops to VDD-OLP, the internal HV startup
circuit is activated and VDD is charged to VDD-ON to
restart IC. Over-voltage conditions are usually caused
by open feedback loops.
Noise Immunity
Sense-Pin Short-Circuit Protection
Noise on the current sense or control signal may cause
significant pulse-width jitter, particularly in continuous-
conduction mode. Slope compensation helps alleviate
this problem. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the FAN6754WA, and increasing the
power MOS gate resistance improve performance.
The FAN6754WA provides safety protection for Limited
Power Source (LPS) tests. When the sense resistor is
shorted by soldering during production, the pulse-by-
pulse current limiting loses efficiency for the purpose of
providing over-power protection for the unit. The unit
may be damaged when the loading is larger than the
maximum load. To protect against a short circuit across
the current-sense resistor, the controller is designed to
immediately shut down if a continuously low voltage
(around 0.05 V/120 µs) on the SENSE pin is detected.
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
12
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 26. 8-Pin, Small Outline Package (SOP) Package
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without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
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specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
13
© 2011 Fairchild Semiconductor Corporation
FAN6754WA • Rev. 1.0.6
www.fairchildsemi.com
14
Mouser Electronics
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