FAN6755 [FAIRCHILD]
Highly Integrated Green-Mode PWM Controller; 高度集成绿色模式PWM控制器
| 型号： | FAN6755 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Highly Integrated Green-Mode PWM Controller |
| 文件： | 总16页 (文件大小：846K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2010
FAN6755
Highly Integrated Green-Mode PWM Controller
Features
Description
This highly integrated PWM controller provides several
features to enhance the performance of flyback
converters.
Internal High-Voltage Startup
Low Operating Current (Maximum: 2mA)
Adaptive Decreasing of PWM Frequency to 23KHz
at Light-Load condition to Improve Light-Load
Efficiency
To minimize standby power consumption, a proprietary
adaptive green-mode function reduces switching
frequency at light-load condition. To avoid acoustic-
noise problems, the minimum PWM frequency is set
above 23kHz. This green-mode function enables the
power supply to meet international power conservation
requirements, such as Energy Star®. With the internal
high-voltage startup circuitry, the power loss caused by
bleeding resistors is also eliminated. To further reduce
power consumption, FAN6755 uses the BiCMOS
process, which allows an operating current of only 2mA.
The standby power consumption can be under 100mW
for most of LCD monitor power supply designs.
Frequency Hopping to Reduce EMI Emission
Fixed PWM Frequency: 65KHz
Internal Leading-Edge Blanking
Built-in Synchronized Slope Compensation
Auto-Restart Protection : Feedback Open-Loop
Protection (OLP), VDD Over-Voltage Protection
(OVP), Over-Temperature Protection (OTP), and
Line Over-Voltage Protection
FAN6755 integrates a frequency-hopping function that
reduces EMI emission of a power supply with minimum
line filters. Its built-in synchronized slope compensation
Soft Gate Drive with Clamped Output Voltage: 18V
VDD Under-Voltage Lockout (UVLO)
achieves
a stable peak-current-mode control and
Programmable Constant Power Limit (Full AC
Input Range)
improves noise immunity. The proprietary, external line
compensation ensures constant output power limit over
Internal OTP Sensor with Hysteresis
Build-in 5ms Soft-Start Function
a wide AC input voltage range from 90VAC to 264VAC
.
FAN6755 provides many protection functions. The
internal feedback open-loop protection circuit protects
the power supply from open feedback loop condition or
output short condition. It also has line under-voltage
protection (brownout protection) and over-voltage
protection using an input voltage sensing pin (VIN).
Input Voltage Sensing (VIN Pin) for Brown-in/out
Protection with Hysteresis and Line Over-Voltage
Protection
Applications
FAN6755 is available in a 7-pin SOP package.
General-purpose switched-mode power supplies and
flyback power converters, including:
LCD Monitor Power Supply
Open-Frame SMPS
Ordering Information
Operating
Temperature Range
Eco
Status
Part Number
Package
Packing Method
7-Lead, Small Outline Integrated
Circuit (SOIC), Depopulated
FAN6755MY
-40 to +105°C
Green
Reel & Tape
JEDEC MS-112, .150 Inch Body
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
ENERGY STAR® is a registered trademark of the U.S. Department of Energy and the U.S. Environmental Protection Agency.
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
1
Application Diagram
Figure 1.
Typical Application
Internal Block Diagram
Figure 2.
Functional Block Diagram
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
2
Marking Information
7
Z: Plant Code
X: 1-Digit Year Code
Y: 1-Digit Week Code
TT: 2-Digit Die Run Code
T: Package Type (M:SOP)
P: Y=Green Package
M: Manufacture Flow Code
ZXYTT
6755
TPM
1
Figure 3. Top Mark
Pin Configuration
SOP-7
VIN
FB
1
2
3
4
7
HV
SENSE
6
5
VDD
GND
GATE
Figure 4.
Pin Configuration (Top View)
Pin Definitions
Pin #
Name Description
Line-voltage detection. The line-voltage detection is used for brownout protection with
hysteresis. Constant output power limit over universal AC input range is also achieved using this
VIN pin. It is suggested to add a low-pass filter to filter out line ripple on the bulk capacitor.
Pulling VIN HIGH also triggers auto-restart protection.
1
VIN
FB
The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is
determined in response to the signal on this pin and the current-sense signal on the SENSE pin.
2
3
Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle
current limiting.
SENSE
GND
4
5
Ground
GATE The totem-pole output driver. Soft-driving waveform is implemented for improved EMI.
Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
6
7
VDD
HV
For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VVDD
VFB
Parameter
Min.
Max.
30
Unit
V
DC Supply Voltage(1, 2)
FB Pin Input Voltage
-0.3
-0.3
-0.3
7.0
V
VSENSE
VVIN
SENSE Pin Input Voltage
VIN Pin Input Voltage
7.0
V
7.0
V
VHV
HV Pin Input Voltage
700
400
V
Power Dissipation (TA＜50°C)
PD
mW
Thermal Resistance (Junction to Air)
Operating Junction Temperature
150
ΘJA
TJ
°C/W
°C
-40
-55
+125
+150
+260
TSTG
TL
Storage Temperature Range
°C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
°C
Human Body Model,
All Pins Except HV Pin
JEDEC: JESD22-A114
4.5
1.0
ESD
kV
Charged Device Model,
All Pins Except HV Pin
JEDEC: JESD22-C101
Notes:
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD with HV pin CDM=1000V and HBM=500V.
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
4
Electrical Characteristics
VDD=15V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD Section
VOP
Continuously Operating Voltage
Start Threshold Voltage
22
17
11
8.8
30
2
V
V
VDD-ON
15
9
16
10
VDD-OFF Protection Mode
V
UVLO
IDD-ST
Normal Mode
6.8
7.8
V
Startup Current
VDD-ON – 0.16V
µA
mA
µA
IDD-OP
IDD-OLP
Operating Supply Current
Internal Sink Current
VDD=15V, GATE Open
VTH-OLP+0.1V
30
6.5
25
75
60
7.5
26
90
Threshold Voltage on VDD for HV
JFET Turn-On
VDD-OLP
8.0
27
V
V
VDD-OVP VDD Over-Voltage Protection
VDD Over-Voltage Protection
tD-VDDOVP
125
200
µs
Debounce Time
Figure 5.
VDD Behavior
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
5
Electrical Characteristics
VDD=15V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
HV Section
Supply Current Drawn from HV
Pin
VDC=120V, VDD=10µF,
IHV
mA
µA
2.0
3.5
1
5.0
20
VDD=0V
HV=700V, VDD=VDD-
OFF+1V
IHV-LC
Leakage Current after Startup
Oscillator Section
62
±4.5
20
65
±5.2
23
68
±5.9
26
Center Frequency
Hopping Range
fOSC
Frequency in Normal Mode
KHz
fOSC-G
Green-Mode Frequency
Hopping Period
KHz
ms
tH OP
fDV
fDT
-
4.20
5.05
5.90
5
Frequency Variation vs. VDD
Deviation
VDD=11V to 22V
%
%
Frequency Variation vs.
Temperature Deviation
5
TA=-40 to 85°C
VIN Section
VIN-OFF PWM Turn-Off Threshold Voltage
0.66
0.70
0.74
V
V
VIN-OFF
0.17
+
VIN-OFF
0.20
+
VIN-OFF
0.23
+
VIN-ON
VIN-Protect
tVIN-Protect
PWM Turn-On Threshold Voltage
PWM Protect Threshold Voltage
PWM Protect Debounce Time
5.1
60
5.3
5.5
V
100
140
µs
Current-Sense Section
Threshold Voltage for Current
Limit
VTH-P at
VIN=1V
VIN=1V
VIN=3V
0.80
0.67
0.83
0.70
0.86
0.73
V
V
Threshold Voltage for Current
Limit
VTH-P at
VIN=3V
tPD
tLEB
tSS
Delay to Output
100
290
5.5
200
340
7.0
ns
ns
Leading-Edge Blanking Time
Period During Soft-Start Time
240
4.0
Startup Time
ms
Figure 6.
VIN vs. VSENSE
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
6
Electrical Characteristics
VDD=15V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Feedback Input Section
Input Voltage to Current-Sense
Attenuation
AV
1/4.5
1/4.0
1/3.5
V/V
ZFB
Input Impedance
11
5.1
4.4
15
5.3
4.6
18
5.5
4.8
kΩ
V
VFB =4V
FB Pin Open
VFB-OPEN Output High Voltage
VFB-OLP FB Open-Loop Trigger Level
V
Delay Time of FB Pin Open-loop
Protection
tD-OLP
45.0
2.8
62.5
70.0
3.2
ms
VFB-N
VFB-G
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
3.0
V
V
VFB-N - 0.6
FB Threshold Voltage for Zero-
Duty Recovery
VFB-ZDCR
1.6
1.4
1.8
1.6
2.0
1.8
V
V
V
FB Threshold Voltage for Zero-
Duty
VFB-ZDC
VFB-ZDCR -
ZDC Hysterisis
0.12
0.15
0.19
VFB-ZDC
PWM Frequency
fOSC
fOSC-G
VFB-ZDC
V
FB-ZDCR VFB-G
VFB-N
VFB
Figure 7.
VFB vs. PWM Frequency
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
7
Electrical Characteristics
VDD=15V, TA=25°C, unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
GATE Section
DCYMAX Maximum Duty Cycle
VGATE-L Gate Low Voltage
VGATE-H Gate High Voltage
60
8
75
90
%
V
VDD=15V, IO=50mA
VDD=12V, IO=50mA
VDD=15V, CL=1nF
VDD=15V, CL=1nF
1.5
V
Gate Rising Time
Gate Falling Time
tr
tf
ns
ns
100
30
IGATE-
SOURCE
mA
V
Gate Source Current
VDD=15V, GATE=6V
VDD=22V
700
VGATE-
CLAMP_1
Gate Output Clamping Voltage
18
Over-Temperature Protection Section (OTP)
TOTP
TRestart
Notes:
Protection Junction Temperature(4)
Restart Junction Temperature(5)
135
°C
°C
TOTP-25
4. When activated, the output is disabled and the latch is turned off.
5. The threshold temperature for enabling the output again and resetting the latch after over-temperature
protection has been activated.
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
8
Typical Performance Characteristics
Figure 9. Operation Supply Current (IDD-OP
)
Figure 8. Startup Current (IDD-ST) vs. Temperature
vs. Temperature
Figure 10.Start Threshold Voltage (VDD-ON
)
Figure 11.Minimum Operating Voltage (VDD-OFF
vs. Temperature
)
vs. Temperature
Figure 12.Supply Current Drawn from HV Pin (IHV
)
Figure 13.HV Pin Leakage Current After Startup
(IHV-LC) vs. Temperature
vs. Temperature
Figure 14.Frequency in Normal Mode (fOSC
)
Figure 15.Maximum Duty Cycle (DCYMAX
)
vs. Temperature
vs. Temperature
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
9
Typical Performance Characteristics
Figure 16.FB Open-Loop Trigger Level (VFB-OLP
)
Figure 17.Delay Time of FB Pin Open-Loop Protection
(tD-OLP) vs. Temperature
vs. Temperature
VIN-ON
VIN-OFF
Figure 18.PWM Turn-Off Threshold Voltage (VIN-OFF
VIN-ON) vs. Temperature
&
Figure 19.VDD Over-Voltage Protection (VDD-OVP
)
vs. Temperature
Figure 20.VIN vs. VLIMIT
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
10
Functional Description
Startup Current
Gate Output / Soft Driving
For startup, the HV pin is connected to the line input
(1N4007 / 100KΩ recommended) or bulk capacitor
through a resistor, RHV. Startup current drawn from pin
HV (typically 3.5mA) charges the hold-up capacitor
through the diode and resistor. When the VDD capacitor
level reaches VDD-ON, the startup current switches off. At
this moment, the VDD capacitor only supplies the
FAN6755 to maintain VDD before the auxiliary winding of
the main transformer to provide the operating current.
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 5.5ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Operating Current
Operating current is around 2mA. The low operating
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance.
Slope Compensation
Green-Mode Operation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillation.
FAN6755 inserts a synchronized positive-going ramp at
every switching cycle.
The proprietary green-mode function provides an off-
time modulation to reduce the switching frequency in
light-load and no-load conditions. The on time is limited
for better abnormal or brownout protection. VFB, which is
derived from the voltage feedback loop, is taken as the
reference. Once VFB is lower than the threshold voltage,
switching frequency is continuously decreased to the
minimum green-mode frequency of around 23KHz.
Constant Output Power Limit
For constant output power limit over universal input-
voltage range, the peak-current threshold is adjusted by
the voltage of the VIN pin. Since the VIN pin is
connected to the rectified AC input line voltage through
the resistive divider, a higher line voltage generates a
higher VIN voltage. The threshold voltage decreases as
VIN increases, making the maximum output power at
high-line input voltage equal to that at low-line input.
The value of R-C network should not be so large that it
affects the power limit (shown in Figure 21). Usually, R
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current sense signal and VFB, the feedback voltage.
When the voltage on the SENSE pin reaches around
VCOMP=(VFB–0.6)/4,
a
switch cycle is terminated
immediately. VCOMP is internally clamped to a variable
voltage around 0.83V for output power limit.
and
respectively.
C should be less than 100Ω and 470pF,
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16V and 7.8V in normal mode. During startup, the
hold-up capacitor must be charged to 16V through the
startup resistor to enable the IC. The hold-up capacitor
continues to supply VDD before the energy can be
delivered from auxiliary winding of the main transformer.
VDD must not drop below 7.8V during startup. This
UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply VDD during startup.
Figure 21. Current-Sense R-C Filter
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
11
VDD Over-Voltage Protection
Limited Power Control
VDD over-voltage protection prevents damage due to
abnormal conditions. Once the VDD voltage is over the
over-voltage protection voltage (VDD-OVP), and lasts for
The FB voltage is saturated HIGH when the power
supply output voltage drops below its nominal value and
shut regulator (KA431) does not draw current through
the opto-coupler. This occurs when the output feedback
loop is open or output is short circuited. If the FB
voltage is higher than a built-in threshold for longer than
t
D-VDDOVP, the PWM pulses are disabled. When the VDD
voltage drops below the UVLO, PWM pulses start
again. Over-voltage conditions are usually caused by
open feedback loops.
t
D-OLP, PWM output is turned off. As PWM output is
turned off, VDD begins decreasing since no more energy
is delivered from the auxiliary winding.
Brownout Protection
When VDD goes below the turn-off threshold (~7.8V),
the controller is totally shut down. VDD is charged up to
the turn-on threshold voltage of 16V through the startup
resistor until PWM output is restarted. This protection
feature continues as long as the over loading condition
persists. This prevents the power supply from
overheating due to overloading conditions.
Since the VIN pin is connected through a resistive
divider to the rectified AC input line voltage, it can also
be used for brownout protection. If VIN is less than 0.7V,
the PWM output is shut off. When VIN reaches over
0.9V, the PWM output is turned on again. The
hysteresis window for ON/OFF is around 0.2V. The
brownout voltage setting is determined by the potential
divider formed with RUpper and RLower. Equations to
calculate the resistors are shown below:
Noise Immunity
Noise on the current sense or control signal may cause
significant pulse-width jitter, particularly in continuous-
conduction mode. Slope compensation helps alleviate
this problem. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the FAN6755, and increasing the
power MOS gate resistance improve performance.
RLower
VIN =
×VAC 2, (unit = V)
(1)
RLower + RUpper
Thermal Overload Protection
Thermal overload protection limits total power
dissipation. When the junction temperature exceeds TJ=
+135°C, the thermal sensor signals the shutdown logic
and turns off most of the internal circuitry. The thermal
sensor turns internal circuitry on again after the IC’s
junction temperature drops by 25°C. Thermal overload
protection is designed to protect the FAN6755 in the
event of a fault condition. For continual operation, do
not exceed the absolute maximum junction temperature
of TJ = +150°C.
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
12
Applications Information
R6
R7
12V1
1
12V
P1
C7
N18
L2
2
12V
C5
1
R8
C10
C8
C9
+
+
F1
2
N1
N1A
R1
N2
3
BD1
C1
C2
CN1
TX1
L
L1
4
1
N4
4
12
11
N17 D1
M1
1
2
3
C3
N28
R4
R5
N21
ZD1
VIN
C4
R3
C6
ACIN
R2
8
N20
7
5V1
1
5V
P2
L3
2
5V
N
N3
N5 N6
6
1
C11
+
1
3
D3
R14
2
N7
10
9
R17
2
D4
C15
C13
C14
+
+
C12
R13
D5
R9
N8
P3
SGND
Q1
N30
R10
R16
N10
D2
1 N9
R11
R12
N29
R15
HV
VIN
C16
U1
VIN
1
8
7
6
5
HV
NA
R20
FB
2
3
4
VDD
FB
5V1
R22
R19
N12
N13
SENSE
VDD
GATE
U2
GATE
GND
12V
5V
C18
C19
FAN67 55
+
R28
C17
SENSE
R23
R24
R25
C20
R21
R
N14
N15
U3
N16
R18
R26
R27
Figure 22. 44W Flyback 12V/2A, 5V/4A Application Circuit
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
13
Build of Materials
Designator
Part Type
BD 4A/600V
Designator
Part Type
MOS 9A/600V
BD1
C1
Q1
R1
R2
R3
YC 2200pF/Y1
YC 2200pF/Y1
XC 0.33µF/300V
NC
R 1.5MΩ 1/4W
R 1.5MΩ 1/4W
R 10MΩ 1/4W
R 47Ω 1/4W
NC
C2
C3
C4
R4, R5, R6, R7
C5
R8, R17, R25, R27
YC 2200pF/Y1
CC 2200pF/100V
CC 1000pF/100V
EC 1000µF/25V
EC 470µF/25V
CC 100pF/50V
EC 100µF/400V
C 1µF/50V
C6
R9
R 50KΩ 1/4W
R 50KΩ 1/4W
R 0Ω 1/8W
C7
R10
R11
R12
R13
R14
R15
R16
R18
R19
R20
R21
R22
R23
R24
R26
R28
TX1
U1
C8
C9
R 47Ω 1/8W
R 100KΩ 1/8W
R 0Ω 1/4W
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
R 10KΩ 1/8W
R 1Ω 1/8W
EC 1000µF/10V
EC 470µF/10V
CC 100pF/50V
C 1nF/50V
R 0Ω 1/8W
R 100Ω 1/8W
R 1KΩ 1/8W
R 4.7KΩ 1/8W
R 7.5KΩ 1/8W
R 120KΩ 1/8W
R 15KΩ 1/8W
R 10KΩ 1/8W
R 0.43Ω 2W
800µH(ERL-28)
IC FAN6755
IC PC817
C 470pF/50V
EC 47µF/50V
C 0.01µF/50V
C 0.1µF/50V
FYP1010
D2
1N4148
D3
FR107
D4
FR103
D5
U2
FYP1010
ZD1
F1
P6KE150A
U3
IC TL431
FUSE 4A/250V
VZ 9G
M1
L1
13mH
L2
Inductor (2µH)
Inductor (2µH)
L3
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
14
Physical Dimensions
3.81
5.00
4.80
A
0.65TYP
1.75TYP
3.81
8
5
B
6.20
5.80
4.00
3.80
3.85 7.35
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45¢X
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8¢X
0¢X
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
DATED MAY 1990 EXCEPT PIN# 7 IS REMOVED.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) STANDARD LEAD FINISH:
200 MICROINCHES / 5.08 MICRONS MIN.
LEAD/TIN (SOLDER) ON COPPER.
E) DRAWING FILENAME : M07AREV2
DETAIL A
SCALE: 2:1
Figure 23. 7-Lead, Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
15
© 2009 Fairchild Semiconductor Corporation
FAN6755 • Rev. 1.0.0
www.fairchildsemi.com
16
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