FDN361 [FAIRCHILD]
N-Channel, Logic Level, PowerTrenchビヌ; N沟道逻辑电平的PowerTrenchビヌ
| 型号： | FDN361 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | N-Channel, Logic Level, PowerTrenchビヌ |
| 文件： | 总8页 (文件大小：947K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1999
FDN361AN
N-Channel, Logic Level, PowerTrenchΤΜ
Features
General Description
This N-Channel Logic Level MOSFET is produced using
Fairchild Semiconductor's PowerTrench process that has
been especially tailored to minimize the on-state resistance
and yet maintain low gate charge for superior switching
performance.
• 1.8 A, 30 V. RDS(on) = 0.100 Ω @ VGS = 10 V
RDS(on) = 0.150 Ω @ VGS = 4.5 V.
• Low gate charge ( 2.1nC typical ).
• Fast switching speed.
• High performance trench technology for extremely
Applications
low RDS(on)
.
• DC/DC converter
• Load switch
• Motor drives
• High power version of industry standard SOT-23
package. Identical pin out to SOT-23 with
30% higher power handling capability.
D
D
S
S
G
SuperSOTTM-3
G
TA=25oC unless otherwise noted
Absolute Maximum Ratings
Symbol
Parameter
FDN361AN
Units
VDSS
Drain-Source Voltage
Gate-Source Voltage - Continuous
Drain Current - Continuous
- Pulsed
30
V
VGSS
ID
20
V
A
±
(Note 1a)
(Note 1a)
1.8
8
PD
Power Dissipation for Single Operation
0.5
W
(Note 1b)
0.46
Operating and Storage Junction Temperature Range
-55 to +150
C
°
TJ, T
stg
Thermal Characteristics
θ
(Note 1a)
(Note 1)
R
Thermal Resistance, Junction-to-Ambient
250
75
C/W
C/W
JA
°
°
R
Thermal Resistance, Junction-to-Case
JC
θ
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
361
FDN361AN
7’’
8mm
3000 units
1998 Fairchild Semiconductor Corporation
FDN361AN, Rev. C
DMOS Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250
A
30
V
µ
Breakdown Voltage Temperature ID = 250 A, Referenced to 25 C
Coefficient
24
mV/ C
DSS
BV
∆
µ
°
°
∆
TJ
IDSS
Zero Gate Voltage Drain Current
Gate-Body Leakage, Forward
VDS = 24 V, VGS = 0 V
VGS = 20 V, VDS = 0 V
VGS = -20 V, VDS = 0 V
1
A
µ
IGSSF
IGSSR
100
-100
nA
nA
Gate-Body Leakage, Reverse
On Characteristics (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250
A
1
8
1.8
3
V
µ
Gate Threshold Voltage
Temperature Coefficient
ID = 250 A, Referenced to 25 C
-4.2
mV/ C
GS(th)
V
µ
°
°
∆
TJ
∆
RDS(on)
Static Drain-Source
On-Resistance
VGS = 10 V, ID = 1.8 A
0.072
0.107
0.105
0.1
0.16
0.15
Ω
V
V
GS = 10 V, ID = 1.8 A, TJ = 125 C
GS = 4.5 V, ID = 1.4 A
°
ID(on)
gFS
On-State Drain Current
VGS = 10 V, VDS = 5 V
VDS = 10 V, ID = 1.8 A
A
S
Forward Transconductance
5
Dynamic Characteristics
Ciss
Coss
Crss
Input Capacitance
VDS = 15 V, VGS = 0 V, f = 1.0 MHz
220
50
pF
pF
pF
Output Capacitance
Reverse Transfer Capacitance
20
Switching Characteristics (Note 2)
td(on)
t
td(off)
tf
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDD = 15 V, ID = 1 A,
3
11
7
6
22
14
6
ns
ns
VGS = 10 V, RGEN = 6.0
Ω
ns
3
ns
Qg
Qgs
Qgd
VDS = 15 V, ID = 1.8 A,
VGS = 5 V
2.1
0.8
0.7
4
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
0.42
1.2
A
V
(Note 2)
VSD
Drain-Source Diode Forward
Voltage
VGS = 0 V, IS = 0.42 A
0.75
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting
surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user's board design.
a) 250°C/W when mounted
b) 270°C/W when mounted
on a mininum pad.
on a 0.02 in2 pad of 2 oz. Cu.
Scale
1
:
1
on letter size paper
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
FDN361AN, Rev. C
Typical Characteristics (continued)
2.5
2
8
VGS= 10V
6.0V
4.5V
4.0V
V
= 3. 5V
6
GS
3.5V
4.0V
1.5
1
4
4.5V
5.0V
7.0V
3.0V
10V
2
0.5
0
0
2
4
6
8
10
0
0.5
1
1.5
2
2.5
3
I
, DRAIN CURRENT (A)
D
V
, DRAIN -SOURCE VOLTAGE (V)
DS
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
0.3
ID= 0.9A
ID = 1.8 A
0.25
VGS= 10 V
1.4
1.2
1
0.2
0.15
TA = 125°C
0.1
0.8
0.6
TA = 25°C
0.05
0
2
4
6
8
10
-50
-25
0
25
50
75
100
125
150
V
, GATE TO SOURCE VOLTAGE (V)
T
, JUNCTION TEMPERATURE (°C)
GS
J
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
10
8
6
4
2
0
T = -55°C
J
VGS= 0V
VDS=5.0V
25°C
125°C
T = 125°C
1
0.1
J
25°C
-55°C
0. 0 1
0.001
0.2
0.4
0.6
0.8
1
1.2
1
2
3
4
5
V
, BODY DIODE FORWARD VOLTAGE (V)
V
, GATE TO SOURCE VOLTAGE (V)
GS
S D
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDN361AN, Rev. C
Typical Characteristics (continued)
10
500
ID = 1.8A
VDS = 5V
8
6
4
2
0
C
C
iss
10V
200
100
50
15V
oss
f = 1 MH z
VGS = 0 V
20
10
C
rss
0
1
2
3
4
0.1
0.2
V
0.5
1
2
5
10
30
Q
, GATE CHARGE (nC)
, DRA IN TO SOURCE VO LTAGE (V )
DS
g
Figure 7. Gate-Charge Characteristics.
Figure 8. Capacitance Characteristics.
30
10
50
40
30
20
10
SINGLE PULSE
JA
Rθ
=270° C/W
3
1
TA = 25°C
0.3
VGS = 10V
SINGLE PULSE
RθJA=270°C/W
0.1
0.03
TA = 25°C
0
0.01
0.1
0.0001
0.001
0.01
0.1
1
10
100 300
0.2 0.5
1
2
5
10
20 30 50
SI NGLE PULS E TI ME (SE C)
V
,DRAIN-SOURCE VOLTAGE (V)
DS
Figure 10. Single Pulse Maximum
Power Dissipation.
Figure 9. Maximum Safe Operating Area.
1
D = 0.5
0.5
0. 2
0.2
R
(t) = r(t) * R
JA JA
θ
θ
0. 1
R
= 270 °C /W
JA
θ
0.1
00. 5
0. 0 5
00. 2
P(pk )
0. 0 2
0. 0 1
00. 1
t
1
Si ng l e P u l s e
t
2
0.005
T
- T =P * R
(t)
J A
J
A
θ
D u t y C y c le, D = t / t
1
0.002
0.001
2
0.0001
0.001
0.01
0.1
1
10
100
300
t , TMI E (sec)
1
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient themal response will change depending on the circuit board design.
FDN361AN, Rev. C
SuperSOTTM-3 Tape and Reel Data and Package Dimensions
SSOT-3 Packaging
Configuration: Figure 1.0
Packaging Description:
SSOT-3 parts are shipped in tape. The carrier tape is
Customize Label
made from dissipative (carbon filled) polycarbonate
a
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
3,000 units per 7" or 177cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 10,000 units per 13"
or 330cm diameter reel. This and some other options are
described in the Packaging Information table.
Antistatic Cover Tape
These full reels are individually labeled and placed inside
a
standard intermediate made of recyclable corrugated
brown paper with a Fairchild logo printing. One pizza box
contains eight reels maximum. And these intermediate
boxes are placed inside
a labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
Human Readable
Label
Embossed
Carrier Tape
3P
3P
3P
3P
SSOT-3 Std Packaging Information
Standard
(no flow code)
Packaging Option
D87Z
Packaging type
TNR
TNR
10,000
13"
SSOT-3 Std Unit Orientation
Qty per Reel/Tube/Bag
Reel Size
3,000
7" Dia
Box Dimension (mm)
Max qty per Box
187x107x183 343x343x64
343mm x 342mm x 64mm
Intermediate box for D87Z Option
Human Readable Label
24,000
0.0097
0.1230
30,000
0.0097
0.4150
Weight per unit (gm)
Weight per Reel (kg)
Note/Comments
Human Readable Label sample
Human Readable
Label
187mm x 107mm x 183mm
SSOT-3 Tape Leader and Trailer
Intermediate Box for Standard Option
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Components
Trailer Tape
Leader Tape
300mm minimum or
75 empty pockets
500mm minimum or
125 empty pockets
August 1999, Rev. C
SuperSOTTM-3 Tape and Reel Data and Package Dimensions, continued
SSOT-3 Embossed Carrier Tape
Configuration: Figure 3.0
P0
P2
D0
D1
T
E1
E2
W
F
Wc
B0
Tc
K0
A0
P1
User Direction of Feed
Dimensions are in millimeter
E1 E2
A0
B0
W
D0
D1
F
P1
P0
K0
T
Wc
Tc
Pkg type
SSOT-3
(8mm)
3.15
+/-0.10
2.77
+/-0.10
8.0
+/-0.3
1.55
+/-0.05
1.125
+/-0.125
1.75
+/-0.10
6.25
min
3.50
+/-0.05
4.0
+/-0.1
4.0
+/-0.1
1.30
+/-0.10
0.228
+/-0.013
5.2
+/-0.3
0.06
+/-02
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
0.5mm
maximum
20 deg maximum
Typical
component
cavity
center line
0.5mm
maximum
B0
20 deg maximum component rotation
Typical
component
center line
Sketch A (Side or Front Sectional View)
Component Rotation
Sketch C (Top View)
Component lateral movement
A0
Sketch B (Top View)
Component Rotation
SSOT-3 Reel Configuration: Figure 4.0
W1 Measured at Hub
Dim A
Max
Dim A
max
See detail AA
Dim N
7"Diameter Option
B Min
Dim C
See detail AA
Dim D
min
W3
13" Diameter Option
W2 max Measured at Hub
DETAIL AA
Dim W2
Dimensions are in inches and millimeters
Reel
Option
Tape Size
8mm
Dim A
Dim B
Dim C
Dim D
Dim N
Dim W1
Dim W3 (LSL-USL)
7.00
177.8
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 – 0.429
7.9 – 10.9
7" Dia
13.00
330
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
4.00
100
0.331 +0.059/-0.000
8.4 +1.5/0
0.567
14.4
0.311 – 0.429
7.9 – 10.9
8mm
13" Dia
July 1999, Rev. C
SuperSOTTM-3 Tape and Reel Data and Package Dimensions, continued
SuperSOT -3 (FS PKG Code 32)
1 : 1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0097
September 1998, Rev. A
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
SyncFET™
TinyLogic™
UHC™
CROSSVOLT™
E2CMOSTM
VCX™
FACT™
FACT Quiet Series™
QS™
FAST®
Quiet Series™
SuperSOT-™3
SuperSOT-™6
SuperSOT-™8
FASTr™
GTO™
HiSeC™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. D
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