FDW2601NZ [FAIRCHILD]

Dual N-Channel 2.5V Specified PowerTrench MOSFET; 双N沟道2.5V指定的PowerTrench MOSFET
FDW2601NZ
型号: FDW2601NZ
厂家: FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述:

Dual N-Channel 2.5V Specified PowerTrench MOSFET
双N沟道2.5V指定的PowerTrench MOSFET

文件: 总11页 (文件大小:265K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
December 2004  
FDW2601NZ  
®
Dual N-Channel 2.5V Specified PowerTrench  
MOSFET  
Features  
General Description  
! 8.2A, 30V  
r
= 0.015, V = 4.5V  
This N-Channel MOSFET is produced using Fairchild  
Semiconductor’s advanced PowerTrench process that has  
been especially tailored to minimize the on-state resistance  
and yet maintain low gate charge for superior switching  
performance. These devices are well suited for portable  
electronics applications.  
DS(ON)  
GS  
r
= 0.020, V = 2.5V  
GS  
DS(ON)  
! Extended V range (±12 V) for battery applications  
GS  
! HBM ESD Protection Level of 3.5kV Typical (note 3)  
! High performance trench technology for extremely low  
r
DS(ON)  
! Low profile TSSOP-8 package  
Applications  
! Load switch  
! Battery charge  
! Battery disconnect circuits  
D1  
D2  
G2  
S2  
S2  
D2  
G1  
S1  
S1  
D1  
G1  
G2  
S1  
S2  
Pin 1  
TSSOP-8  
©2004 Fairchild Semiconductor Corporation  
FDW2601NZ Rev. A  
www.fairchildsemi.com  
1
Absolute Maximum Ratings T =25°C unless otherwise noted  
A
Symbol  
Parameter  
Ratings  
30  
Units  
V
V
Drain to Source Voltage  
Gate to Source Voltage  
V
V
DSS  
GS  
±12  
Drain Current  
Continuous (T = 25 C, V = 4.5V, R  
o
o
= 77 C/W)  
8.2  
4.5  
A
A
C
GS  
θJA  
I
o
o
D
Continuous (T = 100 C, V = 2.5V, R  
= 77 C/W)  
C
GS  
θJA  
Pulsed  
Figure 4  
1.6  
A
Power dissipation  
W
P
D
o
Derate above 25°C  
13  
mW/ C  
o
T , T  
Operating and Storage Temperature  
-55 to 150  
C
J
STG  
Thermal Characteristics  
o
R
R
Thermal Resistance Junction to Ambient (Note 1)  
Thermal Resistance Junction to Ambient (Note 2)  
77  
C/W  
C/W  
θJA  
θJA  
o
114  
Package Marking and Ordering Information  
Device Marking  
2601NZ  
Device  
Package  
TSSOP-8  
TSSOP-8  
Reel Size  
13”  
Tape Width  
Quantity  
2500 units  
2500 units  
FDW2601NZ  
12 mm  
12 mm  
2601NZ  
FDW2601NZ_NL (Note 4)  
13”  
Electrical Characteristics T = 25°C unless otherwise noted  
A
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
B
Drain to Source Breakdown Voltage  
I
= 250µA, V = 0V  
30  
-
-
-
-
-
-
1
V
VDSS  
D
GS  
V
V
V
V
= 24V  
= 0V  
DS  
GS  
GS  
GS  
I
I
DSS  
Zero Gate Voltage Drain Current  
µA  
o
T =100 C  
-
5
A
= ±12V  
= ±4.5V  
-
±10  
±250  
µA  
Gate to Source Leakage Current  
GSS  
nA  
On Characteristics  
V
Gate to Source Threshold Voltage  
V
= V , I = 250µA  
0.6  
0.8  
1.5  
V
GS(TH)  
GS  
DS  
D
I
I
I
I
= 8.2A, V = 4.5V  
-
-
-
-
0.011  
0.011  
0.012  
0.012  
0.015  
0.016  
0.019  
0.020  
D
D
D
D
GS  
= 7.9A, V = 4.0V  
GS  
r
DS(ON)  
Drain to Source On Resistance  
= 7.3A, V = 3.1V  
GS  
= 7.1A, V = 2.5V  
GS  
Dynamic Characteristics  
C
C
C
R
Input Capacitance  
-
-
-
-
-
-
-
-
1840  
250  
160  
2.6  
20  
-
-
pF  
pF  
pF  
ISS  
OSS  
RSS  
G
V
= 15V, V = 0V,  
GS  
DS  
Output Capacitance  
f = 1MHz  
Reverse Transfer Capacitance  
Gate Resistance  
-
V
= 0.5V, f = 1MHz  
= 0V to 4.5V  
-
GS  
Q
Q
Q
Q
Total Gate Charge at 4.5V  
Total Gate Charge at 2.5V  
Gate to Source Gate Charge  
Gate to Drain MillerCharge  
V
V
30  
18  
-
nC  
nC  
nC  
nC  
g(TOT)  
g(2.5)  
gs  
GS  
GS  
V
I
= 15V  
= 8.2A  
DD  
= 0V to 2.5V  
12  
D
2.7  
5.1  
I = 1.0mA  
g
-
gd  
www.fairchildsemi.com  
2
FDW2601NZ Rev. A  
Switching Characteristics (V = 4.5V)  
GS  
t
t
t
t
t
t
Turn-On Time  
Turn-On Delay Time  
Rise Time  
-
-
-
-
-
-
-
113  
ns  
ns  
ns  
ns  
ns  
ns  
ON  
18  
57  
69  
71  
-
-
d(ON)  
-
V
V
= 15V, I = 8.2A  
r
DD  
GS  
D
= 4.5V, R = 6.8Ω  
Turn-Off Delay Time  
Fall Time  
-
-
GS  
d(OFF)  
f
Turn-Off Time  
210  
OFF  
Drain-Source Diode Characteristics  
V
Source to Drain Diode Voltage  
Reverse Recovery Time  
I
I
I
= 1.3A  
-
-
-
0.7  
1.2  
28  
17  
V
SD  
SD  
SD  
SD  
t
= 8.2A, dI /dt = 100A/µs  
-
-
ns  
nC  
rr  
SD  
Q
Reverse Recovered Charge  
= 8.2A, dI /dt = 100A/µs  
SD  
RR  
Notes:  
o
2
1. R  
is 77 C/W (steady state) when mounted on a 1 inch copper pad on FR-4.  
θJA  
θJA  
o
2. R  
is 114 C/W (steady state) when mounted on a mininum copper pad on FR-4.  
3. The diode connected to the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.  
4. FDW2601NZ_NL is lead free product. FDW2601NZ_NZ marking will appear on the reel label.  
www.fairchildsemi.com  
3
FDW2601NZ Rev. A  
Typical Characteristic T = 25°C unless otherwise noted  
A
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
10  
8
V
= 4.5V  
GS  
6
4
V
= 2.5V  
GS  
2
0
0
25  
50  
75  
100  
125  
150  
25  
50  
75  
100  
125  
150  
o
o
T , AMBIENT TEMPERATURE ( C)  
T , AMBIENT TEMPERATURE ( C)  
A
A
Figure 1. Normalized Power Dissipation vs  
Ambient Temperature  
Figure 2. Maximum Continuous Drain Current vs  
Ambient Temperature  
2
DUTY CYCLE - DESCENDING ORDER  
0.5  
1
0.2  
0.1  
0.05  
0.02  
0.01  
P
DM  
0.1  
t
1
t
2
NOTES:  
DUTY FACTOR: D = t /t  
1
2
PEAK T = P  
x Z  
x R  
+ T  
J
DM  
θJA  
θJA A  
0.01  
-4  
-3  
-2  
-1  
0
1
2
3
-5  
10  
10  
10  
10  
10  
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
Figure 3. Normalized Maximum Transient Thermal Impedance  
500  
o
T
= 25 C  
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
A
FOR TEMPERATURES  
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
o
100  
150 - T  
A
I = I  
25  
125  
V
= 2.5V  
GS  
10  
5
-5  
-4  
-3  
-2  
-1  
0
1
2
3
10  
10  
10  
10  
10  
t, PULSE WIDTH (s)  
10  
10  
10  
10  
Figure 4. Peak Current Capability  
www.fairchildsemi.com  
4
FDW2601NZ Rev. A  
Typical Characteristic (Continued) T = 25°C unless otherwise noted  
A
300  
100  
60  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
V
= 10V  
DD  
100µs  
40  
1ms  
10  
o
T
= 150 C  
J
OPERATION IN THIS  
10ms  
AREA MAY BE  
20  
0
LIMITED BY r  
o
DS(ON)  
T
= 25 C  
J
o
T
= -55 C  
SINGLE PULSE  
J
T
= MAX RATED  
J
1
o
T
= 25 C  
A
0.5  
0.1  
1
10  
40  
1.0  
1.5  
2.0  
2.5  
V
, DRAIN TO SOURCE VOLTAGE (V)  
V
, GATE TO SOURCE VOLTAGE (V)  
DS  
GS  
Figure 5. Forward Bias Safe Operating Area  
Figure 6. Transfer Characteristics  
60  
45  
V
= 10V  
GS  
V
= 2.5V  
GS  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
I
= 8.2A  
D
V
= 4.5V  
GS  
40  
30  
15  
0
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
o
T
= 25 C  
A
I
= 1A  
D
20  
0
V
= 1.8V  
GS  
0
0.5  
1.0  
1.5  
1
2
3
4
5
V
, DRAIN TO SOURCE VOLTAGE (V)  
V
, GATE TO SOURCE VOLTAGE (V)  
DS  
GS  
Figure 7. Saturation Characteristics  
Figure 8. Drain to Source On Resistance vs Gate  
Voltage and Drain Current  
2.0  
1.25  
PULSE DURATION = 80µs  
DUTY CYCLE = 0.5% MAX  
V
= V , I = 250µA  
DS D  
GS  
1.00  
1.5  
0.75  
0.50  
1.0  
0.5  
V
= 4.5V, I = 8.2A  
D
GS  
-80  
-40  
0
40  
80  
120  
160  
-80  
-40  
0
40  
80  
120  
160  
o
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
Figure 9. Normalized Drain to Source On  
Resistance vs Junction Temperature  
Figure 10. Normalized Gate Threshold Voltage vs  
Junction Temperature  
www.fairchildsemi.com  
5
FDW2601NZ Rev. A  
Typical Characteristic (Continued) T = 25°C unless otherwise noted  
A
1.10  
1.05  
1.00  
0.95  
0.90  
4000  
C
= C + C  
GS GD  
ISS  
I
= 250µA  
D
1000  
C
C
+ C  
OSS  
DS GD  
C
= C  
GD  
RSS  
V
= 0V, f = 1MHz  
GS  
100  
-80  
-40  
0
40  
80  
120  
160  
0.1  
1
10  
, DRAIN TO SOURCE VOLTAGE (V)  
30  
o
T , JUNCTION TEMPERATURE ( C)  
V
DS  
J
Figure 11. Normalized Drain to Source  
Breakdown Voltage vs Junction Temperature  
Figure 12. Capacitance vs Drain to Source  
Voltage  
4.5  
V
= 15V  
DD  
3.0  
1.5  
WAVEFORMS IN  
DESCENDING ORDER:  
I
I
= 1A  
= 8.2A  
D
D
0
0
5
10  
15  
20  
25  
Qg, GATE CHARGE (nC)  
Figure 13. Gate Charge Waveforms for Constant Gate Currents  
www.fairchildsemi.com  
6
FDW2601NZ Rev. A  
Test Circuits and Waveforms  
V
DS  
BV  
DSS  
t
P
L
V
DS  
I
VARY t TO OBTAIN  
P
AS  
+
-
V
DD  
R
REQUIRED PEAK I  
G
AS  
V
DD  
V
GS  
DUT  
t
P
I
0V  
AS  
0
0.01Ω  
t
AV  
Figure 14. Unclamped Energy Test Circuit  
Figure 15. Unclamped Energy Waveforms  
V
DS  
R
L
V
Q
DD  
g(TOT)  
V
DS  
V
GS  
V
= 4.5V  
GS  
V
GS  
+
-
Q
gs2  
V
DD  
DUT  
V
= 1V  
GS  
I
g(REF)  
0
Q
g(TH)  
Q
Q
gs  
gd  
I
g(REF)  
0
Figure 16. Gate Charge Test Circuit  
Figure 17. Gate Charge Waveforms  
t
t
ON  
OFF  
t
d(OFF)  
R
L
t
d(ON)  
V
t
t
f
DS  
r
V
DS  
+
90%  
90%  
V
GS  
V
GS  
-
0V  
10%  
10%  
0
DUT  
R
GS  
90%  
50%  
V
GS  
50%  
PULSE WIDTH  
10%  
0
Figure 18. Switching Time Test Circuit  
Figure 19. Switching Time Waveforms  
www.fairchildsemi.com  
7
FDW2601NZ Rev. A  
PSPICE Electrical Model  
.SUBCKT FDW2601NZ 2 1 3 ;  
CA 12 8 19.3e-10  
CB 15 14 19.3e-10  
CIN 6 8 1.7e-9  
rev June 2004  
LDRAIN  
DPLCAP  
5
DRAIN  
2
10  
RSLC2  
RLDRAIN  
DBREAK  
DBODY 5 7 DBODYMOD  
DBREAK 7 11 DBREAKMOD  
DPLCAP 10 5 DPLCAPMOD  
DESD1 91 9 DESD1MOD  
DESD2 91 7 DESD2MOD  
EBREAK 5 11 17 18 33.3  
EDS 14 8 5 8 1  
RSLC1  
51  
+
5
ESLC  
11  
51  
-
50  
+
-
17  
18  
-
DBODY  
RDRAIN  
16  
EBREAK  
EGS 13 8 6 8 1  
ESG 6 10 8 6 1  
6
8
ESG  
EVTHRES  
+
+
EVTHRES 6 21 19 8 1  
EVTEMP 6 20 18 22 1  
21  
-
19  
8
MWEAK  
LGATE  
EVTEMP  
+
RGATE  
GATE  
1
9
6
-
18  
22  
IT 8 17 1  
MMED  
20  
MSTRO  
8
RLGATE  
LDRAIN 2 5 1e-9  
DESD1  
91  
DESD2  
LSOURCE  
LGATE 1 9 0.96e-9  
LSOURCE 3 7 0.19e-9  
CIN  
SOURCE  
3
7
RSOURCE  
RLDRAIN 2 5 10  
RLGATE 1 9 9.6  
RLSOURCE 3 7 1.9  
RLSOURCE  
MMED 16 6 8 8 MMEDMOD  
MSTRO 16 6 8 8 MSTROMOD  
MWEAK 16 21 8 8 MWEAKMOD  
S1A  
S1B  
S2A  
RBREAK  
12  
15  
13  
14  
13  
17  
18  
8
RVTEMP  
19  
-
S2B  
RBREAK 17 18 RBREAKMOD 1  
RDRAIN 50 16 RDRAINMOD 8.8e-3  
RGATE 9 20 2.75  
RSLC1 5 51 RSLCMOD 1e-6  
RSLC2 5 50 1e3  
RSOURCE 8 7 RSOURCEMOD 3e-4  
RVTHRES 22 8 RVTHRESMOD 1  
RVTEMP 18 19 RVTEMPMOD 1  
13  
CB  
CA  
IT  
14  
+
+
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
22  
RVTHRES  
S1A 6 12 13 8 S1AMOD  
S1B 13 12 13 8 S1BMOD  
S2A 6 15 14 13 S2AMOD  
S2B 13 15 14 13 S2BMOD  
VBAT 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),2.5))}  
.MODEL DBODYMOD D (IS = 18.6e-12 N=0.93 RS = 6.6e-3 IKF=0.2 TRS1 = 1.7e-3 TRS2 = 2e-6 XTI=0.1 TIKF=0.001  
CJO =5.2e-10 TT=8.7e-9 M = 0.58)  
.MODEL DBREAKMOD D (RS = 1e-1 TRS1 = 9e-3 TRS2 = -2e-5)  
.MODEL DPLCAPMOD D (CJO = 0.76e-9 IS = 1e-30 N = 10 M = 0.58)  
.MODEL DESD1MOD D (BV=10.5 TBV1=-0.0018 N=9.4 RS=5)  
.MODEL DESD2MOD D (BV=10.5 TBV1=-0.0018 N=9.4 RS=5)  
.MODEL MMEDMOD NMOS (VTO = 1.0 KP = 1.7 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.75)  
.MODEL MSTROMOD NMOS (VTO = 1.27 KP = 147 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)  
.MODEL MWEAKMOD NMOS (VTO = 0.83 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 27.5 RS = 0.1)  
.MODEL RBREAKMOD RES (TC1 = 8.8e-4 TC2 = -13e-7)  
.MODEL RDRAINMOD RES (TC1 = 1e-9 TC2 = 1e-5)  
.MODEL RSLCMOD RES (TC1 = 2e-9 TC2 = 5e-8)  
.MODEL RSOURCEMOD RES (TC1 = 8.2e-2 TC2 = 1e-6)  
.MODEL RVTHRESMOD RES (TC1 = -13e-4 TC2 = -2.8e-6)  
.MODEL RVTEMPMOD RES (TC1 = -1.3e-3 TC2 = 1e-6)  
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6 VOFF= -1.5)  
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF= -6)  
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0.3)  
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.3 VOFF= -0.5)  
ENDS  
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global  
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank  
Wheatley.  
www.fairchildsemi.com  
8
FDW2601NZ Rev. A  
SABER Electrical Model  
REV June 2004  
template fdw2601nz n2,n1,n3  
electrical n2,n1,n3  
{
var i iscl  
dp..model dbodymod = (isl = 18.6e-12, nl=0.93, rs = 6.6e-3, trs1 = 1.7e-3, trs2 = 2e-6, xti=0.1, cjo = 5.2e-10, ikf=0.2, tt = 8.7e-9,  
m = 0.58, tikf=0.001)  
dp..model dbreakmod = (rs = 1e-1, trs1 = 9e-3, trs2 = -2.0e-5)  
dp..model dplcapmod = (cjo = 0.76e-9, isl=10e-30, nl=10, m=0.58)  
dp..model desd1mod = (bv=10.5, tbv1=-0.0018, nl=9.4, rs=5)  
dp..model desd2mod = (bv=10.5, tbv1=-0.0018, nl=9.4, rs=5)  
m..model mmedmod = (type=_n, vto = 1.0, kp=1.7, is=1e-30, tox=1)  
m..model mstrongmod = (type=_n, vto = 1.27, kp = 147, is = 1e-30, tox = 1)  
m..model mweakmod = (type=_n, vto = 0.83, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)  
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6, voff = -1.5)  
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -1.5, voff = -6 )  
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3)  
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5)  
LDRAIN  
DPLCAP  
5
DRAIN  
2
10  
RLDRAIN  
RSLC1  
51  
RSLC2  
c.ca n12 n8 = 19.3e-10  
c.cb n15 n14 = 19.3e-10  
c.cin n6 n8 = 1.7e-9  
-
ISCL  
DBREAK  
11  
50  
RDRAIN  
6
8
dp.dbody n7 n5 = model=dbodymod  
dp.dbreak n5 n11 = model=dbreakmod  
dp.dplcap n10 n5 = model=dplcapmod  
dp.desd1 n91 n9 = model=desd1mod  
dp.desd2 n91 n7 = model=desd2mod  
ESG  
DBODY  
EVTHRES  
+
16  
21  
+
-
19  
8
MWEAK  
LGATE  
EVTEMP  
RGATE  
GATE  
1
+
6
-
18  
22  
EBREAK  
+
MMED  
9
20  
DESD1  
91  
MSTRO  
8
17  
18  
-
RLGATE  
spe.ebreak n11 n7 n17 n18 = 33.3  
spe.eds n14 n8 n5 n8 = 1  
LSOURCE  
CIN  
SOURCE  
3
DESD2  
7
spe.egs n13 n8 n6 n8 = 1  
spe.esg n6 n10 n6 n8 = 1  
RSOURCE  
RLSOURCE  
spe.evtemp n20 n6 n18 n22 = 1  
spe.evthres n6 n21 n19 n8 = 1  
S1A  
S2A  
RBREAK  
12  
15  
13  
14  
13  
17  
18  
8
RVTEMP  
19  
S1B  
S2B  
i.it n8 n17 = 1  
13  
CB  
CA  
IT  
14  
-
+
+
l.ldrain n2 n5 = 1e-9  
l.lgate n1 n9 = 0.96e-9  
l.lsource n3 n7 = 0.19e-9  
VBAT  
6
8
5
8
EGS  
EDS  
+
-
-
8
22  
RVTHRES  
res.rldrain n2 n5 = 10  
res.rlgate n1 n9 = 9.6  
res.rlsource n3 n7 = 1.9  
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u  
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u  
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u  
res.rbreak n17 n18 = 1, tc1 = 8.8e-4, tc2 = -13e-7  
res.rdrain n50 n16 = 8.8e-3, tc1 = 1e-9, tc2 = 1e-5  
res.rgate n9 n20 = 2.75  
res.rslc1 n5 n51= 1e-6, tc1 = 2e-9, tc2 =5e-8  
res.rslc2 n5 n50 = 1e3  
res.rsource n8 n7 = 3e-4, tc1 = 8.2e-2, tc2 =1e-6  
res.rvtemp n18 n19 = 1, tc1 = -1.3e-3, tc2 = 1e-6  
res.rvthres n22 n8 = 1, tc1 = -13e-4, tc2 = -2.8e-6  
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod  
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod  
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod  
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod  
v.vbat n22 n19 = dc=1  
equations {  
i (n51->n50) +=iscl  
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/120))** 2.5))  
}
}
www.fairchildsemi.com  
9
FDW2601NZ Rev. A  
SPICE Thermal Model  
REV June 2004  
JUNCTION  
th  
FDW2601NZ_JA Junction Ambient  
Minimum copper pad area  
CTHERM1 Junction c2 5.7e-4  
CTHERM2 c2 c3 5.72e-4  
CTHERM3 c3 c4 5.8e-4  
CTHERM4 c4 c5 4.7e-3  
CTHERM5 c5 c6 5.1e-3  
CTHERM6 c6 c7 0.02  
RTHERM1  
RTHERM2  
RTHERM3  
RTHERM4  
RTHERM5  
RTHERM6  
RTHERM7  
RTHERM8  
CTHERM1  
2
3
CTHERM7 c7 c8 0.2  
CTHERM8 c8 Ambient 6  
CTHERM2  
CTHERM3  
CTHERM4  
CTHERM5  
CTHERM6  
CTHERM7  
CTHERM8  
RTHERM1 Junction c2 0.003  
RTHERM2 c2 c3 0.25  
RTHERM3 c3 c4 1.0  
RTHERM4 c4 c5 1.1  
RTHERM5 c5 c6 7.5  
RTHERM6 c6 c7 33.6  
RTHERM7 c7 c8 33.7  
RTHERM8 c8 Ambient 33.8  
4
5
SABER Thermal Model  
SABER thermal model FDW2601NZ  
Minimum copper pad area  
template thermal_model th tl  
thermal_c th, tl  
6
7
8
{
ctherm.ctherm1 th c2 = 5.7e-4  
ctherm.ctherm2 c2 c3 = 5.72e-4  
ctherm.ctherm3 c3 c4 = 5.8e-4  
ctherm.ctherm4 c4 c5 = 4.7e-3  
ctherm.ctherm5 c5 c6 = 5.1e-3  
ctherm.ctherm6 c6 c7 = 0.02  
ctherm.ctherm7 c7 c8 = 0.2  
ctherm.ctherm8 c8 tl = 6  
rtherm.rtherm1 th c2 = 0.003  
rtherm.rtherm2 c2 c3 = 0.25  
rtherm.rtherm3 c3 c4 = 1.0  
rtherm.rtherm4 c4 c5 = 1.1  
rtherm.rtherm5 c5 c6 = 7.5  
rtherm.rtherm6 c6 c7 = 33.6  
rtherm.rtherm7 c7 c8 = 33.7  
rtherm.rtherm8 c8 tl = 33.8  
}
tl  
AMBIENT  
www.fairchildsemi.com  
10  
FDW2601NZ Rev. A  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not  
intended to be an exhaustive list of all such trademarks.  
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FACT Quiet SeriesImpliedDisconnectPOP™  
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®
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CROSSVOLTFRFET™  
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FAST  
FASTr™  
FPS™  
IntelliMAX™  
ISOPLANAR™  
LittleFET™  
Power247™  
PowerEdge™  
PowerSaver™  
SuperFET™  
SuperSOT-3  
SuperSOT-6  
SuperSOT-8  
SyncFET™  
®
MICROCOUPLERPowerTrench  
®
GlobalOptoisolatorMicroFET™  
QFET  
®
EcoSPARK™  
GTO™  
MicroPak™  
MICROWIRE™  
MSX™  
MSXPro™  
OCX™  
QS™  
TinyLogic  
2
E CMOS™  
HiSeC™  
QT OptoelectronicsTINYOPTO™  
2
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I C™  
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RapidConnect™  
µSerDes™  
SILENT SWITCHER VCX™  
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SPM™  
TruTranslation™  
UHC™  
i-Lo™  
®
UltraFET  
Across the board. Around the world.OCXPro™  
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®
®
®
OPTOLOGIC  
OPTOPLANAR™  
PACMAN™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY  
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY  
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;  
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR  
CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the body,  
or (b) support or sustain life, or (c) whose failure to perform  
when properly used in accordance with instructions for use  
provided in the labeling, can be reasonably expected to  
result in significant injury to the user.  
2. A critical component is any component of a life support  
device or system whose failure to perform can be  
reasonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or In  
Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  
www.fairchildsemi.com  
FDW2601NZ Rev. A  
11  

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