FIN224AC_11 [FAIRCHILD]
22-Bit Bi-Directional Serializer/Deserializer; 22位双向串行器/解串器
| 型号： | FIN224AC_11 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 22-Bit Bi-Directional Serializer/Deserializer |
| 文件： | 总19页 (文件大小：1042K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Click here for this datasheet
translated into Korean!
April 2011
FIN224AC
22ꢀBit BiꢀDirectional Serializer/Deserializer
Features
Description
• Industry smallest 22ꢀbit Serializer/Deserializer pair
The FIN224AC ꢁSerDes™ is a lowꢀpower serializer/
deserializer (SerDes) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred
from one point to another can be significantly reduced.
Typical reduction is 4:1 to 6:1 for unidirectional paths.
For bidirectional operation, using half duplex for multiple
sources, it is possible to reach signal reduction close to
10:1. Through the use of differential signaling, shielding
and EMI filters can also be minimized, further reducing
the cost of serialization. The differential signaling is also
important for providing a noiseꢀinsensitive signal that can
withstand radio and electrical noise sources. Major
reduction in power consumption allows minimal impact
on battery life in ultraꢀportable applications. It is possible
to use a single PLL for most applications including biꢀ
directional operation.
• Low power for minimum impact on battery life
– Multiple powerꢀdown modes
• 100nA in standby mode, 5mA typical operating
conditions
• Highly rolled LVCMOS edge rate option to meet
regulatory requirements
• Cable reduction: 25:4 or greater
• Differential signaling:
––90dBm EMI when using CTL in lab conditions
–Minimized shielding
–Minimized EMI filter
–Minimum susceptibility to external interference
• Up to 22 bits in either direction
• Voltage translation from 1.65V to 3.6V
• High ESD protection: > 15kV HBM
• Parallel I/O power supply (VDDP) range, 1.65V ꢀ 3.6V
• Can support Microcontroller or RGB pixel interface
FIN224AC to FIN24AC Comparison
• Up to 20% power reduction
• Double wide CKP pulse on FIN224AC, Mode 3
Applications
• Rolled edge rate for deserializer outputs on
FIN224AC, for single display applications
• Image sensors
• Small displays
– LCD, cell phone, digital camera, portable gaming,
printer, PDA, video camera, automotive
• Same voltage range
• Same pinout and package
Ordering Information
Operating
Order
Packing
Temperature
Number
Package Description
Method
Range
42ꢀBall, UltraꢀSmall Scale Ball Grid Array (USSꢀBGA),
JEDEC MOꢀ195, 3.5mm Wide (Slow LVCMOS Edge Rate)
FIN224ACGFX
FIN224ACMLX
ꢀ30 to +70°C
ꢀ30 to +70°C
Tape and Reel
Tape and Reel
40ꢀTerminal, Molded Leadless Package (MLP), Quad,
JEDEC MOꢀ220, 6mm Square (Slow LVCMOS Edge Rate)
ꢁSerDesTM is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
Basic Concept
LVCMOS
22
LVCMOS
CTL
4
FIN224AC
Serializer
FIN224AC
Deserializer
22
Figure 1. Conceptual Diagram
Functional Block Diagram
+
-
CKS0+
PLL
0
CKREF
CKS0-
STROBE
I
cksint
Serializer
Control
DP[21:22]
DP[1:20]
DSO+/DSI-
DSO-/DSI+
+
-
Serializer
oe
100 Gated
Termination
+
-
Deserializer
Deserializer
Control
cksint
+
CKSI+
CKSI-
DP[23:24]
-
100
Termination
WORD CK
Generator
CKP
Control Logic
S1
DIRO
Freq
Control
Direction
Control
S2
oe
DIRI
Power Down
Control
Figure 2. Block Diagram
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
2
Terminal Description
Terminal
I/O Type
Name
Number of
Terminals
Description of Signals
DP[1:20]
DP[21:22]
DP[23:24]
CKREF
I/O
I
20
2
LVCMOS parallel I/O, Direction controlled by DIRI pin
LVCMOS parallel unidirectional inputs
O
2
LVCMOS unidirectional parallel outputs
LVCMOS clock input and PLL reference
LVCMOS strobe signal for latching data into the serializer
LVCMOS word clock output
IN
1
STROBE
CKP
IN
1
OUT
1
CTL differential serial I/O data signals(1.)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO+ / DSIꢀ
DSOꢀ / DSI+
DIFFꢀI/O
2
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)ꢀ: Negative signal of DSO(I) pair
CTL differential deserializer input bit clock
CKSI: Refers to signal pair
CKSI+
CKSIꢀ
DIFFꢀIN
2
2
CKSI+: Positive signal of CKSI pair
CKSIꢀ: Negative signal of CKSI pair
CTL differential serializer output bit clock
CKSO: Refers to signal pair
CKSO+
CKSOꢀ
DIFFꢀOUT
CKSO+: Positive signal of CKSO pair
CKSOꢀ: Negative signal of CKSO pair
S1
S2
IN
IN
1
1
LVCMOS mode selection terminals used to select frequency range for
the reflect, CKREF
LVCMOS control input used to control direction of data flow:
DIRI = “1” Serializer
DIRI
IN
1
DIRI = “0” Deserializer
DIRO
VDDP
VDDS
VDDA
GND
OUT
1
1
1
1
2
LVCMOS control output inversion of DIRI
Power supply for parallel I/O and translation circuitry
Power supply for core and serial I/O
Supply
Supply
Supply
Supply
Power supply for analog PLL circuitry
For ground signals (2 for ꢁBGA, 1 for MLP)
Note
:
1. The DSO/DSI serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the
other device, the serial connections properly align without the need for any traces or cable signals to cross. Other
layout orientation may require that traces or cables cross.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
3
Connection Diagrams
1
DP[9]
DP[10]
DP[11]
DP[12]
VDDP
30 DIRO
29 CKSO+
28 CKSO-
27 DSO+
26 DSO-
25 CKSI-
24 CKSI+
23 DIRI
2
3
4
5
6
CKP
7
DP[13]
DP[14]
DP[15]
DP[16]
8
9
22 S2
10
21 VDDS
Figure 3. Terminal Assignments for MLP (Top View)
42 MBGA Package
3.5mm x 4.5mm
(.5mm Pitcth)
(Top View)
Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
DP[9]
DP[11]
CKP
DP[7]
DP[5]
DP[6]
DP[8]
VDDP
GND
DP[3]
DP[2]
DP[4]
GND
DP[1]
CKREF
DIRO
1
2
3
4
5
6
DP[10]
DP[12]
DP[14]
DP[16]
DP[18]
DP[20]
STROBE
CKSO+
A
B
C
D
E
F
CKSOꢀ
DP[13]
DP[15]
DP[17]
DP[19]
DSOꢀ/DSI+ DSO+/DSIꢀ
VDDS
VDDA
DP[23]
CKSI+
S2
CKSIꢀ
DIRI
S1
DP[21]
DP[22]
G
DP[24]
G
Figure 4. Terminal Assignments for ꢁBGA (Top View)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
4
TurnꢀAround Functionality
Control Logic Circuitry
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken by the system designer to ensure that no
contention occurs between the deserializer outputs and
the other devices on this port. Optimally the peripheral
device driving the serializer should be put into a HIGHꢀ
impedance state prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned around into a
deserializer and the values are overwritten.
The FIN224AC has the ability to be used as a 22ꢀbit seriꢀ
alizer or a 22ꢀbit deserializer. Pins S1 and S2 must be
set to accommodate the clock reference input frequency
range of the serializer. Table 1 shows the pin programꢀ
ming of these options based on the S1 and S2 control
pins. The DIRI pin controls whether the device is a serialꢀ
izer or a deserializer. When DIRI is asserted LOW, the
device is configured as a deserializer. When the DIRI pin
is asserted HIGH, the device is configured as a serialꢀ
izer. Changing the state on the DIRI signal reverses the
direction of the I/O signals and generate the opposite
state signal on DIRO. For unidirectional operation the
DIRI pin should be hardwired to the HIGH or LOW state
and the DIRO pin should be left floating. For biꢀdirecꢀ
tional operation, the DIRI of the master device is driven
by the system and the DIRO signal of the master is used
to drive the DIRI of the slave device.
PowerꢀDown Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differꢀ
ential input buffers are shut off, differential output buffers
are placed into a HIGHꢀimpedance state, LVCMOS outꢀ
puts are placed into a HIGHꢀimpedance state, and LVCꢀ
MOS inputs are driven to a valid level internally.
Additionally all internal circuitry is reset. The loss of
CKREF state is also enabled to ensure that the PLL only
powersꢀup if there is a valid CKREF signal.
Serializer/Deserializer with Dedicated I/O Variation
The serialization and deserialization circuitry is set up for
24 bits. Because of the dedicated inputs and outputs,
only 22 bits of data are serialized or deserialized.
DP[21:22] inputs to the serializer are transmitted to
DP[23:24] outputs on the deserializer.
In a typical application mode, signals of the device do not
change states other than between the desired frequency
range and the powerꢀdown mode. This allows for sysꢀ
temꢀlevel powerꢀdown functionality to be implemented
via a single wire for a SerDes pair. The S1 and S2 selecꢀ
tion signals that have their operating mode driven to a
“logic 0” should be hardwired to GND. The S1 and S2
signals that have their operating mode driven to a “logic
1” should be connected to a systemꢀlevel powerꢀdown or
reset signal.
Table 1. Control Logic Circuitry
Mode
S2
S1
DIRI
Description
Number
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
x
1
0
1
0
1
0
PowerꢀDown Mode
22ꢀBit Serializer 2MHz to 5MHz CKREF
22ꢀBit Deserializer
1
2
3
22ꢀBit Serializer 5MHz to 15MHz CKREF
22ꢀBit Deserializer
22ꢀBit Serializer 10MHz to 26MHz CKREF (Divide by 2 Serial Data)
22ꢀBit Deserializer
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
5
Serializer Operation Mode
The serializer configurations are described in the followꢀ
ing sections. The basic serialization circuitry works
essentially identically in these modes, but the actual data
and clock streams differ depending on if CKREF is the
same as the STROBE signal or not. When it is stated
that CKREF does not equal STROBE, each signal is disꢀ
tinct and CKREF must be running at a frequency high
enough to avoid any loss of data condition. CKREF must
never be a lower frequency than STROBE.
The exact frequency that the reference clock needs to
run at depends upon the stability of the CKREF and
STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the minimun
frequency of the spread spectrum clock should be used
in calculating the ratio of STROBE frequency to the
CKREF frequency. Similarly, if the STROBE signal has
significant cycleꢀtoꢀcycle variation, the maximum cycleꢀ
toꢀcycle time needs to be factored into the selection of
the CKREF frequency.
Serializer Operation: MODE 1 or MODE 2,
DIRI = 1, CKREF = STROBE
Serializer Operation: MODE 3 (S1 = S2 =1),
DIRI =1. CKREF Divide by 2 Mode.
The PLL must receive a stable CKREF signal to achieve
lock prior to any valid data being sent. The CKREF sigꢀ
nal can be used as the data STROBE signal provided
that data can be ignored during the PLL lock phase.
When operating in mode 3, the effective serial speed is
divided by two. This mode has been implemented to
accommodate cases where the reference clock freꢀ
quency is high compared to the actual strobe frequency.
The actual strobe frequency must be less than or equal
to 50% of the CKREF frequency for this mode to work
properly. This mode, in all other ways, operates the
same as described in the section where CKREF does
not equal STROBE.
Once the PLL is stable and locked, the device can begin
to capture and serialize data. Data is captured on the risꢀ
ing edge of the STROBE signal and serialized. When
operating in serializer mode, the internal deserializer cirꢀ
cuitry is disabled; including the serial clock, serial data
input buffers, biꢀdirectional parallel outputs, and CKP
word clock. The CKP word clock is driven HIGH.
Serializer Operation: DIRI = 1, No CKREF
A third method of serialization can be acheived by proꢀ
viding a freeꢀrunning bit clock on the CKSI signal. This
mode is enabled by grounding the CKREF signal and
driving the DIRI signal HIGH. At powerꢀup, the device is
configured to accept a serialization clock from CKSI. If a
CKREF is received, this device enables the CKREF seriꢀ
alization mode. The device remains in this mode even if
CKREF is stopped. To reꢀenable this mode, the device
must be powered down and then powered back up with a
“logic 0” on CKREF.
Serializer Operation: DIRI = 1, CKREF Does Not
= STROBE
If the same signal is not used for CKREF and STROBE,
the CKREF signal must be run at a higher frequency
than the STROBE rate to serialize the data correctly. The
actual serial transfer rate remains at 13 times the
CKREF frequency. A data bit value of zero is sent when
no valid data is present in the serial bit stream. The operꢀ
ation of the serializer otherwise remains the same.
Deserializer Operation Mode
The operation of the deserializer is dependent on the
data received on the DSI data signal pair and the CKSI
clock signal pair. The following sections describe the
operation of the deserializer under distinct serializer
source conditions. References to the CKREF and
STROBE signals refer to the signals associated with the
serializer device generating the serial data and clock sigꢀ
nals that are inputs to the deserializer. When operating in
deserializer mode, the internal serializer circuitry is disꢀ
abled, including the parallel data input buffers. If there is
a CKREF signal provided, the CKSO serial clock continꢀ
ues to transmit bit clocks. Upon powerꢀup (S1 or S2 = 1),
deserializer output data pins are driven LOW until valid
data is passed through the deserializer.
serial port and deserialized through use of the bit clock
sent with the data.
Deserializer Operation: DIRI = 0 (Serializer
Source: CKREF Does Not = STROBE)
The logical operation of the deserializer remains the
same if the CKREF is equal in frequency to the STROBE
or at a higher frequency than the STROBE. The actual
serial data stream presented to the deserializer is differꢀ
ent because it has nonꢀvalid data bits sent between
words. The duty cycle of CKP varies based on the ratio
of the frequency of the CKREF signal to the STROBE
signal. The frequency of the CKP signal is equal to the
STROBE frequency. In modes 1 and 2, the CKP LOW
time equals half of the CKREF period of the serializer. In
mode 3, the CKP LOW is equal to the CKREF period.
The CKP HIGH time is approximately equal to the
STROBE period, minus the CKP LOW time.
Deserializer Operation: DIRI = 0 (Serializer
Source: CKREF = STROBE)
When the DIRI signal is asserted LOW, the device is
configured as a deserializer. Data is captured on the
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
6
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold
value equal to half VDD. The input buffers are only operꢀ
ational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
The LVCMOS 3ꢀSTATE output buffers are rated for a
source / sink current of approximately 0.5mA at 1.8V.
The outputs are active when the DIRI signal and either
S1 or S2 is asserted HIGH. When the DIRI signal and
either S1 or S2 is asserted LOW, the biꢀdirectional LVCꢀ
MOS I/Os is in a HIGHꢀZ state. Under purely capacitive
load conditions, the output swings between GND and
V
DDP. When S1 or S2 initially transitions HIGH, the initial
state of the deserializer LVCMOS outputs is zero.
Unused LVCMOS input buffers must be either tied off to
a valid logic LOW or a valid logic HIGH level to prevent
static current draw due to a floating input. Unused LVCꢀ
MOS output should be left floating. Unused biꢀdirectional
pins should be connected to GND through a highꢀvalue
resistor. If a FIN224AC device is configured as an unidiꢀ
rectional serializer, unused data I/O can be treated as
unused inputs. If the FIN224AC is hardwired as a deseriꢀ
alizer, unused data I/O can be treated as unused outputs.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
7
Application Mode Diagrams
SerDesSerializer
SerDes Deserializer
U20
FIN224AC
U22
FIN224AC
TP6
VDDP
A6
B5
PIXCLK_M
CKREF
STROBE
J6
F5
F6
S1
S2
DIRI
F6
F5
J6
DIRI
S2
S1
TP5
GPIO_MODE
C1
PIXCLK_S
CKP
J5
J4
J3
F3
J2
J1
J5
J4
J3
F3
J2
J1
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
LCD_ENABLE_S
B5
A6
STROBE
CKREF
LCD_ENABLE_M
LCD_VSYNC_M
LCD_HSYNC_M
LCD17_M
B6
C1
LCD_VSYNC_S
LCD_HSYNC_S
LCD17_S
LCD16_S
LCD15_S
DIRO
CKP
B6
DIRO
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
LCD16_M
LCD15_M
LCD14_M
LCD13_M
LCD14_S
LCD13_S
D6
D5
D5
D6
DSO+/DSI-
DSO-/DSI+
DSO-/DSI+
DSO+/DSI-
LCD12_M
LCD11_M
LCD12_S
LCD11_S
LCD
Controller
Out
LCD
Display
In
C6
C5
E6
E5
LCD10_M
LCD9_M
LCD8_M
LCD7_M
LCD6_M
LCD5_M
LCD4_M
LCD3_M
LCD2_M
LCD1_M
LCD0_M
LCD10_S
LCD9_S
LCD8_S
LCD7_S
LCD6_S
LCD5_S
LCD4_S
LCD3_S
LCD2_S
LCD1_S
LCD0_S
CKSO-
CKSO+
CKSI-
CKSI+
E6
E5
C6
C5
CKSI-
CKSI+
CKSO-
CKSO+
2.8V
2.8V
1.8V
2.8V
F4
E4
D3
F4
E4
D3
VDDA
VDDS
VDDP
VDDA
VDDS
VDDP
C12
.01µuF
C10
1nF
C11
C6
1nF
C3
.01µuF
2.2uµF
Assumptions:
1) 18-bit Unidirectional RGB Application
2) Mode 3 Operation (10 Mhzto 20Mhz CKREF)
3) VDDP = (1.65Vto 3.6V)
Figure 5. FIN224AC RGB
SerDes Serializer
SerDes Deserializer
U21
FIN224AC
U23
FIN224AC
TP2
TP1
VDDP
A6
B5
REFCLK
LCD_/WRITE_ENABLE_M
CKREF
STROBE
J6
F5
F6
S1
S2
DIRI
F6
F5
J6
DIRI
S2
S1
TP3
GPIO_MODE
C1
LCD_/WRITE_ENABLE_S
CKP
J5
J4
J3
F3
J2
J1
J5
J4
J3
F3
J2
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
B5
A6
STROBE
CKREF
B6
C1
LCD_/CS_M
LCD_/CS_S
LCD_ADDRESS_S
LCD17_S
LCD16_S
LCD15_S
LCD14_S
LCD13_S
LCD12_S
LCD11_S
DIRO
CKP
B6
J1
LCD_ADDRESS_M
LCD17_M
LCD16_M
LCD15_M
LCD14_M
LCD13_M
LCD12_M
LCD11_M
LCD10_M
DIRO
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
D6
D5
D5
D6
DSO+/DSI-
DSO-/DSI+
DSO-/DSI+
DSO+/DSI-
LCD
C6
C5
E6
E5
LCD10_S
LCD9_S
LCD8_S
Controller
Out
CKSO-
CKSO+
CKSI-
CKSI+
LCD
Display
In
LCD9_M
LCD8_M
LCD7_M
LCD6_M
LCD5_M
LCD4_M
LCD3_M
LCD2_M
LCD1_M
LCD0_M
E6
E5
C6
C5
LCD7_S
LCD6_S
LCD5_S
LCD4_S
LCD3_S
LCD2_S
LCD1_S
LCD0_S
CKSI-
CKSI+
CKSO-
CKSO+
2.8V
2.8V
1.8V
2.8V
F4
E4
D3
F4
E4
D3
VDDA
VDDS
VDDP
VDDA
VDDS
VDDP
C9
.01FuF
C7
1nF
C8
C5
1nF
C2
.01FuF
2.2uFF
Assumptions:
1) 18-bit Unidirectional Controller Application
2) Mode 3 Operation (10 Mhz to 20Mhz CKREF)
3) VDDP= (1.65V to 3.6V)
4) REFCLK is a continously running clock with a frequency
greater than /WRITE_ENABLE.
Figure 6. FIN224AC Microcontroller
Flex Circuit Design Guidelines
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex
cable. The following best practices should be used when developing the flex cabling or Flex PCB:
Keep all four differential wires the same length.
Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires.
Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
Do not place test points on differential serial wires.
Use differential serial wires a minimum of 2cm away from the antenna.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
8
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operaꢀ
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addiꢀ
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
ꢀ0.5
Max.
+4.6
+4.6
Unit
V
V
Supply Voltage
DD
ALL Input/Output Voltage
ꢀ0.5
V
I
CTL Output ShortꢀCircuit Duration
Storage Temperature Range
Continuous
ꢀ65
OS
T
+150
+150
+260
15.0
8.0
°C
°C
°C
STG
T
Maximum JunctionTemperature
Lead Temperature (Soldering 4 Seconds)
IEC61000ꢀ4ꢀ2
J
T
L
Human Body Model, JESD22ꢀA114, Serial I/O Pin
Human Body Model, JESD22ꢀA114, All Pins
Charged Device Model, JESD22ꢀC101
ESD
kV
2.5
2.0
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
, V
Parameter
Min.
2.5
Max.
3.3
Unit
V
V
Supply Voltage
DDA
DDS
V
Supply Voltage
1.65
ꢀ30
3.60
+70
100
V
DDP
(2.)
T
Operating Temperature
Supply Noise Voltage
°C
A
V
mV
PP
DDAꢀPP
Note
:
2. Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired.
The datasheet specification should be met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside
datasheet specifications.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
9
DC Electrical Characteristics
Values are for overꢀsupply voltage and operating temperature ranges, unless otherwise specified. Typical values are
given for V = 2.775V and T = 25°C. Positive current values refer to the current flowing into the device and negative
DD
A
values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless otherwise specified
(except and V ).
∆
V
OD
OD
Symbol
LVCMOS I/O
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
Input High Voltage
Input Low Voltage
0.65 x V
V
DDP
IH
DDP
V
GND
0.35 x V
V
V
IL
DDP
V
V
V
V
V
V
= 3.3±0.30
= 2.5±ꢀ0.20
= 1.8±0.18
= 3.3±0.30
= 2.5±0.20
= 1.8±0.18
DDP
DDP
DDP
DDP
DDP
DDP
V
Output High Voltage
I
I
= 2.0mA
= 2.0mA
0.75 x V
DDP
OH
OH
V
Output Low Voltage
Input Current
0.25 x V
5.0
V
OL
OL
DDP
I
V
= 0V to 3.6V
ꢀ5.0
ꢁA
IN
IN
DIFFERENTIAL I/O
Output HIGH source current V = 1.0V
I
ꢀ1.75
0.950
mA
mA
mA
ꢁA
ODH
OS
I
Output LOW sink current
V = 1.0V
OS
ODL
Driver Enabled
Driver Disabled
ShortꢀCircuit Output
Current
V
= 0V
OUT
I
OS
±5
±5
Disabled Output
Leakage Current
CKSO, DSO = 0V to V
S2 = S1 = 0V
DDS
I
±1
ꢁA
ꢁA
ꢁA
OZ
Differential Input Threshold
High Current
I
50
TH
Differential Input Threshold
Low Current
I
ꢀ50
±5
TL
Disabled Input Leakage
Current
CKSI, DSI = 0V to V
S2 = S1 = 0V
DDS
I
±1
ꢁA
mA
V
IZ
I
ShortꢀCircuit Input Current
V
= V
DDS
IS
OUT
DDS
Input Common Mode
Range
V
V
= 2.775 ±5%
0.5
V
DDSꢀ1
ICM
CKSI, DS Internal Receiver V = 50mV, V = 925mV, DIRI = 0
ID
IC
R
100
Ω
+
–
TRM
Termination Resistor
| CKSI – CKSI | = V
ID
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
10
Power Supply Currents
Typical values are given for V = 2.775V and T = 25°C. Positive current values refer to the current flowing into the
DD
A
device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless
otherwise specified (except and V ).
∆
V
OD
OD
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
VDDA Serializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1
IDDA1
450
550
4
ꢁA
ꢁA
mA
mA
ꢁA
VDDA Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0
IDDA2
IDDS1
IDDS2
IDD_PD
VDDS Serializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1
VDDS Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0
4.5
0.1
VDD PowerꢀDown Supply Current
IDD_PD = IDDA
S1 = S2 = 0 All Inputs at GND or VDD
1.2MHz
S2 = 0
9
14
9
S1 = 1
5MHz
26:1 Dynamic Serializer
5MHz
CKREF = STROBE S2 = 1
IDD_SER1 Power Supply Current
IDD_SER1 = IDDA+IDDS+IDDP
mA
DIRI = H
S1 = 0
15MHz
10MHz
26MHz
2MHz
17
9
S2 = 1
S1 = 1
16
5
S2 = 0
S1 = 1
5MHz
6
26:1 Dynamic Deserializer
IDD_DES1 Power Supply Current
IDD_DES1 = IDDA+IDDS+IDDP
5MHz
4
CKREF = STROBE S2 = 1
mA
DIRI = L
S1 = 0
15MHz
10MHz
26MHz
2MHz
5
7
S2 = 1
S1 = 1
11
8
NO CKREF
STROBE Active
CKSI = 15x STROBE
DIRI = H
26:1 Dynamic Serializer
IDD_SER2 Power Supply Current
IDD_SES2 = IDDA+IDDS+IDDP
5MHz
8
mA
10MHz
15MHz
10
12
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
11
AC Electrical Characteristics
Characteristics at recommended overꢀsupply voltage and operating temperature ranges, unless otherwise specified.
Typical values are given for V
= 2.775V and T = 25°C. Positive current values refer to the current flowing into
DD
A
device and negative values means current flowing out of the pins. Voltages are referenced to GROUND unless otherꢀ
wise specified (except
∆
V
and V ).
OD OD
Symbol
Parameter
Test Conditions
Min.
Typ.
Max. Unit
Serializer Input Operating Conditions
S2=0 S1=1
200
66
500
CKREF Clock Period
tTCP
CKREF = STROBE
Figure 7.
S2=1 S1=0
S2=1 S1=1
200
ns
(2MHz – 26MHz)
38.46
100.00
CKREF Frequency Relative to
STROBE
CKREF does not =
STROBE
2.25 x
fSTROBE
fREF
S2=0 S1=1
MHz
tCPWH
tCPWL
tCLKT
CKREF Clock High Time
0.2
0.2
0.5
0.5
T
T
CKREF Clock Low Time
LVCMOS Input Transition Time
STROBE Pulse Width HIGH/LOW
Figure 9.
Figure 9.
90.0
(Tx22)/26
130
ns
ns
tSPWH
(Tx4)/26
52
S2=0 S1=1
S2=1 S1=0
S2=1 S1=1
fMAX
Maximum Serial Data Rate
CKREF x 26
DIRI = 1
Mb/s
130
260
2.5
390
676
tSTC
tHTC
DP(n) Setup to STROBE
DP(n) Hold to STROBE
ns
ns
2.0
Serializer AC Electrical Characteristics
Transmitter Clock Input to Clock
Output Delay
tTCCD
CKREF = STROBE
33a+1.5
ꢀ50
35a+6.5
250
ns
ps
tSPOS
CKSO Position Relative to DS(3.)
PLL AC Electrical Characteristics
Serializer Phase Lock Loop
tTPLLS0
Figure 11.
200
ꢁs
Stabilization Time
tTPLLD0 PLL Disable Time Loss of Clock
tTPLLD1 PLL PowerꢀDown Time(4.)
Figure 12.
Figure 13.
30
20
ꢁs
ns
Deserializer Input Operating Conditions
Serial Port Setup Time,
tS_DS
1.4
ns
ps
DSꢀtoꢀCKSI(5.)
Serial Port Hold Time,
tH_DS
ꢀ250
DSꢀtoꢀCKS(5.)
Deserializer AC Electrical Characteristics
Deserializer Clock Output
tRCOP
Figure 10.
50
500
ns
(CKP OUT) Period(6.)
tRCOL
tRCOH
CKP OUT Low Time(6.)
CKP OUT High Time
(Rising Edge STROBE) Serializer
source STROBE = CKREF
Figure 10.
13aꢀ3
13aꢀ3
13a+3
13a+3
ns
ns
(Rising Edge STROBE)
Figure 10.
tPDV
tROLH
tROHL
Data Valid to CKP LOW
8aꢀ6
8a+1
ns
ns
ns
CL = 8pF
Figure 7.
Output Rise Time (20% to 80%)
Output Fall Time (20% to 80%)
18
18
CL = 8pF
Figure 7.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
12
Notes
:
3. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
4. The powerꢀdown time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies
dependent upon the operating mode of the device.
5. Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when
the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI
and jitter effects.
6. a = (1/f)/13) Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling
edge of CKP occurs approximately eight bit times after a data transition or six bit times after the falling edge of
CKSO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the
data and CKP path and propagation delay differences on the various data pins. Note that if the CKREF is not equal
to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13
bit times.
Control Logic Timing Controls
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
t
t
,
Propagation Delay
DIRIꢀtoꢀDIRO
PHL_DIR
DIRI LOWꢀtoꢀHIGH or HIGHꢀtoꢀLOW
17
25
25
ns
ns
ns
PLH_DIR
Propagation Delay
DIRIꢀtoꢀDP
t
t
, t
DIRI LOWꢀtoꢀHIGH
DIRI HIGHꢀtoꢀLOW
PLZ PHZ
Propagation Delay
DIRIꢀtoꢀDP
, t
PZL PZH
DIRI = 0,
Deserializer Disable Time:
S0 or S1 to DP
t
t
t
t
, t
S1(2) = 0 and S2(1) = LOWꢀtoꢀHIGH,
Figure 14.
25
2
ns
ꢁs
ns
ns
PLZ PHZ
(7.)
DIRI = 0,
Deserializer Enable Time:
S0 or S1 to DP
, t
S1(2) = 0 and S2(1) = LOWꢀtoꢀHIGH
Figure 14.
PZL PZH
DIRI = 1,
Serializer Disable Time:
S0 or S1 to CKSO, DS
, t
S1(2) = 0 and S2(1) = HIGHꢀtoꢀLOW,
Figure 13.
25
65
PLZ PHZ
DIRI = 1,
Serializer Enable Time:
S0 or S1 to CKSO, DS
, t
S1(2) and S2(1) = LOWꢀtoꢀHIGH,
Figure 13.
PZL PZH
Note
:
7. Deserializer Enable Time includes the time required for internal voltage and current references to stabilize. This time
is significantly less than the PLL Lock Time and therefore does not limit overall system startup time.
Capacitance
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
Capacitance of Input Only Signals, DIRI = 1, S1 = S2 = 0,
C
2
2
2
pF
pF
pF
IN
IO
CKREF, STROBE, S1, S2, DIRI = 2.5V
V
DD
Capacitance of Parallel Port Pins DIRI = 1, S1 = S2 = 0,
DP = 2.5V
C
V
1:12
DD
Capacitance of Differential I/O
Signals
DIRI = 0, S1 = S2 = 0,
C
IOꢀDIFF
V
= 2.775V
DD
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
13
AC Loading and Waveforms
Setup Time
t
STC
STROBE
DP[1:12]
t
t
ROHL
ROLH
80%
80%
Data
20%
20%
DPn
t
Hold Time
HTC
DPn
STROBE
DP[1:12]
Data
8pF
Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1”
Figure 7. LVCMOS Output Load and Transition
Times
Figure 8. Serial Setup and Hold Times
Data Time
t
PDV
t
t
CLKT
CLKT
90%
90%
CKP
Data
DP[1:12]
10%
10%
t
RCOP
t
TCP
75%
50%
25%
50%
CKREF
V
IH
CKREF
50%
50%
V
IL
t
t
RCOL
RCOH
t
t
CPWL
CPWH
EN_DES = “1”, CKSI and DSI are valid signals
Setup:
Figure 9. LVCMOS Clock Parameters
Figure 10. Deserializser Data Valid Window Time and
Clock Output Parameters
tTPLLS0
VDD/VDDA
S1 or S2
CKREF
CKS0
Note: CKREF Signal is free running.
Figure 11. Serializer PLL Lock Time
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
14
AC Loading and Waveforms (Continued)
t
TPPLD0
CKREF
CKS0
Note: CKREF Signal can be stopped either High or LOW
Figure 12. PLL Loss of Clock Disable Time
t
t
PZL(ZH)
PLZ(HZ)
S1 or S2
t
TPPLD1
DS+,CKS0+
S1 or S2
CKS0
HIGHZ
DS+,CKS0-
Note: CKREF must be active and PLL must be stable
Figure 13. PLL PowerꢀDown Time
Figure 14. Serializer Enable and Disable Time
t
t
PLZ(HZ)
PZL(ZH)
S1 or S2
DP
Note: If S1(2) transitioning then S2(1) must = 0 for test to be valid
Figure 15. Deserializer Enable and Disable Times
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
15
Tape and Reel Specification
MLP Embossed Tape Dimension
Dimensions are in millimeters.
D
P
0
P
2
T
E
F
K
0
W
W
c
B
0
Tc
A
0
D
1
P
1
User Direction of Feed
A0
B0
D
D1
E
F
K0
P1
P0
P2
T
TC
W
WC
Package ±0.1 ±0.1 ±0.05 Min. ±0.1 ±0.1 ±0.1 Typ. Typ. ±0/05 Typ. ±0.005 ±0.3 Typ.
5 x 5
6 x 6
5.35 5.35 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30
6.30 6.30 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30
0.07 12.00 9.30
0.07 12.00 9.30
Notes
:
Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RSꢀ481 rotational and lateral movement
requirements (see sketches A, B, and C).
Shipping Reel Dimension
Dimensions are in millimeters.
1.0mm
maximum
10° maximum
Typical component
cavity center line
1.0mm
maximum
B0
Typical component
center line
10°maximum component rotation
Sketch A (Side or Front Sectional View)
Sketch C (Top View)
A0
Sketch B (Top View)
Component Rotation
Component lateral movement
Component Rotation
W1 Measured at Hub
W2 max Measured at Hub
B Min
Dia C
Dia D
min
Dia A
max
Dia N
DETAIL AA
See detail AA
W3
Tape
Width
Dia A
Max.
Dim B
Min.
Dia C
+0.5/–0.2
Dia D
Min.
Dim N
Min.
Dim W1
+2.0/–0
Dim W2
Max.
Dim W3
(LSL–USL)
8
330.0
330.0
330.0
1.5
1.5
1.5
13.0
13.0
13.0
20.2
20.2
20.2
178.0
178.0
178.0
8.4
14.4
18.4
22.4
7.9 ~ 10.4
11.9 ~ 15.4
15.9 ~ 19.4
12
16
12.4
16.4
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
16
Physical Dimensions
0.15
C
6.00
B
A
(0.80)
6.00
PIN #1 IDENT
6.38MIN
4.37MAX
0.15
C
4.77MIN
0.80 MAX
0.10
C
(0.20)
C
0.20MIN
X4
0.08
C
0.05
0.00
0.28 MAX
X40
0.50TYP
SEATING
PLANE
E
4.20
4.00
0.50
0.30
0.50
4.20
4.00
(DATUM B)
PIN #1 ID
(DATUM A)
0.18ꢀ0.30
0.10
0.05
C
C
A B
0.50
NOTES:
A. CONFORMS TO JEDEC REGISTRATION MOꢀ220, VARIATION
WJJDꢀ2 WITH EXCEPTION THAT THIS IS A SAWN VERSION..
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5Mꢀ1994.
D. LAND PATTERN PER IPC SMꢀ782.
E. WIDTH REDUCED TO AVOID SOLDER BRIDGING.
F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR
TIE BAR PROTRUSIONS.
G. DRAWING FILENAME: MKTꢀMLP40Arev3.
Figure 16. 40ꢀTerminal, Molded Leadless Package (MLP), Quad, JEDEC MO0220, 6mm Square
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
17
Physical Dimensions (Continued)
2X
0.10
C
3.50
2X
(0.35)
(0.5)
0.10
C
(0.6)
2.5
(0.75)
TERMINAL
A1 CORNER
INDEX AREA
4.50
3.0
0.5
0.5
Ø0.3±0.05
X42
BOTTOM VIEW
0.15
C
C
A B
0.05
0.89±0.082
0.45±0.05
(QA CONTROL VALUE)
1.00 MAX
0.21±0.04
0.10
C
0.08
C
+0.1
0.2
C
0.23±0.05
ꢀ0.0
SEATING PLANE
LAND PATTERN
RECOMMENDATION
Figure 17. 42ꢀBall, Ultra Small Scale Ball Grid Array (USSꢀBGA), JEDEC MOꢀ195, 3.5mm Wide
Note: Click here for tape and reel specifications, available at:
http://www.fairchildsemi.com/products/analog/packaging/bga42.html.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
18
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.6
www.fairchildsemi.com
19
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