FIN3385MTD [FAIRCHILD]
Low Voltage 28-Bit Flat Panel Display Link Serializers; 低电压28位平板显示器连接串行器
| 型号： | FIN3385MTD |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low Voltage 28-Bit Flat Panel Display Link Serializers |
| 文件： | 总9页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2003
Revised January 2004
FIN3385 • FIN3383
Low Voltage 28-Bit Flat Panel Display Link Serializers
General Description
Features
The FIN3385 and FIN3383 transform 28 bit wide parallel
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
steam over a separate LVDS link. Every cycle of transmit
clock 28 bits of input LVTTL data are sampled and trans-
mitted.
■ Low power consumption
■ 20 MHz to 85 MHz shift clock support
■ ±1V common-mode range around 1.2V
■ Narrow bus reduces cable size and cost
■ High throughput (up to 2.38 Gbps throughput)
■ Internal PLL with no external component
■ Compatible with TIA/EIA-644 specification
These chipsets are an ideal solution to solve EMI and
cable size problems associated with wide and high-speed
TTL interfaces.
■ Devices are offered in 48- and 56-lead TSSOP
packages
Ordering Code:
Order Number Package Number
Package Description
FIN3383MTD
FIN3385MTD
MTD56
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
TABLE 1. Display Panel Link Serializers/De-Serializers Chip Matrix
Part
CLK Frequency LVTTL IN
LVDS OUT
Package
56 TSSOP
56 TSSOP
FIN3385
FIN3383
85
66
28
28
4
4
Block Diagram
Functional Diagram for FIN3385 and FIN3383
© 2004 Fairchild Semiconductor Corporation
DS500864
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Pin Descriptions
Pin Names I/O Type Number of Pins
Description of Signals
LVTTL Level Inputs
TxIn
I
I
28/21
1
TxCLKIn
LVTTL Level Clock Input
The rising edge is for data strobe.
TxOut+
TxOut−
O
O
O
O
I
4/3
4/3
1
Positive LVDS Differential Data Output
Negative LVDS Differential Data Output
Positive LVDS Differential Clock Output
Negative LVDS Differential Clock Output
Rising Edge Clock (HIGH), Falling Edge Clock (LOW)
TxCLKOut+
TxCLKOut−
R_FB
1
1
PwrDn
I
1
LVTTL Level Power-Down Input
Assertion (LOW) puts the outputs in High Impedance state.
PLL VCC
PLL GND
LVDS VCC
LVDS GND
VCC
I
I
I
I
I
I
1
2
1
3
3
5
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Outputs
Ground Pins for LVDS Outputs
Power Supply Pins for LVTTL Inputs
Ground pins for LVTTL Inputs
No Connect
GND
NC
Connection Diagram
Truth Table
Inputs
Outputs
PwrDn
(Note 1)
TxIn
TxCLKIn
TxOut± TxCLKOut±
Active
Active
L/H/Z
Active
F
H
H
H
H
L
L/H
L/H
L
L/H
X (Note 2)
L/H
Active
F
F
X
L
X (Note 2)
Z
X
Z
H = HIGH Logic Level
L = LOW Logic Level
X = Don’t Care
Z = High Impedance
F = Floating
Note 1: The outputs of the transmitter or receiver will remain in a
High Impedance state until VCC reaches 2V.
Note 2: TxCLKOut± will settle at a free running frequency when the
part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic
level (L/H/Z).
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2
Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions
Power Supply Voltage (VCC
)
-0.3V to +4.6V
−0.5V to +4.6V
-0.3V to +4.6V
Continuous
TTL/CMOS Input/Output Voltage
LVDS Input/Output Voltage
Supply Voltage (VCC
)
3.0V to 3.6V
Operating Temperature (TA)(Note 3)
Maximum Supply Noise Voltage
−10°C to +70°C
LVDS Output Short Circuit Current (IOSD
)
Storage Temperature Range (TSTG
)
−65°C to +150°C
150°C
(VCCNPP
)
100 mVP-P (Note 4)
Maximum Junction Temperature (TJ)
Lead Temperature (TL)
(Soldering, 4 seconds)
ESD Rating (HBM, 1.5 kΩ, 100 pF)
I/O to GND
Note 3: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
260°C
>10.0 kV
>6.5 kV
>400V
All Pins
Note 4: 100mV VCC noise should be tested for frequency at least up to
2 MHz. All the specification below should be met under such a noise.
ESD Rating (MM, 0Ω, 200 pF)
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 5)
Symbol Parameter Test Conditions
Transmitter LVTTL Input Characteristics
Min
Typ
Max
Units
VIH
VIL
VIK
IIN
Input High Voltage
Input Low Voltage
Input Clamp Voltage
Input Current
2.0
VCC
0.8
V
V
V
GND
I
IK = −18 mA
−0.79
1.8
0
−1.5
10.0
V
IN = 0.4V to 4.6V
IN = GND
µA
V
−10.0
250
Transmitter LVDS Output Characteristics (Note 6)
VOD
∆VOD
VOS
Output Differential Voltage
TBD
1.25
450
35.0
mV
mV
V
VOD Magnitude Change from Differential LOW-to-HIGH
Offset Voltage
R
L = 100 Ω, See Figure 1
1.125
1.375
∆VOS
IOS
Offset Magnitude Change from Differential LOW-to-HIGH
Short Circuit Output Current
mV
mA
V
OUT = 0V
−3.5
±1.0
−5.0
IOZ
Disabled Output Leakage Current
DO = 0V to 4.6V, PwrDn = 0V
±10.0
µA
Transmitter Supply Current
ICCWT
28:4 Transmitter Power Supply Current
32.5 MHz
31.0
32.0
37.0
42.0
49.5
55.0
60.5
66.0
for Worst Case Pattern (With Load)
(Note 7)
R
L = 100 Ω,
40.0 MHz
66.0 MHz
85.0 MHz
mA
See Figure 2
ICCPDT
ICCGT
Powered Down Supply Current
28:4 Transmitter Supply Current
for 16 Grayscale (Note 7)
PwrDn = 0.8V
10.0
29.0
30.0
35.0
39.0
55.0
41.8
44.0
49.5
55.0
µA
32.5 MHz
40.0 MHz
65.0 MHz
85.0 MHz
See Figure 11
(Note 8)
mA
Note 5: All Typical values are at TA = 25°C and with VCC = 3.3V.
Note 6: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to
ground unless otherwise specified (except ∆VOD and VOD).
Note 7: The power supply current for both transmitter and receiver can be different with the number of active I/O channels.
Note 8: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical strips across the display.
3
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AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified.
Symbol Parameter Test Conditions
tTCP Transmit Clock Period
Min
11.76
0.35
0.35
1.0
Typ
T
Max
50.0
0.65
0.65
6.0
Units
ns
T
tTCH
tTCL
tCLKT
tJIT
Transmit Clock (TxCLKIn) HIGH Time
Transmit Clock Low Time
See Figure 4
0.5
0.5
T
TxCLKIn Transition Time (Rising and Failing)
TxCLKIn Cycle-to-Cycle Jitter
TxIn Transition Time
(10% to 90%) See Figure 5
ns
ns
ns
3.0
tXIT
1.5
6.0
LVDS Transmitter Timing Characteristics
tTLH
Differential Output Rise Time (20% to 80%)
0.75
0.75
1.5
1.5
ns
ns
ns
ns
ns
See Figure 3
tTHL
Differential Output Fall Time (80% to 20%)
TxIn Setup to TxCLNIn
tSTC
tHTC
tTPDD
tTCCD
2.5
0
See Figure 4 (f = 85 MHz)
TxIn Holds to TCLKIn
Transmitter Power-Down Delay
See Figure 7, (Note 9)
(TA = 25°C and with VCC = 3.3V)
See Figure 6
100
5.5
6.8
Transmitter Clock Input to Clock Output Delay
Transmitter Clock Input to Clock Output Delay
ns
2.8
Transmitter Output Data Jitter (f = 40 MHz) (Note 10)
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
−0.25
0
0.25
ns
ns
ns
ns
ns
ns
ns
See Figure 9
a−0.25
a
a+0.25
1
a =
2a−0.25
3a−0.25
4a−0.25
5a−0.25
6a−0.25
2a
3a
4a
5a
6a
2a+0.25
3a+0.25
4a+0.25
5a+0.25
6a+0.25
f x 7
Transmitter Output Data Jitter (f = 65 MHz) (Note 10)
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
−0.2
0
0.2
ns
ns
ns
ns
ns
ns
ns
See Figure 9
a−0.2
a
a+0.2
1
a =
2a−0.2
3a−0.2
4a−0.2
5a−0.2
6a−0.2
2a
3a
4a
5a
6a
2a+0.2
3a+0.2
4a+0.2
5a+0.2
6a+0.2
f x 7
Transmitter Output Data Jitter (f = 85 MHz) (Note 10)
tTPPB0
tTPPB1
tTPPB2
tTPPB3
tTPPB4
tTPPB5
tTPPB6
tJCC
Transmitter Output Pulse Position of Bit 0
Transmitter Output Pulse Position of Bit 1
Transmitter Output Pulse Position of Bit 2
Transmitter Output Pulse Position of Bit 3
Transmitter Output Pulse Position of Bit 4
Transmitter Output Pulse Position of Bit 5
Transmitter Output Pulse Position of Bit 6
FIN3385 Transmitter Clock Out Jitter
(Cycle-to-Cycle)
−0.2
0
a
0.2
ns
ns
ns
ns
ns
ns
ns
See Figure 9
a−0.2
a+0.2
2a+0.2
3a+0.2
4a+0.2
5a+0.2
6a+0.2
370
1
a =
2a−0.2
3a−0.2
4a−0.2
5a−0.2
6a−0.2
2a
3a
4a
5a
6a
350
210
110
f x 7
f = 40 MHz
f = 65 MHz
230
ps
See Figure 10
f = 85 MHz
150
tTPLLS
Transmitter Phase Lock Loop Set Time (Note 11)
See Figure 12, (Note 10)
10.0
ms
Note 9: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after VCC reaches 3V and
Power-Down pin is above 1.5V.
Note 10: This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 8). Figure 9 shows the skew
between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter.
Note 11: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns.
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4
FIGURE 1. Differential LVDS Output DC Test Circuit
AC Loading and Waveforms
Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of
transmitter, the TxCLKIn can be either rising or falling edge data strobe.
FIGURE 2. “Worst Case” Test Pattern
FIGURE 3. Transmitter LVDS Output Load and Transition Times
FIGURE 4. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe)
5
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AC Loading and Waveforms (Continued)
FIGURE 5. Transmitter Input Clock Transition Time
FIGURE 6. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe)
FIGURE 7. Transmitter Power-Down Delay
Note: The information in this diagram shows the relationship between clock out and the first data bit. A 2-bit cycle delay is guaranteed when the MSB is out-
put from the transmitter.
FIGURE 8. 28 Parallel LVTTL Inputs Mapped to 4 Serial LVDS Outputs
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6
AC Loading and Waveforms (Continued)
FIGURE 9. Transmitter Output Pulse Bit Position
Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter ±3ns (cycle-to-cycle) clock
input. The specific test methodology is as follows:
•
•
Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left −3ns and to the right +3ns when data is HIGH.
The ±3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst
case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise
(VCC noise frequency <2 MHz).
FIGURE 10. Timing Diagram of Transmitter Clock Input with Jitter
7
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AC Loading and Waveforms (Continued)
Note: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical strips across the display.
FIGURE 11. “16 Grayscale” Test Pattern
FIGURE 12. Transmitter Phase Lock Loop Time
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8
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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9
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