FOD0720 [FAIRCHILD]
High CMR, 25Mbit/sec Logic Gate Optocoupler; 高CMR的25Mbit /秒的逻辑门光电耦合器
| 型号： | FOD0720 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | High CMR, 25Mbit/sec Logic Gate Optocoupler |
| 文件： | 总12页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2008
FOD0721, FOD0720, FOD0710
High CMR, 25Mbit/sec Logic Gate Optocoupler
Features
Description
■ 20kV/µs minimum CMR
The FOD0721/0720/0710 family utilizes Fairchild’s
patented coplanar packaging technology, Optoplanar®,
and optimized IC design to guarantee minimum 20kV/µs
Common Mode Noise Rejection (CMR) rating.
■ 40ns max. propagation delay
■ Data Rate, Non-Return Zero Coding
– 25Mbit/sec (FOD0721 and FOD0720)
– 12.5Mbit/sec (FOD0710)
These high-speed logic gate optocouplers consist of a
high-speed AlGaAs LED driven by a CMOS IC coupled
to a CMOS detector IC, comprising an integrated photo-
diode, a high-speed transimpedance amplifier and a
voltage comparator with an output driver. The CMOS
technology coupled to the high efficiency of the LED
achieves low power consumption as well as very high
speed (40ns propagation delay, 6ns pulse width
distortion).
■ Pulse Width Distortion
– 6ns (FOD0721)
– 8ns (FOD0720 and FOD0710)
■ +5V CMOS compatibility
■ Extended industrial temperate range
– -40 to 100°C temperature range
■ Safety and regulatory approvals
– UL1577, 3750 VACrms for 1 min. (File #E90700,
Volume 2)
These devices are available in a compact 8-pin small
outline package.
– IEC60747-5-2 pending approval
Applications
■ Industrial fieldbus communications
– Profibus, DeviceNet, CAN, RS485
■ Programmable logic control
■ Isolated data acquisition system
Package Dimensions
0.164 (4.16)
0.144 (3.66)
0.202 (5.13)
0.182 (4.63)
0.010 (0.25)
0.006 (0.16)
0.143 (3.63)
0.123 (3.13)
0.244 (6.19)
0.224 (5.69)
0.008 (0.20)
0.003 (0.08)
0.021 (0.53)
0.011 (0.28)
0.050 (1.27)
TYP
Lead Coplanarity : 0.004 (0.10) MAX
Note:
All dimensions are in inches (millimeters)
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
Functional Block Diagram
VDD1
VDD2
1
8
VI
NC
2
3
4
7
6
5
VO
*
GND1
GND2
*: Pin 3 must be left unconnected
Truth Table
VI
H
L
LED VO
OFF
ON
H
L
Pin Definitions
Pin Number
Pin Name
Pin Function Description
1
2
3
4
5
6
7
8
V
Input Supply Voltage
Input Data
DD1
V
I
LED Anode – must be left unconnected
Input Ground
GND1
GND2
Output Ground
V
Output Data
O
NC
Not Connected
V
Output Supply Voltage
DD2
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
2
Absolute Maximum Ratings (T = 25°C unless otherwise specified.)
A
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Value
Units
°C
T
Storage Temperature
-55 to +125
-40 to +100
260 for 10 sec
STG
T
Operating Temperature
Lead Solder Temperature
Reflow Temperature Profile (Refer to Relow Profile)
Input Supply Voltage
°C
OPR
T
°C
SOL
V
0 to 6.0
V
V
DD1
V
Input Voltage
-0.5 to V
+ 0.5
I
DD1
I
Input DC Current
-10 to +10
0 to 6.0
mA
V
I
V
Output Supply Voltage
Output Voltage
DD2
V
-0.5 to V
+ 0.5
V
D
DD2
I
Average Output Current
Input Power Dissipation
Output Power Dissipation
10
mA
mW
mW
O
PD1
PD2
90
70
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Ambient Operating Temperature
Supply Voltages
Min.
-40
4.5
2.0
0
Max.
+100
5.5
Unit
°C
V
T
OPR
V
, V
DD1 DD2
V
Logic High Input Voltage
Logic Low Input Voltage
V
V
IH
DD1
V
0.8
1.0
V
IL
t , t
Input Signal Rise and Fall Time
ms
r
f
• A 0.1µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8
• Pin 3 must be left unconnected
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
3
Electrical Characteristics (T = -40°C to 100°C and 4.5V ≤ V ≤ 5.5V, all typicals are at T = 25°C, V = 5V)
A
DD
A
DD
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
INPUT CHARACTERISTICS
I
Logic Low Input Supply Current
Logic High Input Supply Current
Input Supply Current
V = 0V
6.5
0.8
10.0
3.0
mA
mA
mA
µA
DD1L
DD1H
I
I
V = V
I DD1
I
13.0
+10
DD1
I
Input Current
-10
I
OUTPUT CHARACTERISTICS
I
Logic Low Output Supply Current
Logic High Output Supply Current
Logic High Output Voltage
V = 0V
5.5
5.3
5.0
4.8
0
9
9
mA
mA
V
DD2L
DD2H
I
I
V = V
I DD1
V
V
I
I
I
I
= -20µA, V = V
IH
4.4
4.0
OH
O
O
O
O
I
= -4mA, V = V
V
OH
I
IH
V
V
Logic Low Output Voltage
= 20µA, V = V
IL
0.1
1.0
V
OL
I
= 4mA, V = V
0.5
V
OL
I
IL
Isolation Characteristics (T = -40°C to +100°C unless otherwise specified.)
A
Symbol
Characteristics
Test Conditions
Min. Typ.* Max.
Unit
(1)(2)
V
R
C
Input-Output Isolation Voltage f = 60Hz, t = 1.0 min, I ≤ 10µA
3750
Vac
RMS
ISO
ISO
ISO
I-O
(1)
11
Isolation Resistance
Isolation Capacitance
V
V
= 500V
10
Ω
I-O
I-O
(1)
= 0 , f = 1.0MHz
0.2
pF
*All typicals at T = 25°C
A
Notes:
1. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
2. 3,750 VAC RMS for 1 minute duration is equivalent to 4,500 VAC RMS for 1 second duration.
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
4
Switching Characteristics (T = -40°C to 100°C and 4.5V ≤ V ≤ 5.5V, all typicals are at T = 25°C, V = 5V)
A
DD
A
DD
Symbol Parameter
Test Conditions Min.
Typ.
Max.
Unit
t
Propagation Delay Time to
C = 15pF
21
40
ns
PHL
L
Logic Low Output
t
Propagation Delay Time to
Logic High Output
C = 15pF
23
40
ns
PLH
L
PWD
Pulse Width Distortion, | t
FOD0710
– t
|
PHL
PLH
PW = 80ns, C = 15pF
2
2
2
8
8
ns
ns
L
FOD0720
PW = 40ns, C = 15pF
L
FOD0721
PW = 40ns, C = 15pF
6
ns
L
Data Rate
FOD0710
12.5
25
20
Mb/s
Mb/s
ns
FOD0720, FOD0721
Propagation Delay Skew
(3)
t
C = 15pF
L
PSK
t
Output Rise Time (10%–90%)
Output Fall Time (90%–10%)
5
ns
R
t
4.5
40
ns
F
|CM |
Common Mode Transient
Immunity at Output High
V = V
, V > 0.8 V
20
20
kV/µs
H
I
DD1
O
DD2
(4)
V
= 1000V
CM
|CM |
Common Mode Transient
Immunity at Output Low
V = 0V, V < 0.8,
40
kV/µs
L
I
O
(4)
V
= 1000V
CM
Notes:
3. t
is equal to the magnitude of the worst case difference in t
and/or t
that will be seen between units at any given
PSK
PHL
PLH
temperature within the recommended operating conditions.
4. Common mode transient immunity at output high is the maximum tolerable (positive) dVcm/dt on the leading edge
of the common mode impulse signal. Vcm, to assure that the output will remain high. Common mode transient
immunity at output low is the maximum tolerable (negative dVcm/dt on the trailing edge of the common pulse
signal, Vcm, to assure that the output will remain low.
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
5
Typical Performance Curves
Figure 2. Typical Input Voltage Switching Threshold vs.
Input Supply Voltage
Figure 1. Typical Output Voltage vs. Input Voltage
1.9
1.8
1.7
1.6
1.5
1.4
V
DD2 = 5.0V
5
4
3
2
1
0
0
1
2
3
4
5
4.50
4.75
5.00
5.25
5.50
VI - Input Voltage (V)
VDD1 - Input Supply Voltage (V)
Figure 4. Typical Pulse Width Distortion vs. Ambient Temperature
(FOD0710)
Figure 3. Typical Propogation Delay vs. Ambient Temperature
(FOD0710)
26
4
Frequency = 6.25MHz
Dut y Cycle = 50%
VDD1 = VDD2 = 5.0V
3
25
24
23
2
1
tPLH
22
t
PHL
0
21
20
19
18
-1
-2
-3
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TA - Ambient Temperature (°C)
TA - Ambient Temperature (°C)
Figure 5. Typical Propogation Delay vs. Ambient Temperature
(FOD0721/FOD0720)
Figure 6. Typical Pulse Width Distortion vs. Ambient Temperature
(FOD0721/FOD0720)
28
5
Frequency = 12.5MHz
Frequency = 12.5MHz
Duty Cycle = 50%
Duty Cycle = 50%
VDD1 = VDD2 = 5.0V
V
= V
= 5.0V
DD1
DD2
4
26
24
22
20
18
3
2
t
PLH
1
0
tPHL
-1
-2
-3
-40
-20
0
T
20
40
60
80
100
-40
-20
0
20
40
60
80
100
- Ambient Temperature (°C)
TA - Ambient Temperature (°C)
A
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
6
Typical Performance Curves (Continued)
Figure 8. Typical Propogation Delay vs. Output Load Capacitance
(FOD0710)
Figure 7. Typical Rise and Fall Time vs. Ambient Temperature
6.00
28
Frequency = 6.25MHz
Frequency = 6.25MHz
Duty Cycle = 50%
VDD1 = VDD2 = 5.0V
Duty Cycle = 50%
VDD1 = VDD2 = 5.0V
27
26
25
24
23
22
21
5.50
5.00
t
r
t
PLH
4.50
t
f
tPHL
4.00
3.50
3.00
-40
-20
0
T
20
40
60
80
100
15
20
25
30
35
40
45
50
55
- Ambient Temperature (°C)
CL - Output Load Capacitance (pF)
A
Figure 9. Typical Pulse Width Distortion vs. Output Load Capacitance
(FOD0710)
Figure 10. Typical Propogation Delay vs. Output Load Capacitance
(FOD0721/FOD0720)
27
1.6
Frequency = 6.25MHz
Frequency = 12.5MHz
Duty Cycle = 50%
Duty Cycle = 50%
VDD1 = VDD2 = 5.0V
V
= V
= 5.0V
DD1
DD2
26
1.4
1.2
1.0
0.8
0.6
25
tPLH
24
23
tPHL
22
21
15
20
25
30
35
40
45
50
55
15
20
25
30
35
40
45
50
55
CL - Output Load Capacitance (pF)
CL - Output Load Capacitance (pF)
Figure 11. Typical Pulse Width Distortion vs. Output Load Capacitance
(FOD0721/FOD0720)
Figure 12. Typical Rise and Fall Time vs. Output Load Capacitance
(FOD0710)
12
1.4
Frequency = 12.5MHz
Frequency = 6.25MHz
Dut y Cycle = 50%
Duty Cycle = 50%
VDD1 = VDD2 = 5.0V
VDD1 = VDD2 = 5.0V
1.3
1.2
1.1
1.0
0.9
0.8
10
8
t
f
t
r
6
4
2
15
20
25
30
35
40
45
50
55
15
20
25
30
35
40
45
50
55
CL - Output Load Capacitance (pF)
CL - Output Load Capacitance (pF)
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
7
Typical Performance Curves (Continued)
Figure 13. Typical Rise and Fall Time vs. Output Load Capacitance
(FOD0721/FOD0720)
Figure 14. Typical Input Supply Current vs. Frequency
12
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
VDD1 = 5.5V
Frequency = 12.5MHz
Dut y Cycle = 50%
VDD1 = VDD2 = 5.0V
10
8
TA = 100°C
t
f
TA = 25°C
t
r
TA = -40°C
6
4
2
0
2000
4000
6000
8000
10000
12000
15
20
25
30
35
40
45
50
55
f - Frequency (kHz)
CL - Output Load Capacitance (pF)
Figure 15. Typical Output Supply Current vs. Frequency
6.0
5.8
5.6
5.4
5.2
5.0
VDD1 = VDD2 = 5.5V
* Pin 6 Floating
T
= 25°C
A
T
A = -40°C
T
= 100°C
A
0
2000
4000
6000
8000
10000
12000
f - Frequency (kHz)
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
8
Ordering Information
Option
No Suffix
R2
Order Entry Identifier
Description
FOD0721
Shipped in Tubes (50 units per tube)
Tape and Reel (2500 units per reel)
FOD0721R2
Marking Information
1
2
721
5
X YY S1
4
3
Definitions
1
2
3
4
5
Fairchild logo
Device number
One digit year code, e.g., ‘8’
Two digit work week ranging from ‘01’ to ‘53’
Assembly package code
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
9
Carrier Tape Specification
8.0 0.1
0.05
2
3.5 0.2
0.3 MAX
Ø1.5 MIN
1.75 0.10
4.0 0.1
5.5 0.05
12.0 0.3
8.3 0.1
5.2 0.2
6.4 0.2
Ø1.5 + 0.1/-0
0.1 MAX
User Direction of Feed
Reflow Profile
300
280
260
240
220
200
180
160
140
120
100
80
260°C
>245°C = 42 Sec
Temperature
Time above
(°C)
183°C = 90 Sec
1.822°C/Sec Ramp up rate
60
40
33 Sec
20
0
0
60
120
180
270
360
Time (s)
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
10
1
2
3
4
8
7
6
5
0.1µF
0.1µF
V
= 5V
DD2
V
= 5V
DD1
0V–5V
V
O
Pulse width = 40ns
Duty Cycle = 50%
C
L
t
t
PHL
PLH
5V
Input
50%
V
IN
V
2.5V
90%
10%
OH
Output
V
V
OUT
OL
t
t
F
R
Figure 16.Test Circuit for Propogation Delay Time and Rise Time, Fall Time
1
2
3
4
8
7
6
5
0.1µF
SW
0.1µF
V
= 5V
DD2
B
A
V
O
V
= 5V
DD1
C
L
+
–
V
CM
V
1kV
CM
GND
V
CM
OH
H
Switching Pos. (A) V = 5V
IN
0.8 x V
DD
0.8V
Switching Pos. (B) V = 0V
IN
V
CM
OL
L
Figure 17.Test Circuit for Instantaneous Common Mode Rejection Voltage
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
11
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The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global
subsidiaries, and is not intended to be an exhaustive list of all such trademarks.
ACEx®
PDP-SPM™
SupreMOS™
FPS™
Power220®
SyncFET™
Build it Now™
CorePLUS™
CROSSVOLT™
CTL™
Current Transfer Logic™
EcoSPARK®
EZSWITCH™ *
™
FRFET®
POWEREDGE®
Power-SPM™
PowerTrench®
Programmable Active Droop™
QFET®
®
Global Power ResourceSM
Green FPS™
Green FPS™e-Series™
GTO™
i-Lo™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
The Power Franchise®
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
µSerDes™
UHC®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
SMART START™
SPM®
STEALTH™
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SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
Fairchild®
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FACT Quiet Series™
FACT®
MicroPak™
MillerDrive™
Motion-SPM™
OPTOLOGIC®
FAST®
Ultra FRFET™
UniFET™
VCX™
OPTOPLANAR®
FastvCore™
®
FlashWriter® *
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Advance Information
Formative or In Design
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
the design.
No Identification Needed
Obsolete
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I33
©2004 Fairchild Semiconductor Corporation
FOD0721, FOD0720, FOD0710 Rev. 1.0.7
www.fairchildsemi.com
12
相关型号：
FOD0720R2
Logic IC Output Optocoupler, 1-Element, 3750V Isolation, 25MBps, LEAD FREE, SOP-8
FAIRCHILD
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