FQB55N10_技术文档

August 2000

TM

QFET

FQB55N10 / FQI55N10

100V N-Channel MOSFET

General Description

Features

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar stripe, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for low voltage applications such as audio amplifier,

high efficiency switching DC/DC converters, and DC motor

control.

•

55A, 100V, R

= 0.026Ω @V = 10 V

DS(on) GS

Low gate charge ( typical 75 nC)

Low Crss ( typical 130 pF)

Fast switching

100% avalanche tested

Improved dv/dt capability

175°C maximum junction temperature rating

D

!

D

"

! "

"

!

G

"

G

S

D²-PAK

FQB Series

I²-PAK

FQI Series

G

D

S

!

S

Absolute Maximum Ratings

T = 25°C unless otherwise noted

C

Symbol

Parameter

FQB55N10 / FQI55N10

Units

V

I

Drain-Source Voltage

100

55

DSS

- Continuous (T = 25°C)

Drain Current

A

D

C

- Continuous (T = 100°C)

38.9

220

A

C

I

(Note 1)

Drain Current

- Pulsed

A

DM

V

E

I

Gate-Source Voltage

± 25

1100

55

V

GSS

(Note 2)

(Note 1)

(Note 3)

Single Pulsed Avalanche Energy

Avalanche Current

mJ

A

AS

AR

E

Repetitive Avalanche Energy

Peak Diode Recovery dv/dt

15.5

6.0

mJ

V/ns

W

AR

dv/dt

Power Dissipation (T = 25°C) *

3.75

155

P

A

D

Power Dissipation (T = 25°C)

W

C

- Derate above 25°C

Operating and Storage Temperature Range

1.03

-55 to +175

W/°C

°C

T , T

J

STG

Maximum lead temperature for soldering purposes,

T

300

°C

L

1/8" from case for 5 seconds

Thermal Characteristics

Symbol

Parameter

Typ

--

Max

0.97

40

Units

°C/W

R

Thermal Resistance, Junction-to-Case

Thermal Resistance, Junction-to-Ambient *

Thermal Resistance, Junction-to-Ambient

θJC

θJA

--

62.5

* When mounted on the minimum pad size recommended (PCB Mount)

Rev. A, July 2000

Electrical Characteristics

T = 25°C unless otherwise noted

C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

BV

V

= 0 V, I = 250 µA

GS D

Drain-Source Breakdown Voltage

100

--

V

DSS

∆BV

Breakdown Voltage Temperature

Coefficient

DSS

I

= 250 µA, Referenced to 25°C

0.1

V/°C

D

/

∆T

J

I

V

= 100 V, V = 0 V

--

1

µA

nA

DSS

DS

GS

Zero Gate Voltage Drain Current

= 80 V, T = 150°C

10

DS

GS

C

I

= 25 V, V = 0 V

Gate-Body Leakage Current, Forward

Gate-Body Leakage Current, Reverse

100

-100

GSSF

DS

I

= -25 V, V = 0 V

GSSR

DS

On Characteristics

V

= V , I = 250 µA

Gate Threshold Voltage

2.0

--

4.0

V

Ω

S

GS(th)

DS

GS

DS

GS

D

R

Static Drain-Source

On-Resistance

DS(on)

= 10 V, I = 27.5 A

0.021 0.026

D

g

= 40 V, I = 27.5 A

(Note 4)

Forward Transconductance

--

38

--

FS

D

Dynamic Characteristics

C

Input Capacitance

--

2100

640

2730

830

pF

iss

V

= 25 V, V = 0 V,

GS

DS

Output Capacitance

oss

rss

f = 1.0 MHz

Reverse Transfer Capacitance

130

170

Switching Characteristics

t

Turn-On Delay Time

Turn-On Rise Time

Turn-Off Delay Time

Turn-Off Fall Time

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

--

25

250

110

140

75

60

510

230

290

98

ns

d(on)

V

= 50 V, I = 55 A,

DD

D

r

R

= 25 Ω

G

ns

d(off)

f

(Note 4, 5)

ns

Q

nC

g

V

= 80 V, I = 55 A,

DS

D

13

--

= 10 V

gs

gd

GS

36

--

Drain-Source Diode Characteristics and Maximum Ratings

I

Maximum Continuous Drain-Source Diode Forward Current

--

55

220

1.5

--

A

S

I

Maximum Pulsed Drain-Source Diode Forward Current

SM

V

t

V

= 0 V, I = 55 A

Drain-Source Diode Forward Voltage

Reverse Recovery Time

--

V

SD

GS

S

= 0 V, I = 55 A,

100

380

ns

nC

rr

GS

S

(Note 4)

dI / dt = 100 A/µs

Q

Reverse Recovery Charge

--

F

rr

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 0.55mH, I = 55A, V = 25V, R = 25 Ω, Starting T = 25°C

AS

DD

G

J

3. I ≤ 55A, di/dt ≤ 300A/µs, V ≤ BV Starting T = 25°C

SD

DD

DSS, J

4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%

5. Essentially independent of operating temperature

Rev. A, July 2000

Typical Characteristics

V_GS

Top :

15.0 V

10.0 V

8.0 V

7.0 V

6.0 V

5.5 V

5.0 V

10²

10¹

10⁰

10²

10¹

10⁰

Bottom : 4.5 V

℃

175

℃

25

※

Notes :

μ

※

Notes :

℃

-55

1. 250 s Pulse Test

1. V_DS= 40V

℃

2. T_C= 25

μ

2. 250 s Pulse Test

-1

10

10^-1

10⁰

10¹

2

4

6

8

10

V_GS, Gate-Source Voltage [V]

V_DS, Drain-Source Voltage [V]

Figure 1. On-Region Characteristics

Figure 2. Transfer Characteristics

0.12

0.09

0.06

0.03

0.00

10²

10¹

10⁰

V_GS= 10V

V_GS= 20V

℃

25

175

※

Notes :

1. V_GS= 0V

※

℃

Note : T = 25

J

μ

2. 250 s Pulse Test

-1

10

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0

60

120

180

240

300

I_D, Drain Current [A]

V_SD, Source-Drain voltage [V]

Figure 3. On-Resistance Variation vs.

Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage

Variation vs. Source Current

and Temperature

6000

5000

4000

3000

2000

1000

0

12

10

8

C

_iss= C_gs+ C_gd(C_ds= shorted)

C_oss= C_ds+ C_gd

_rss= C

C

gd

V_DS= 50V

V_DS= 80V

C

iss

※

Notes :

C_oss

1. V_GS= 0 V

2. f = 1 MHz

6

4

C

rss

2

※

Note : I_D= 55A

70

0

-1

10

10⁰

10¹

0

10

20

30

40

50

60

80

Q_G, Total Gate Charge [nC]

V_DS, Drain-Source Voltage [V]

Figure 5. Capacitance Characteristics

Figure 6. Gate Charge Characteristics

Rev. A, July 2000

Typical Characteristics (Continued)

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.2

1.1

1.0

※Notes :

1. V_GS= 0 V

2. I_D= 250 μA

0.9

※

Notes :

1. V_GS= 10 V

2. I_D= 27.5 A

0.8

-100

-50

0

50

100

150

200

-100

-50

0

50

100

150

200

T_J, Junction Temperature [^oC]

Figure 7. Breakdown Voltage Variation

vs. Temperature

Figure 8. On-Resistance Variation

vs. Temperature

60

50

40

30

20

10

0

10³

Operation in This Area

is Limited by R _DS(on)

10 µs

10²

10¹

10⁰

100 µs

1 ms

10 ms

DC

※

Notes :

1. T_C= 25 ^o

2. T_J= 175 ^o

C

3. Single Pulse

-1

10

10⁰

10¹

10²

25

50

75

100

125

150

175

℃

T_C, Case Temperature [

]

V_DS, Drain-Source Voltage [V]

Figure 9. Maximum Safe Operating Area

Figure 10. Maximum Drain Current

vs. Case Temperature

1 0 ⁰

D = 0 .5

※

N o te s

1 . Z _θ_{J C}(t)

2 . D u ty F a c to r, D = t₁/t₂

3 . T _{J M}T _CP _DZ _θ_{J C}(t)

:

0 .2

℃

/W M a x .

=

0 .9 7

1 0^-1

0 .1

-

=

*

M

0 .0 5

P_DM

0 .0 2

0 .0 1

t₁

s in g le p u ls e

t₂

1 0^-2

1 0 ^-5

1 0^-4

1 0 ^-3

1 0 ^-2

1 0 ^-1

1 0 ⁰

1 0 ¹

t₁, S q u a re W a v e P u ls e D u ra tio n [s e c ]

Figure 11. Transient Thermal Response Curve

Rev. A, July 2000

Gate Charge Test Circuit & Waveform

V_GS

Same Type

50KΩ

as DUT

Q_g

12V

200nF

10V

300nF

V_DS

V_GS

Q_gs

Q_gd

DUT

3mA

Charge

Resistive Switching Test Circuit & Waveforms

R_L

V_DS

90%

V_DS

V_DD

V_GS

R_G

10%

V_GS

DUT

10V

t_d(on)

t_r

t_d(off)

t_f

t _on

t _off

Unclamped Inductive Switching Test Circuit & Waveforms

BV_DSS

--------------------

BV_DSS- V_DD

L

1

2

----

E_AS

=

L I_AS

V_DS

I _D

BV_DSS

I_AS

R_G

V_DD

I_D(t)

V_DD

V_DS(t)

DUT

10V

t _p

Time

Rev. A, July 2000

Peak Diode Recovery dv/dt Test Circuit & Waveforms

+

DUT

V_DS

_

I _SD

L

Driver

R_G

Same Type

as DUT

V_DD

V_GS

• dv/dt controlled by R_G

• I_SDcontrolled by pulse period

Gate Pulse Width

--------------------------

V_GS

D =

Gate Pulse Period

10V

( Driver )

I_FM, Body Diode Forward Current

I _SD

di/dt

( DUT )

I_RM

Body Diode Reverse Current

Body Diode Recovery dv/dt

V_SD

V_DS

( DUT )

V_DD

Body Diode

Forward Voltage Drop

Rev. A, July 2000

Package Dimensions

D²PAK

4.50 ±0.20

9.90 ±0.20

+0.10

–0.05

1.30

0.10 ±0.15

2.40 ±0.20

0.80 ±0.10

1.27 ±0.10

+0.10

0.50

–0.05

2.54 TYP

10.00 ±0.20

(8.00)

(4.40)

10.00 ±0.20

(2XR0.45)

0.80 ±0.10

Rev. A, July 2000

Package Dimensions ^(Continued)

I²PAK

4.50 ±0.20

9.90 ±0.20

+0.10

–0.05

1.30

1.27 ±0.10

1.47 ±0.10

0.80 ±0.10

+0.10

–0.05

0.50

2.40 ±0.20

2.54 TYP

10.00 ±0.20

Rev. A, July 2000

TRADEMARKS

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is

not intended to be an exhaustive list of all such trademarks.

ACEx™

HiSeC™

SuperSOT™-8

SyncFET™

TinyLogic™

UHC™

Bottomless™

CoolFET™

CROSSVOLT™

E²CMOS™

FACT™

ISOPLANAR™

MICROWIRE™

POP™

PowerTrench^®

QFET™

VCX™

FACT Quiet Series™

QS™

FAST^®

Quiet Series™

SuperSOT™-3

SuperSOT™-6

FASTr™

GTO™

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

INTERNATIONAL.

As used herein:

result in significant injury to the user.

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. A, January 2000


型号：	FQB55N10
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	100V N-Channel MOSFET 100V N沟道MOSFET
文件：	总9页 (文件大小：674K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FQB55N10 [FAIRCHILD]

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