FSA3157P6X-F40 [FAIRCHILD]
SPDT, 1 Func, CMOS, PDSO6;
| 型号： | FSA3157P6X-F40 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | SPDT, 1 Func, CMOS, PDSO6 光电二极管 输出元件 |
| 文件： | 总11页 (文件大小：1059K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2009
NC7SB3157, FSA3157
Low-Voltage SPDT Analog Switch or 2:1Multiplexer /
De-multiplexer Bus Switch
Features
Description
■ Useful in Both Analog and Digital Applications
■ Space-Saving, SC70 6-Lead Surface Mount Package
■ Ultra-Small, MicroPak™ Leadless Package
■ Low On Resistance: <10Ω on Typical at 3.3V VCC
■ Broad VCC Operating Range: 1.65V to 5.5V
■ Rail-to-Rail Signal Handling
The NC7SB3157 / FSA3157 is a high-performance, sin-
gle-pole / double-throw (SPDT) analog switch or 2:1 mul-
tiplexer / de-multiplexer bus switch.
The device is fabricated with advanced sub-micron
CMOS technology to achieve high-speed enable and
disable times and low on resistance. The break-before-
make select circuitry prevents disruption of signals on
the B Port due to both switches temporarily being
enabled during select pin switching. The device is speci-
fied to operate over the 1.65 to 5.5V VCC operating
range. The control input tolerates voltages up to 5.5V,
independent of the VCC operating range.
■ Power-Down, High-Impedance Control Input
■ Over-Voltage Tolerance of Control Input to 7.0V
■ Break-Before-Make Enable Circuitry
■ 250MHz, 3dB Bandwidth
Ordering Information
Top
Packing
Part Number Mark
Eco Status
Package Description
Method
3000 Units on
Tape and Reel
NC7SB3157P6X B7A
RoHS
6-Lead, SC70, EIAJ SC88, 1.25mm Wide Package
5000 Units on
Tape and Reel
NC7SB3157L6X
FSA3157P6X
FSA3157L6X
BB
B7A
BB
RoHS
RoHS
RoHS
6-Lead, MicroPak 1.0mm Wide Package
6-Lead, SC70, EIAJ SC88, 1.25mm Wide Package
6-Lead, MicroPak 1.0mm Wide Package
3000 Units on
Tape and Reel
5000 Units on
Tape and Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
MicroPak™ is a trademark of Fairchild Semiconductor Corporation.
©2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
Logic Symbol
Connection Diagrams
B1
S
A
B0
2. Pin Assignments SC70
Figure 1. Logic Symbol
Analog Symbol
B1
S
VCC
GND
B0
A
Figure 4. Pin One Orientation
Figure 3. Analog Symbol
Function Table
Note:
Orientation of top mark determines pin one location.
Read the top product code mark left to right and pin one
is the lower left pin (see Figure 4).
Input (S)
Function
Logic Level Low
Logic Level High
B0 Connected to A
B1 Connected to A
1
B1
GND
B0
6
5
4
S
Pin Descriptions
2
3
VCC
A
Pin Names
A, B0, B1
S
Description
Data Ports
Control Input
Figure 5. Pad Assignments for MicroPak™
© 2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
VCC
VS
Parameter
Min.
–0.5
–0.5
–0.5
Max.
+7.0
VCC +0.5
+7.0
–50
Unit
V
Supply Voltage
DC Switch Voltage(1)
V
VIN
DC Input Voltage(1)
V
IIK
DC Input Diode Current at VIN < 0V
DC Output Current
mA
mA
mA
°C
IOUT
ICC/IGND
TSTG
TJ
128
DC VCC or Ground Current
±100
+150
+150
+260
1
Storage Temperature Range
–65
Junction Temperature Under Bias
Junction Lead Temperature (Soldering, 10 seconds)
Moisture Sensitivity Level (JEDEC J-STD-020A)
Power Dissipation at +85°C
°C
TL
°C
MSL
PD
Level
mW
V
180
ESD
Human Body Model, JESD22-A114
4000
Note:
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
VCC
Parameter
Supply Voltage Operating
Control Input Voltage(2)
Switch Input Voltage(2)
Output Voltage(2)
Min.
1.65
0
Max.
5.50
VCC
VCC
VCC
+85
Unit
V
VIN
V
VIN
0
V
VOUT
TA
0
V
Operating Temperature
–40
°C
Control Input
VCC = 2.3V–3.6V
0
0
10
ns/V
tr, tf
Input Rise and Fall Time
Control Input
VCC = 4.5V–5.5V
5
ns/V
θJA
Thermal Resistance, SC70
270
°C/W
Note:
2. Control input must be held HIGH or LOW; it must not float.
© 2006 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7SB3157, FSA3157 Rev. 1.0.4
3
DC Electrical Characteristics
TA = –40°C to
+85°C
TA = +25°C
Symbol
Parameter
Conditions
VCC (V)
Units
Min.
Typ. Max.
Min.
Max.
1.65 – 1.95 0.75 VCC
2.3 – 5.5 0.7 VCC
1.65 – 1.95
0.75 VCC
0.7 VCC
High Level
Input Voltage
VIH
VIL
V
V
0.25 VCC
0.3 VCC
0.25 VCC
0.3 VCC
Low Level
Input Voltage
2.3 – 5.5
Input Leakage
Current
IIN
0 ≤ VIN ≤ 5.5V
0 – 5.5
±0.05
±0.05
±0.1
±0.1
±1
±1
µA
µA
Off State Leakage
Current
IOFF
0 ≤ A, B ≤ VCC
1.65 – 5.5
4.5
VIN = 0V, IO = 30mA
3.0
5.0
7.0
7.0
V
IN = 2.4V, IO = –30mA
12.0
15.0
9.0
12.0
15.0
9.0
VIN = 4.5V, IO = –30mA
VIN = 0V, IO = 24mA
VIN = 3V, IO = –24mA
VIN = 0V, IO = 8mA
7.0
3.0
2.3
4.0
Switch On
RON
10.0
5.0
20.0
12.0
30.0
20.0
50.0
20.0
12.0
30.0
20.0
50.0
Ω
Resistance(3)
VIN = 2.3V, IO = –8mA
VIN = 0V, IO = 4mA
13.0
6.5
1.65
VIN = 1.65V, IO = –4mA
17.0
Quiescent Supply
Current;
All Channels On or
Off
ICC
V
IN = VCC or GND IOUT = 0
5.5
1
10
µA
V
Analog Signal
Range
VCC
0
VCC
0
VCC
IA = –30mA, 0 ≤ VBn ≤ VCC
IA = –24mA, 0 ≤ VBn ≤ VCC
IA = –8mA, 0 ≤ VBn ≤ VCC
IA = –4mA, 0 ≤ VBn ≤ VCC
IA = –30mA, VBn = 3.15
IA = –24mA, VBn 2.1
4.5
3.0
2.3
1.65
4.5
3.0
2.3
25.0
50.0
100
300
On Resistance Over
Signal Range (3, 7)
RRANGE
Ω
Ω
Ω
0.15
0.2
On Resistance
ΔRON Match Between-
Channels(3, 4, 5)
I
A = –8mA, VBn = 1.6
0.5
IA = –4mA, VBn = 1.15
1.65
5.0
3.3
2.5
1.8
0.50
6.0
IA = –30mA, 0 ≤ VBn ≤ VCC
IA = –24mA, 0 ≤ VBn ≤ VCC
IA = –8mA, 0 ≤ VBn ≤ VCC
12.0
28.0
125
On Resistance
Rflat
Flatness(3, 4, 6)
I
A = –4mA, 0 ≤ VBn ≤ VCC
Notes:
3. Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is
determined by the lower of the voltages on the two (A or B Ports).
4. Parameter is characterized, but not tested in production.
5. ΔRON = RON max – RON minimum measured at identical VCC, temperature, and voltage levels.
6. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified
range of conditions.
7. Guaranteed by design.
© 2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
4
AC Electrical Characteristics
TA = –40°C to
+85°C
VCC
(V)
TA = +25°C
Figure
Number
Symbol
Parameter
Conditions
Units
Min. Typ. Max. Min. Max.
1.65 – 1.95
2.3 – 2.7
3.5
1.2
3.5
1.2
tPHL
tPLH
,
Propagation Delay
Bus-to-Bus(8)
Figure 12
Figure 13
VI = OPEN
ns
3.0 – 3.6
0.8
0.8
4.5 – 5.5
0.3
0.3
1.65 – 1.95 7.0
23.0
13.0
6.9
7.0
3.5
2.5
1.7
3.0
2.0
1.5
0.8
0.5
0.5
0.5
0.5
24.0
14.0
7.6
Output Enable Time
Turn-On Time
(A to Bn)
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
3.5
2.5
1.7
tPZL
tPZH
,
VI = 2 x VCC for tPZL
VI = 0V for tPZH
Figure 12
Figure 13
ns
5.2
5.7
1.65 – 1.95 3.0
12.5
7.0
13.0
7.5
Output Disable Time
Turn-Off Time
(A Port to B Port)
Figure 12
ns Figure 13
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
2.0
1.5
0.8
tPLZ
tPHZ
,
VI = 2 x VCC for tPLZ
VI = 0V for tPHZ
5.0
5.3
3.5
3.8
1.65 –1.95 0.5
2.3 – 2.7
3.0 – 3.6
4.5 – 5.5
5.0
0.5
0.5
0.5
Break-Before-Make
Time(9)
tB-M
ns Figure 14
pC Figure 15
CL = 0.1nF, VGEN = 0V,
RGEN = 0Ω
7.0
3.0
Q
Charge Injection(9)
3.3
OIRR
Xtalk
BW
Off Isolation(10)
Crosstalk
RL = 50Ω, f = 10MHz
RL = 50Ω, f = 10MHz
RL = 50Ω
1.65 – 5.5
1.65 – 5.5
1.65 – 5.5
–57.0
–54.0
250
dB Figure 16
dB Figure 17
MHz Figure 20
–3dB Bandwidth
Total Harmonic
Distortion(9)
RL = 600Ω, 0.5 VPP
f = 600 Hz to 20 KHz
,
THD
5.0
.011
%
Notes:
8. This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than
the RC delay of the on resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage
source (zero output impedance).
9. Guaranteed by design.
10. Off Isolation = 20 log10 [VA / VBn].
Capacitance
TA = +25°C, f = 1MHz. Capacitance is characterized, but not tested in production.
Figure
Number
Symbol
Parameter
Conditions
Typ.
Max.
Units
CIN
Control Pin Input Capacitance
B Port Off Capacitance
VCC = 0V
VCC = 5.0V
VCC = 5.0V
2.3
6.5
pF
pF
pF
CIO-B
Figure 18
Figure 19
CIOA-ON A Port Capacitance When Switch Is Enabled
18.5
© 2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
5
Typical Characteristics
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-10
VCC = 5.5V
VCC = 1.65V
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
1
1
1
10
100
1000
1000
1000
1
1
1
10
100
1000
1000
1000
Frequency (MHz)
Frequency (MHz)
Figure 6. Off Isolation, VCC = 1.65V
Figure 7. Off Isolation, VCC = 5.5V
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
VCC = 1.65V
VCC = 5.5V
10
100
10
100
Frequency (MHz)
Frequency (MHz)
Figure 8. Crosstalk, VCC = 1.65V
Figure 9. Crosstalk, VCC = 5.5V
0
-1
-2
-3
-4
-5
-6
-7
-8
0
-1
-2
-3
-4
-5
-6
-7
-8
CL = 0pF
VCC = 1.65V
CL = 0pF
VCC = 5.5V
10
100
10
100
Frequency (MHz)
Frequency (MHz)
Figure 10. Bandwidth, VCC = 1.65V
Figure 11. Bandwidth, VCC = 5.5V
© 2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
6
AC Loading and Waveforms
VI
RU
FROM
OUTPUT
UNDER
TEST
CL
RD
Notes:
Input driven by 50Ω source terminated in 50Ω
CL includes load and stray capacitance
Input PRR = 1.0 MHz; tW = 500 ns
Figure 12. AC Test Circuit
tr = 2.5ns
tr = 2.5ns
VCC
90%
50%
90%
Control
Input
tr = 2.5ns
tr = 2.5ns
50%
VCC
90%
50%
90%
50%
10%
10%
GND
Switch
Input
tPZL
tPLZ
VTRI
10%
10%
GND
tW
Output
50%
tPLH
tPHL
VOL+0.3V
VOL
tPHZ
VOH
tPZH
Output
50%
50%
VOH
VOL
VOH–0.3V
Output
50%
VTRI
Figure 13. AC Waveforms
B0
VIN
A
Logic
Input
VOUT
B1
S
RL
CL
VOUT
0.9 x VOUT
Logic
Input
tD
Figure 14. Break-Before-Make Interval Timing
© 2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
7
AC Loading and Waveforms (continued)
RGEN
Logic
Input
A
BN
S
OFF
ON
OFF
ΔVOUT
VOUT
VGE
RL
CL
VOUT
1MΩ 100pF
Logic
Input
Q = (ΔVOUT)(CL)
Figure 15. Charge Injection Test
10nF
10nF
Signal
VCC
B0
A
VCC
Generator
A
Logic Input
0V or VIH
0dBm
50Ω
50Ω
50Ω
B1
S
S
BN
Analyzer
Analyzer
GND
50Ω
GND
Figure 16. Off Isolation
Figure 17. Crosstalk
10nF
10nF
Capacitance
VCC
A
VCC
A
Meter
Logic Input
0V or VCC
Logic Input
0V or VCC
f = 1MHz
Capacitance
Meter
S
S
BN
BN
f = 1MHz
GND
GND
Figure 19. Channel On Capacitance
Figure 18. Channel Off Capacitance
10nF
VCC
A
Signal
Generator
0dBm
BN
S
50Ω
Logic Input
0V or VCC
GND
Figure 20. Bandwidth
© 2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
8
Physical Dimensions
Figure 21. 6-Lead, SC70, EIAJ SC88, 1.25mm Wide Package
Note: click here for tape and reel specifcations, available at:
http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
9
Physical Dimensions
2X
0.05 C
1.45
B
2X
(1)
0.05 C
(0.49)
5X
1.00
(0.75)
(0.52)
1X
A
TOP VIEW
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
0.10
1.0
DETAIL A
C B A
C
0.40
0.05
0.30
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
MAC06AREVC
6-Lead, MicroPak™ 1.0mm Wide Package
Note: click here for tape and reel specifcations, available at:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
10
© 2006 Fairchild Semiconductor Corporation
NC7SB3157, FSA3157 Rev. 1.0.4
www.fairchildsemi.com
11
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