GTLP1B151MX [FAIRCHILD]
1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path; 1位LVTTL / GTLP收发器具有独立LVTTL端口和反馈路径
| 型号： | GTLP1B151MX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path |
| 文件： | 总7页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2001
Revised February 2002
GTLP1B151
1-Bit LVTTL/GTLP Transceiver
with Separate LVTTL Port and Feedback Path
General Description
Features
■ Separate LVTTL inputs and outputs
The GTLP1B151 is
a
1-bit transceiver that provides
LVTTL-to-GTLP signal level translation. Individual LVTTL
and GTLP driver enables are also available. The
GTLP1B151 offers separate LVTTL inputs and outputs,
and can provide a feedback path for control and diagnos-
tics monitoring.
■ A feedback path for control and diagnostics monitoring
■ Bidirectional interface between GTLP and LVTTL logic
levels
■ Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
High-speed backplane operation is
a direct result of
■ VREF pin provides external supply reference voltage for
receiver threshold adjustibility
GTLP’s reduced output swing (<1V), reduced input thresh-
old levels and output edge rate control. The edge rate
control minimizes bus-settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transistor Logic
(GTL) JEDEC standard JESD8-3.
■ Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage and temperature compensated. GTLP’s I/O
structure is similar to GTL and BTL but offers different out-
put levels and receiver threshold. Typical GTLP output volt-
age levels are: VOL = 0.5V, VOH = 1.5V, and VREF = 1V.
■ TTL compatible driver and control inputs
■ Designed using Fairchild advanced BiCMOS technology
■ Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
■ Power up/down and power off high impedance for live
insertion
■ Open drain on GTLP to support wired-or connection
■ Flow through pinout optimizes PCB layout
■ A Port source/sink −24mA / +24mA
■ B Port sink +50mA
Ordering Code:
Order Number Package Number
Package Description
GTLP1B151M
GTLP1B151MX
GTLP1B151K8X
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TUBE]
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
[TAPE and REEL]
MAB08A
(Preliminary)
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
[TAPE and REEL]
© 2002 Fairchild Semiconductor Corporation
DS500484
www.fairchildsemi.com
Pin Descriptions
Connection Diagrams
US8
Pin Names
Description
OEB, OEC
LVTTL Individual Output Enable Controls
(OEC is Active LOW)
VCC, GND, VREF Device Supplies
A
B
C
A Port LVTTL Input
B Port GTLP Input/Output
C Port LVTTL Output
SOIC
Functional Description
The GTLP1B151 is a 1-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting with sep-
arate LVTTL inputs and outputs and there are individual GTLP and LVTTL output enable controls.
Functional Tables
Inputs
Outputs
Description
An
Bn
Bn
Cn
OEB
H
OEC
L
L
L
H
Output
L
H
L
L
H
Z
Z
Z
Z
L
B Bus Enabled, C Bus Enabled
B Bus Enabled, C Bus Enabled
B Bus Enabled, C Bus Disabled
B Bus Enabled, C Bus Disabled
B Bus Disabled, C Bus Disabled
B Bus Disabled, C Bus Disabled
B Bus Disabled, C Bus Enabled
B Bus Disabled, C Bus Enabled
H
Output
H
H
H
H
H
L
L
Output
H
H
Output
H
Z
Z
Z
Z
L
L
L
H
L
L
H
L
N/A
N/A
L
L
H
H
Logic Diagram
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
DC Output Voltage (VO)
Outputs 3-STATE
Supply Voltage VCC
3.15V to 3.45V
Bus Termination Voltage (VTT
)
−0.5V to +4.6V
−0.5V to +4.6V
GTLP
1.47V to 1.53V
0.98V to 1.02V
Outputs Active (Note 2)
DC Output Sink Current into
C Port IOL
VREF
Input Voltage (VI)
on A Port and Control Pins
48 mA
−48 mA
100 mA
−50 mA
0.0V to VCC
DC Output Source Current from
C Port IOH
HIGH Level Output Current (IOH
)
C Port
−24 mA
DC Output Sink Current into
B Port in the LOW State, IOL
LOW Level Output Current (IOL
)
C Port
+24 mA
+50 mA
DC Input Diode Current (IIK
)
B Port
VI < 0V
Operating Temperature (TA)
−40°C to +85°C
DC Output Diode Current (IOK
O < 0V
)
Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. The device should not be oper-
ated at these limits. The parametric values defined in the “Electrical Char-
acteristics” table are not guaranteed at the absolute maximum rating. The
“Recommended Operating Conditions” table will define the conditions for
actual device operation.
V
−50 mA
>2000V
ESD Rating
Storage Temperature (TSTG
)
−65°C to +150°C
Note 2: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, V
= 1.0V (unless otherwise noted).
REF
Min
Typ
Max
Symbol
Test Conditions
Units
(Note 3)
VIH
VIL
B Port
V
REF + 0.05
VTT
V
V
Others
B Port
Others
B Port
B Port
2.0
0.0
V
REF − 0.05
0.8
VREF
VTT
0.7V
1.0
1.5
1.3V
V
V
V
VREF + 50 mV
VCC
VIK
V
V
V
CC = 3.15V
II = −18 mA
−1.2
VOH
C Port
C Port
CC = Min to Max (Note 4)
CC = 3.15V
I
I
OH = −100 µA
OH = −8 mA
VCC –0.2
2.4
V
V
IOH = -24mA
2.2
VOL
V
V
V
V
CC = Min to Max (Note 4)
I
I
I
I
I
OL = 100 µA
OL = 8 mA
OL = 24mA
OL = 40 mA
OL = 50 mA
0.2
0.4
0.5
0.4
0.55
5
CC = 3.15V
CC = 3.15V
B Port
CC = 3.15V
V
II
Control Pins
A Port
VCC = 3.45V
VCC = 3.45V
VCC = 3.45V
VCC = 0
VI = 3.45V
VI = 0V
µA
µA
−5
VI = 3.45V
VI = 0V
10
−10
5
B Port
VI = 3.45
µA
µA
VI = 0
−5
IOFF
A or C Ports,
Control Pins
B Port
VI or VO = 0 to 3.45V
30
VCC = 0
VI or VO = 0 to 3.45V
VI = 0.8V
30
µA
µA
II (HOLD)
A Port
VCC = 3.15V
75
VI = 2.0V
−75
10
IOZH
C Port
B Port
C Port
B Port
V
CC = 3.45V
CC = 3.45V
V
V
V
V
O = 3.45V
O = 3.45V
O = 0V
µA
µA
5
IOZL
V
−10
−5
O = 0.0V
3
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DC Electrical Characteristics (Continued)
Min
Typ
Max
Symbol
All Ports
Test Conditions
VI = 0 to 3.45V
Units
(Note 3)
IPU/PD
ICC
V
CC = 0 to 1.5V
CC = 3.45V
30
11
11
11
2
µA
A or B Ports
or C Port
V
Outputs HIGH
Outputs LOW
I
O = 0
VI = VCC/VTT or GND
VCC = 3.45V,
mA
mA
Outputs Disabled
One Input at VCC
∆ICC
(Note 5)
Ci
A Port and
Control Pins A or Control Inputs at VCC or GND −0.6V
Control Pins
and A Port
C Port
VI = VCC or 0
3
pF
CO
VI = VCC or 0
VI = VTT or 0
5
pF
pF
CI/O
B Port
5.5
Note 3: All typical values are at VCC = 3.3V and TA = 25°C.
Note 4: For conditions shown as Min, use the appropriate value specified under recommended operating conditions.
Note 5: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
Note: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In
addition, VTT and RTERM can be adjusted beyond the recommended operating to accommodate backplane impedances other than 50Ω, but must remain
within the boundaries of the DC Absolute Maximum Ratings. Similarly, VREF can be adjusted to optimize noise margin.
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, V
= 1.0V (unless otherwise noted).
REF
C
L = 30 pF for B Port and CL = 50 pF for C Port.
From
To
Min
Typ
(Note 6)
3.2
Max
Symbol
(Input)
Unit
ns
(Output)
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tRISE
tFALL
tRISE
tFALL
1.2
0.8
1.4
1.6
1.6
2.0
7.3
4.5
4.4
5.0
8.1
7.5
A
B
A
B
C
C
2.3
2.8
ns
2.9
6.0
ns
5.1
Transition Time, B Outputs (20% to 80%)
Transition Time, B Outputs (80% to 20%)
Transition Time, C Outputs (10% to 90%)
Transition Time, C Outputs (90% to 10%)
1.4
ns
ns
ns
ns
2.0
2.8
2.5
tPZH, tPZL
tPHZ, tPLZ
tPLH
1.2
1.4
1.7
0.5
2.7
2.8
3.5
2.2
5.3
4.9
5.9
4.7
OEC
OEB
C
B
ns
ns
tPHL
Note 6: All typical values are at VCC = 3.3V, and TA = 25°C.
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4
Test Circuits and Timing Waveforms
Test Circuit for C Outputs
Test Circuit for B Outputs
Test
S
tPLH/tPHL OPEN
tPLZ/tPZL 6V
Note: CL includes probes and Jig capacitance.
Note: For B Port, CL = 30 pF is used for worst case.
tPHZ/tPZH GND
Note: CL includes probes and Jig capacitance.
Voltage Waveforms Propagation Delay
Voltage Waveform Enable and Disable Times
A or LVTTL
B or GTLP
Pins
Pins
VINHIGH
VINLOW
VM
VCC
1.5
0.0
0.0
VCC/2
OL + 0.3V
1.0
VX
V
N/A
N/A
VY
VOH − 0.3V
Note: Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.
Note: All input pulses have the following characteristics:
Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50Ω. The outputs are measured one at a time with one transition per measurement.
5
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M08A
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide
Package Number MAB08A
Preliminary
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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7
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