SG5851 [FAIRCHILD]
Low-Cost Green-Mode PWM Controller for Flyback Converters; 低成本绿色模式PWM控制器，用于反激式转换器
| 型号： | SG5851 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Low-Cost Green-Mode PWM Controller for Flyback Converters |
| 文件： | 总11页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2008
SG5851
Low-Cost Green-Mode PWM Controller for Flyback
Converters
Features
Description
This highly integrated PWM controller provides several
special enhancements designed to meet the low
standby-power needs of low-power SMPS. To minimize
standby power consumption, the proprietary green-
mode function provides off-time modulation to linearly
decrease the switching frequency under light-load
conditions. This green-mode function enables the
power supply to meet even the strictest power
conservation requirements.
Green-Mode PWM
Supports the “Blue Angel” Standard
Low Start-up Current: 9µA
Low Operating Current: 3mA
Leading-Edge Blanking
Constant Output Power Limit
Universal Input
The BiCMOS fabrication process enables reducing the
start-up current to 9µA and the operating current to
3mA. To further improve power conservation, a large
start-up resistance can be used. Built-in synchronized
slope compensation ensures the stability of peak
current mode control. Proprietary internal compensation
provides a constant output power limit over a universal
AC input range (90VAC to 264VAC). Pulse-by-pulse
current limiting ensures safe operation even during
short-circuit conditions.
Built-in Synchronized Slope Compensation
Current Mode Operation
Cycle-by-cycle Current Limiting
Under-Voltage Lockout (UVLO)
Programmable PWM Frequency with Frequency
Hopping
VDD Over-Voltage Protection (Auto Restart)
Gate Output Voltage Clamped at 17V
Low Cost
To protect the external power MOSFET from being
damaged by supply over voltage, the output driver is
clamped at 17V. SG5851 controllers, available in an
SOP package, can be used to improve the performance
and reduce the production cost of power supplies.
Few External Components Required
Applications
Power Adaptors
Open-Frame SMPS
Ordering Information
Part Number
SG5851SZ
Operating Temperature Range
Package
Packing Method
Tape & Reel
Rail
-40°C to +85°C
-40°C to +85°C
8-pin Small Outline Package (SOP)
8-pin Dual in-line Package (DIP)
SG5851DZ
All packages are lead free per JEDEC: J-STD-020B standard.
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
Application Diagram
Figure 1.
Typical Application
Block Diagram
Figure 2. Function Block Diagram
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
2
Pin Configuration
GATE
VDD SENSE
NC
8
7
6
5
1
2
3
4
GND
FB
VDD
RI
Figure 3. Pin Configuration(Top View)
Pin Definitions
Pin #
Name
GND
FB
Description
1
2
3
Ground. For ATX SMPS, it detects AC line voltage through the main transformer.
Feedback.
VDD
Power Supply.
Reference Setting. A resistor connected from the RI pin to ground generates a constant
current source used to charge an internal capacitor and determine the switching frequency.
Increasing the resistance reduces the amplitude of the current source and reduces the
switching frequency. A 95kΩ resistor, RI, results in a 50µA constant current II and a 70kHz
switching frequency.
4
RI
5
6
NC
No Connection.
Current Sense. This pin senses the voltage across a resistor. When the voltage reaches the
internal threshold, PWM output is disabled. This activates over-current protection. This pin also
provides current amplitude information for current-mode control.
SENSE
7
8
VDD
Power Supply.
GATE
Driver Output. The totem-pole output driver for driving the power MOSFET.
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VVDD
VFB
Parameter
Min.
Max.
30
Unit
V
DC Supply Voltage
-0.5
-0.5
7.0
V
Input Voltage to FB Pin
7.0
V
VSENSE
PD
Input Voltage to Sense Pin
Power Dissipation
300
150
141
150
mW
°C
TJ
Operating Junction Temperature
Thermal Resistance (Junction to Air)
Storage Temperature Range
θJA
°C/W
°C
-55
TSTG
TL
260
3.0
Lead Temperature (Wave soldering, or IR 10 seconds)
Electrostatic Discharge Capability, Human Body Model
Electrostatic Discharge Capability, Machine Model
°C
KV
V
ESD
200
Notes:
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under “absolute maximum ratings “may cause permanent damage to the device.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Operating Ambient Temperature
Min.
Typ.
Max.
Unit
TA
-40
+85
°C
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
4
Electrical Characteristics
VDD =15V, TA= 25°C, unless noted operating specs.
Symbol
Parameter
Conditions
Min.
Typ. Max. Units
VDD Section
VDD-OP
VDD-ON
Continuous Operation Voltage
Turn-on Threshold Voltage
22
17.5
12.5
15
V
V
15.5
10.5
16.5
11.5
9
VDD-OFF Turn-off Threshold Voltage
V
IDD-ST
IDD-OP
Start-up Current
µA
V
DD=VDD-ON – 0.1V
VDD=15V, GATE with
1nF to GND
Operating Supply Current
3.0
3.5
26
mA
VDD-OVP VDD Over-voltage Protection level
tD-VDDOVP VDD Over-voltage Protection Debounce
Feedback Input Section
Auto Restart
Auto Restart
24
25
V
100
µs
VFB-OPEN FB Output High Voltage
5
V
V
VFB-OL
tD-OLP
VFB-N
VFB-G
SG
FB Open-loop Trigger Level
4.3
4.6
56
4.9
3.10
100
Delay Time of FB Pin Open-loop Protection
Green-Mode Entry FB Voltage
Green-Mode Ending FB Voltage
Green-Mode Modulation Slope
ms
V
2.60
40
2.85
2.2
75
V
RI=95KΩ
Hz/mV
Current-Sense Section
ZSENSE
tPD
Input Impedance
10
40
KΩ
ns
V
Delay to Output
VDD=13.5 to 22V
55
1
100
VSTHFL
VSTHVA
tLEB
Flat Threshold Voltage for Current Limit
Valley Threshold Voltage for Current Limit
Leading-Edge Blanking Time
0.75
250
0.80
310
45
0.85
370
V
ns
%
DCYSAW Duty Cycle of SAW Limit
Maximum Duty Cycle
Oscillator Section
Center Frequency
FOSC
65
0
70
±4.9
3.7
75
RI=95KΩ
KHz
Hopping Range
tHOP
FOSC-G
FDV
Hopping Period
RI=95KΩ
ms
KHz
%
Green-Mode Frequency
Frequency Variation vs. VDD Deviation
RI=95KΩ
20
VDD=13.5 to 22V
0.02
2.00
2
Frequency Variation vs. Temperature
Deviation
FDT
TA=-20 to 85°C
%
Output Section
DCYMAX Maximum Duty Cycle
VGATE-L Output Voltage Low
VGATE-H Output Voltage High
70
8
75
80
%
V
VDD=15V, IO=20mA
VDD=13.5V, IO=20mA
VDD=15V, CL=1nF
VDD=15V, CL=1nF
1.5
V
tr
tf
Rising Time
Falling Time
200
55
ns
ns
VGATE-
CLAMP
Output Clamp Voltage
VDD=22V
16
17
18
V
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
5
Functional Description
SG5851 devices integrate many useful designs into
one controller for low-power switch-mode power
supplies. The following descriptions highlight some of
the features of the SG5851 series.
Constant Output Power Limit
When the SENSE voltage across the sense resistor,
RS, reaches the threshold voltage (~1.00V), the output
GATE drive is turned off after propagation delay, tPD
.
This propagation delay introduces an additional current
proportional to tPD•Vin/Lp. The propagation delay is
nearly constant regardless of the input line voltage VIN.
Higher input line voltages result in larger additional
currents. At high input line voltages, the output power
limit is higher than at low input line voltages.
Start-up Current
The start-up current is only 9µA, which allows a start-
up resistor with a high resistance and a low-wattage to
supply the start-up power for the controller. A 1.5MΩ,
0.25W, start-up resistor and a 10µF/25V VDD hold-up
capacitor are sufficient for an AC-to-DC power adapter
with a wide input range (90VAC to 264VAC).
To compensate for this output power limit variation
across a wide AC input range, the threshold voltage is
adjusted by adding a positive ramp. This ramp signal
rises from 0.80V to 1.00V, then flattens out at 1.00V. A
smaller threshold voltage forces the output GATE drive
to terminate earlier. This reduces the total PWM turn-
on time and makes the output power equal to that of
low line input. This proprietary internal compensation
ensures a constant output power limit for a wide AC
input voltage range (90VAC to 264VAC).
Operating Current
The operating current has been reduced to 3mA, which
results in higher efficiency and reduces the VDD hold-up
capacitance requirement.
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching
frequency under light-load conditions. On-time is
limited to provide stronger protection against
brownouts and abnormal conditions. The feedback
current, which is sampled from the voltage feedback
loop, is taken as the reference. Once the feedback
current exceeds the threshold current, the switching
frequency starts to decrease. This green-mode
function dramatically reduces power consumption
under light-load and zero-load conditions. Power
supplies using the SG5851 can meet even the strictest
regulations regarding standby power consumption.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 11.5V. During start-up, the hold-up
capacitor must be charged to 16.5V through the start-
up resistor to enable SG5851. The hold-up capacitor
continues to supply VDD until power can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 11.5V during the start-up process.
This UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply VDD during start-up.
Gate Output
The SG5851 BiCMOS output stage is a fast totem-pole
gate driver. Cross conduction has been avoided to
minimize heat dissipation, increase efficiency, and
enhance reliability. The output driver is clamped by an
internal 17V Zener diode to protect power MOSFET
transistors against undesired over-voltage gate signals.
Oscillator Operation
A resistor connected from the RI pin to ground
generates a constant current source used to charge an
internal capacitor. The charge time determines the
internal clock speed and the switching frequency.
Increasing the resistance reduces the amplitude of the
input current and reduces the switching frequency. A
95kΩ resistor, RI, results in a 50µA constant current, II,
and a 70kHz switching frequency. The relationship
between RI and the switching frequency is:
Built-in Slope Compensation
The sensed voltage across the current sense resistor
is used for current mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
6650
(1)
fPWM
=
(kHz)
RI(kΩ)
peak-current mode control. The SG5851 has
a
synchronized, positively-sloped ramp built-in at each
switching cycle. The slope of the ramp is:
The range of the oscillation frequency is designed to
be within 50kHz ~ 100kHz.
0.36 × Duty
(2)
Duty(max.)
Leading-Edge Blanking
Noise Immunity
Each time the power MOSFET is switched on, a turn-
on spike occurs at the sense-resistor. To avoid
premature termination of the switching pulse, a 320ns
leading-edge blanking time is built in. Conventional RC
filtering can therefore be omitted. During this blanking
period, the current-limit comparator is disabled and it
cannot switch off the gate driver.
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
continuous-conduction mode. While slope compensation
helps alleviate these problems, further precautions
should be taken. Good placement and layout practices
should be followed. Avoiding long PCB traces and
component leads, locating compensation and filter
components near the SG5851, and increasing power
MOS gate resistance improve performance.
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
6
Typical Performance Characteristics
17.000
16.800
16.600
16.400
16.200
14.000
13.000
12.000
11.000
10.000
9.000
8.000
16.000
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature (℃)
Temperature (℃)
Figure 4. VDD-ON vs. TA
Figure 5. VDD-OFF vs. TA
2.000
14.000
12.000
10.000
8.000
1.800
1.600
1.400
1.200
6.000
4.000
2.000
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
℃
Temperature (
)
Temperature (℃)
Figure 6. IDD-ST vs. TA
Figure 7. IDD-OP vs. TA
70.0
69.8
69.6
69.4
69.2
69.0
70.0
69.8
69.6
69.4
69.2
69.0
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature (
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
)
℃
Temperature (
)
℃
Figure 8. fOSC vs. TA
Figure 9. DCYMAX vs. TA
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
7
Typical Performance Characteristics
2.30
2.28
2.26
2.24
2.22
2.20
3.0
2.9
2.8
2.7
2.6
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature (
Temperature (
)
℃
)
℃
Figure 10. VFB-N vs. TA
Figure 11. VFB-G vs. TA
320
310
300
290
280
270
260
-40℃ -25℃ -10℃ 5℃ 20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Temperature (
)
℃
Figure 12. tLEB vs. TA
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
8
Mechanical Dimensions
C
8
5
H
E
F
1
b
4
e
D
Θ
L
A
A1
Figure 13. 8-SOIC
Dimensions
Millimeter
Min.
Inch
Min.
Symbol
Typ.
Max.
Typ.
Max.
A
A1
b
1.346
0.101
1.752
0.254
0.053
0.004
0.069
0.010
0.406
0.203
0.016
0.008
c
D
E
e
4.648
3.810
4.978
3.987
0.183
0.150
0.196
0.157
1.270
0.050
F
0.381X45˚
0.015X45˚
H
L
θ˚
5.791
0.406
0˚
6.197
1.270
8˚
0.228
0.016
0˚
0.244
0.050
8˚
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
9
Mechanical Dimensions (Continued)
D
Θ
8
5
e
B
E
1
4
L
b1
b
e
Figure 14. 8-DIPIC
Dimensions
Millimeter
Min.
Inch
Min.
Symbol
Typ.
Max.
Typ.
Max.
A
A1
A2
b
b1
D
E
E1
e
5.334
3.429
0.210
0.135
0.381
3.175
0.015
0.125
3.302
1.524
0.457
9.271
7.620
6.350
2.540
3.302
9.017
7˚
0.130
0.060
0.018
0.365
0.300
0.250
0.100
0.130
0.355
7˚
9.017
6.223
10.160
6.477
0.355
0.245
0.400
0.255
L
eB
θ˚
2.921
8.509
0˚
3.810
9.525
15˚
0.115
0.335
0˚
0.150
0.375
15˚
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
10
© 2007 Fairchild Semiconductor Corporation
SG5851 • Rev. 1.0.0
www.fairchildsemi.com
11
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