FM8PE531MAP [FEELING]
OTP-Based 8-Bit Microcontroller;
| 型号： | FM8PE531MAP |
| 厂家： | 
Feeling Technology |
| 描述： | OTP-Based 8-Bit Microcontroller 微控制器 |
| 文件： | 总55页 (文件大小：7544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EELING
FM8PE531M
OTP-Based 8-Bit Microconer
Devices Included in this Data Sheet:
FM8PE531MA: 14-pin OTP device
FM8PE531MB: 16-pin OTP device
GENERAL DESCRIPTION
The FM8PE531M is a low-cost, high speed, OTP-based 8-bit CMOS microcontrollers. It employs a RISC
architecture with only 37 instructions. All instructions are single cycle except for program branches which take two
cycles. The easy to use and easy to remember instruction set reduces development time significantly.
The FM8PE531M consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT),
Watchdog Timer, OTP, SRAM, tristate I/O port, I/O pull-high control, Power saving SLEEP mode, real time
programmable clock/counter, Interrupt, PWM, Comparator (with CVREF, Fixed Band Gap reference voltage), Wake-
up from SLEEP mode products.
FEATURES
2K Word on chip OTP-ROM and 88 Bytes on chip general purpose registers (SRAM).
6-level deep hardware stack.
One analog comparator.
- Internal reference voltage: 16-step CVREF module, 1.2V fixed voltage reference.
One 16-bit real timer/Counter with 2-bit programmable pre-scaler.
Two 8-bit fixed period-cycle PWM.
Three channel 15-bit RFC.
Six levels LVDT (Low Voltage Detect): 3.6V, 2.6V, 2.4V, 2.2V, 2.0V and 1.8V.
Power-up Reset Timer (PWRT)
On chip Watchdog Timer (WDT) with internal oscillator for reliable operation.
Two I/O port, PORTA and PORTB with independent direction control:
- 13 Bi-direction I/O pin (Programmable Pull-up enable in Input mode).
- One Input /Open-drain pin (IOB3/RSTB).
Two kinds of interrupt source:
- 4 internal interrupt sources: Timer1, RFC, Comparator and LVDT.
- 1 external interrupt sources: INT pin.
Wake-up from SLEEP:
- ALL pin (IOA5~IOA0, IOB7~IOB0) input change wake-up.
- WDT overflow.
Power saving SLEEP mode.
Selectable oscillator options:
-HIRC: Internal Resistor/Capacitor 8MHZ Oscillator.
-LIRC: Internal Resistor/Capacitor 55KHZ Oscillator.
Wide-operating voltage range: 2.0V to 5.5V.
This datasheet contains on. Feeling Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a rethis product. No rights under any patent accompany the sales of the product.
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Rev1.00.003 Feb 32, 2017
Page 1 of 55, FM8PE531M
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FM8PE531M
BLOCK DIAGRAM
Power-up
Timer
8MHZ
HIRC
Oscillator
Start-up Timer
55KHZ
LIRC
Power on
Reset
Stack
6-level
8-bit
RISC
CPU
Watchdog
Timer
OTP
2K-Wrod
Low voltage
Detect
SRAM
88-Byte
PORTA
PORTB
Band Gap
Reference
PWM0
8-bit
PWM1
8-bit
Timer1
16-bit
RFC
15-bit
Comparator
PIN CONNECTION
DIP/SOP14
IOA0/RFC0
IOB7/CIN-
IOB6/CIN+
VDD
1
2
3
4
5
6
7
14 IOA1/PWM0/RFC1
13 IOA2/PWM1/RFC2
12 IOA3/CX
FM8PE531MA
11 VSS
IOB5
10 IOB0/INT
IOB4
9
8
IOB1
IOB3/RSTB
IOB2/T1CKI
DIP/SOP16
IOA4
IOA0/RFC0
IOB7/CIN-
IOB6/CIN+
VDD
1
2
3
4
5
6
7
8
16 IOA5
15 IOA1/PWM0/RFC1
14 IOA2/PWM1/RFC2
13 IOA3/CX
12 VSS
8PE531MB
IOB5
11 IOB0/INT
10 IOB1
IOB4
IOB3/RSTB
9
IOB2/T1CKI
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Page 2 of 55, FM8PE531M
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FM8PE531M
PIN DESCRIPTIONS
Name
I/O
I/O
Description
Bi-direction I/O port with wake-up function (programmable Pull-high in Input mode).
The RC oscillator network output0 of RFC module.
IOA0/RFC0
Bi-direction I/O port with wake-up function (programmable Pull-high in Input mode).
IOA1/PWM0/RFC1 I/O PWM0 output.
The RC oscillator network output1 of RFC module.
Bi-direction I/O port with wake-up function (programmable Pull-high in Input mode).
IOA2/PWM1/RFC2 I/O PWM1 output.
The RC oscillator network output2 of RFC module.
Bi-direction I/O port with wake-up function (programmable Pull-high in Input mode).
The RC oscillator network input of RFC module.
IOA3/CX
I/O
IOA4, IOA5
IOB1, IOB4, IOB5
I/O Bi-direction I/O port with wake-up function (programmable Pull-high in Input mode).
Bi-direction I/O port with wake-up function (programmable Pull-high in Input mode).
External interrupt input.
IOB0/INT
I/O
Bi-direction I/O port with wake-up function (programmable Pull-high in Input mode).
External clock input to Timer1.
IOB2/T1CKI
I/O
Input pin only with system wake-up/pin change interrupt function; voltage on this
pin must not exceed VDD
System clear (RESET) input. This pin is an active low RESET to the device.
.
IOB3/RSTB
I/O
Open-Drain output.
Bi-direction I/O port with wake-up function (programmable Pull-high in Input mode).
Comparator positive input.
IOB6/CIN+
IOB7/CIN-
I/O
I/O
Bi-direction I/O port with wake-up function (programmable Pull-high in Input mode).
Comparator negative input.
Positive supply.
VDD
VSS
-
-
Ground.
Legend: I=input, O=output, I/O=input/output.
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Page 3 of 55, FM8PE531M
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FM8PE531M
1.0 MEMORY ORGANIZATION
FM8PE531M memory is organized into program memory and data memory.
1.1 Program Memory Organization
The FM8PE531M have a 12-bit Program Counter capable of addressing a 2K program memory space.
The RESET vector for the FM8PE531M is at 0x900.
The H/W interrupt vector is at 0x008.
CALL and GOTO instructions only have a 10-bit address range. This 10-bit address range allows a branch within a
1K program memory page size. To allow CALL and GOTO instructions to address the entire 2K program memory
address range for 8PE531M, there is other two bits to specify the program memory page. This paging bit comes
from the PG<1:0> bits (STATUS<6:5>, STATUS<6> must keep 0.).
Figure 1.1: Program Memory Map and STACK
0x97F
User`s Boot ROM
0x900
0x8FF
Reset Vector
Reserved
0x800
0x7FF
Stack 0~5
Program Counter
:
:
0x008 H/W Interrupt Vector
0x000
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Page 4 of 55, FM8PE531M
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FM8PE531M
1.2 Data Memory Organization
Data memory is composed of Special Function Registers and General Purpose Registers.
The General Purpose Registers are accessed either directly or indirectly through the FSR register.
The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of
the device.
In FM8PE531M, the data memory is partitioned into four banks. Switching between these banks requires the RP1,
RP0 bits in the FSR register to be configured for the desired bank.
Table 1.1: Registers File Map for FM8PE531M
Description
0 1
Bank 1
FSR<7:6>
0 0
Bank 0
1 0
Bank 2
1 1
Bank 3
Address
0x00
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
INDF
PCL
STATUS
FSR
IOSTA
PORTA
IOSTB
PORTB
T1CON
TMR1LB
TMR1HB
OSCCON
LVDTCON
INTEN
INTFLAG
PWMCON
P0DPR
P1DPR
RFCCON
RFCDLB
RFCDHB
AWUCON
APHCON
BWUCON
BPHCON
CMPCON1
CMPCON2
PCHBUF
0x18
|
0x2F
General
Purpose
Registers
Memory back to address in Bank 0
0x30
|
0x3F
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
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Page 5 of 55, FM8PE531M
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FM8PE531M
Table 1.2: Operational Registers Map
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
Unbanked
0x00 (r/w)
0x02 (r/w)
0x03 (r/w)
0x04 (r/w)
0x05 (r/w)
0x06 (r/w)
0x07 (r/w)
0x08 (r/w)
0x09 (r/w)
0x0A (r/w)
0x0B (r/w)
0x0C (r/w)
0x0D (r/w) LVDTCON
0x0E (r/w) INTEN
0x0F (r/w) INTFLAG
0x16 (w)
Bank0, 1
INDF
PCL
STATUS
FSR
IOSTA
PORTA
IOSTB
PORTB
T1CON
TMR1LB
TMR1HB
OSCCON
Uses contents of FSR to address data memory (not a physical register)
Low order 8 bits of PC
̅̅̅̅
TO
̅̅̅̅
PD
RST
RP1
-
PG1
RP0
-
PG0
Z
DC
C
Indirect data memory address pointer
IOSTA5
IOA5
IOSTB5
IOB5
-
IOSTA4
IOA4
IOSTB4
IOB4
IOSTA3
IOA3
IOSTB3
IOB3
IOSTA2
IOA2
IOSTB2
IOB2
GP
IOSTA1 IOSTA0
IOA1 IOA0
IOSTB1 IOSTB0
IOB1
T1CS
-
-
IOSTB7
IOB7
-
IOSTB6
IOB6
-
IOB0
T1EN
T1PS1
T1PS0
Low byte of 16-bit real-time clock/counter 1
High byte of 16-bit real-time clock/counter 1
WDTEN
EIS
GIE
-
IRCEN
RDPORT
WDTSEL1 WDTSEL0
CPUS
IRCF2
IRCF1
IRCF0
IOB3EN
LVREN
LVDTIE
LVDTIF
-
INTEDG LVDSEL2 LVDSEL1 LVDSEL0
-
-
-
-
-
-
CMPIE
CMPIF
-
INTIE
INTIF
-
RFCIE
RFCIF
2 MSBs Buffer of PC
T1IE
T1IF
PCHBUF
-
0x10 (r/w)
0x11 (r/w)
0x12 (r/w)
0x13 (r/w)
0x14 (r)
PWMCON
P0DPR
P1DPR
RFCCON
RFCDLB
RFCDHB
-
-
-
PWMCS2
PWMCS1
PWMCS0
P1EN
P0EN
PWM0 Duty Compare Pre-set register
PWM1 Duty Compare Pre-set register
RFCON
RFCOV
START
-
RFCMOD
-
-
RFCS1
RFCD9
RFCS0
RFCD8
Low byte of 15 bit RFC conversion result
0x15 (r)
RFCD14
RFCD13
RFCD12
RFCD11
RFCD10
Bank2, 3
0x10 (r/w)
0x11 (r/w)
0x12 (r/w)
0x13 (r/w)
0x14 (r/w) CMPCON1
0x15 (r/w) CMPCON2
AWUCON
APHCON
BWUCON
BPHCON
-
-
-
-
WUA5
/PHA5
WUB5
/PHB5
COUT
WUA4
/PHA4
WUB4
/PHB4
CINV
WUA3
/PHA3
WUB3
GP
CINS
CVR3
WUA2
/PHA2
WUB2
/PHB2
CM2
WUA1
/PHA1
WUB1
/PHB1
CM1
WUA0
/PHA0
WUB0
/PHB0
CM0
WUB7
/PHB7
-
WUB6
/PHB6
-
-
-
CVREN
CVRR
CVR2
CVR1
CVR0
Legend: - = unimplemented, read as ‘0’.
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Page 6 of 55, FM8PE531M
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FM8PE531M
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Operational Registers
2.1.1
INDF (Indirect Addressing Register)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x00
Name
INDF
Uses contents of FSR to address data memory (not a physical register)
Legend: x = unknown, more bits’ default state, please refer to Table 2.3.
The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the
register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0x00”) will read 0x00. Writing to
the INDF register indirectly results in a no-operation (although status bits may be affected).
The bits 5-0 of FSR register are used to select up to 64 registers (address 0x00 ~ 0x3F).
In FM8PE531M, the data memory is partitioned into four banks. Switching between these banks requires the RP1
and RP0 bits in the FSR register to configure for the desired bank. The lower locations of each bank are reserved
for the Special Function Registers. Above the Special Function Registers are General Purpose Registers. Some
Special Function Registers and some of General Purpose Registers from other banks are mirrored in bank 0 for
code reduction and quicker access.
RP1:RP0
Accessed Bank
0
0
1
1
0
1
0
1
0
1
2
3
Example 2.1: INDIRECT ADDRESSING
Register file 0x18 contains the value 0x10
Register file 0x19 contains the value 0x0A
Load the value 0x18 into the FSR Register
A read of the INDF Register will return the value of 0x10
Increment the value of the FSR Register by one (@FSR=0x19)
A read of the INDF register now will return the value of 0x0A.
Figure 2.1: Direct/Indirect Addressing
Direct Addressing
Indirect Addressing
From FSR register 0
RP1:RP0
5
From opcode
0
5
bank select
0 0
0 1
1 0
1 1
0x00
location select
addressing INDF register
location select
0x3F
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FM8PE531M
2.1.2
PCL (Low Byte of Program Counter) & Stack
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x02
Name
PCL
Low order 8 bits of PC
Note: more bits’ default state, please refer to Table 2.3.
FM8PE531M devices have a 12-bit wide Program Counter (PC) and six-level deep 12-bit hardware push/pop stack.
The low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called
the PCH register. This register contains the PC<11:8> bits and is not directly readable or writable. All updates to the
PCH register go through the PCHBUF register and PG<1:0> bits (STATUS<6:5>). As a program instruction is
executed, the Program Counter will contain the address of the next program instruction to be executed. The PC
value is increased by one, every instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PC<11:10> is updated from
the PG<1:0> bits (STATUS<6:5>). The PCL register is mapped to PC<7:0>.
For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The PC<11:10> is updated from the
PG<1:0> bits (STATUS<6:5>). The next PC will be loaded (PUSHed) into the top of STACK. The PCL register is
mapped to PC<7:0>.
For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL
register is mapped to PC<7:0>.
For any instruction where the PCL is the destination, the PC<7:0> is provided by the instruction word or ALU result;
the PC<9:8> bits will be fixed loading as ‘0’. The PC<11:8> is updated from the PCHBUF<1:0>bits and PG<1:0>
bits (STATUS<6:5>).
Please note: the PCHBUF is write-only register. If read, it will read as ‘0’.
Figure 2.2: Loading of PC in Different Situations
Situation 1: GOTO Instruction
PCH
11 10
PCL
9
8
7
0
PC
PG<1:0>
Opcode <9:0>
-
-
-
-
-
-
STATUS
Situation 2: CALL Instruction
STACK<11:0>
Opcode <9:0>
PCH
PCL
11 10
9
8
-
7
-
0
PC
PG<1:0>
-
-
-
-
STATUS
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FM8PE531M
Situation 3: RETIA, RETFIE, or RETURN Instruction
STACK<11:0>
PCH
11 10
PCL
9
8
-
7
-
0
PC
-
-
-
-
STATUS
Situation 4: Instruction with PCL as destination
PCH
PCL
11 10
9
8
7
0
PC
ALU result <7:0>
or Opcode <7:0>
-
-
-
-
-
-
-
-
PG<1:0>
-
PCHBUF
-
-
-
STATUS
2.1.3
STATUS (Status Register)
Read/Write-POR
R/W-0
B7
R/W-1
B6
R/W-0
B5
R-#
B4
̅̅̅̅
TO
R-#
B3
̅̅̅̅
PD
R/W-x
B2
Z
R/W-x
B1
R/W-x
B0
Address
0x03
Name
STATUS
RST
PG1
PG0
DC
C
Legend: x = unknown, # = refer Table 2.4 for detail description; more bits’ default state, please refer to Table 2.3.
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
̅̅̅̅
̅̅̅̅
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits
are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different
than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS
Register as 000u u1uu (where u = unchanged).
C:Carry/borrow bit.
ADDAR, ADDIA, ADCAR
= 0, No Carry occurred.
= 1, Carry occurred.
SUBAR, SUBIA, SBCAR
= 0, Borrow occurred.
= 1, No borrow occurred.
Note:A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)
instructions, this bit is loaded with either the high or low order bit of the source register.
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FM8PE531M
DC:Half carry/half borrow bit.
ADDAR, ADDIA, ADCAR
= 0, No Carry from the 4th low order bit of the result occurred.
= 1, Carry from the 4th low order bit of the result occurred.
SUBAR, SUBIA, SBCAR
= 0, Borrow from the 4th low order bit of the result occurred.
= 1, No Borrow from the 4th low order bit of the result occurred.
Z:Zero bit.
= 0, The result of a logic operation is not zero.
= 1, The result of a logic operation is zero.
̅̅̅̅
PD:Power down flag bit.
= 0, by the SLEEP instruction.
= 1, after power-up or by the CLRWDT instruction.
̅̅̅̅
TO:Time overflow flag bit.
= 0, a watch-dog time overflow occurred.
= 1, after power-up or by the CLRWDT or SLEEP instruction.
PG1:PG0:Program memory page select bits. Used for GOTO, CALL, or any instruction with PCL as destination.
PG1:PG0
Program Memory Page [Address]
Page 0 [0x000~0x3FF]
Page 1 [0x400~0x7FF]
Page 2 [0x900~0x97F]
Inhibit
0
0
1
1
0
1
0
1
Note: Page0 and 1 is User’s main program area, page2 is User’s Boot ROM.
RST:Bit for wake-up type.
= 0, Wake-up from other reset types.
= 1, Wake-up from SLEEP.
2.1.4
FSR (Indirect Data Memory Address Pointer)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x04
Name
FSR
RP1
RP0
Indirect data memory address pointer
Note: more bits’ default state, please refer to Table 2.3.
Bit5:Bit0:Select registers address in the indirect addressing mode. See section 2.1.1 for detail description.
RP1:RP0:These bits are used to switching the bank of four data memory banks. See section 2.1.1 for detail
description.
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FM8PE531M
2.1.5
IOSTA & IOSTB (Port I/O Control Register)
Read/Write-POR
-
B7
-
-
B6
-
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x05
Name
IOSTA
IOSTA5 IOSTA4 IOSTA3 IOSTA2 IOSTA1 IOSTA0
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x07
Name
IOSTB
IOSTB7 IOSTB6 IOSTB5 IOSTB4 IOSTB3 IOSTB2 IOSTB1 IOSTB0
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
IOSTA5:IOSTA0:PORTA I/O control bit.
= 0, PORTA pin configured as an output.
= 1, PORTA pin configured as an input (tristate).
IOSTB7:IOSTB0:PORTB I/O control bit.
= 0, PORTB pin configured as an output.
= 1, PORTB pin configured as an input (tristate).
Note: IOB3 is open-drain output only if IOSTB3 = 0.
2.1.6
PORTA & PORTB (Port Data Register)
Read/Write-POR
-
B7
-
-
B6
-
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x06
Name
PORTA
IOA5
IOA4
IOA3
IOA2
IOA1
IOA0
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x08
Name
PORTB
IOB7
IOB6
IOB5
IOB4
IOB3
IOB2
IOB1
IOB0
Legend: - = unimplemented, read as ‘0’, x = unknown, more bits’ default state, please refer to Table 2.3.
Reading the port (PORTA and PORTB register) reads the status of the pins independent of the pin’s input/output
modes. Writing to these ports will write to the port data latch.
IOA5:IOA0:PORTA I/O pin.
= 0, Port pin is low level.
= 1, Port pin is high level.
IOB7:IOB0:PORTB I/O pin.
= 0, Port pin is low level.
= 1, Port pin is high level.
Note:1. IOB3 is open-drain output only if IOSTB3 = 0.
2. Before setting IOB3 output 0, user must first IOB3EN bit set to 1, or they may cause
reset.
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2.1.7
T1CON (Timer 1 Control Register)
Read/Write-POR
-
B7
-
-
B6
-
-
B5
-
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x09
Name
T1CON
T1PS1
T1PS0
GP
T1CS
T1EN
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
T1EN:Timer1 Enable/Disable bit.
= 0, Disable Timer1.
= 1, Enable Timer1.
T1CS:Timer1 clock source select bit.
= 0, Internal instruction clock cycle.
= 1, External T1CKI pin.
GP:General purpose read/write bits.
T1PS1:T1PS0:Timer1 pre-scaler rate select bits.
T1PS1:T1PS0
Pre-scaler Rate
0
0
1
1
0
1
0
1
1:1
1:2
1:4
1:8
2.1.8
TMR1LB and TMR1HB (Timer 1 Clock/Counter Register)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0A
Name
TMR1LB
Low byte of 16-bit real-time clock/counter 1
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0B
Name
TMR1HB
High byte of 16-bit real-time clock/counter 1
Note: more bits’ default state, please refer to Table 2.3.
The Timer1 is a 16-bit timer/counter. The clock source of Timer1 can come from the instruction cycle clock or by an
external clock source (T1CKI pin) defined by T1CS bit (T1CON<1>). If T1CKI pin is selected, the Timer1 is
increased by T1CKI signal rising edge.
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Page 12 of 55, FM8PE531M
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2.1.9
OSCCON (Oscillator Control Register)
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0C
Name
OSCCON
WDTEN
IRCEN WDTSEL1 WDTSEL0
CPUS
IRCF2
IRCF1
IRCF0
Note: more bits’ default state, please refer to Table 2.3.
IRCF2:IRCF0:Internal RC oscillator frequency select bits.
IRCF2:IRCF0
Description
0
0
0
0
1
1
0
0
1
0
1
0
1
8MHZ
0
4MHZ
2MHZ
1
1
0
1MHZ
500KHZ
0
250KHZ
Other
No function, do not use.
CPUS:CPU clock source select bit.
= 0, CPU clock source is LIRC.
= 1, CPU clock source is HIRC, frequency defined by IRCF<2:0> bits.
WDTSEL1:WDTSEL0:Watchdog time-out select bits.
WDTSEL1:WDTSEL0
Time-out
2Sec
288mS
72mS
0
0
1
1
0
1
0
1
18mS
IRCEN:Internal RC enable bit
= 0, Disable internal RC clock source (Power down HIRC).
= 1, Enable internal RC clock source.
Note:Make sure the system clock (FCPU) been switch to LIRC source before power down internal RC.
WDTEN:Watchdog Timer enable bit.
= 0, WDT Disable.
= 1, WDT Enable.
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Page 13 of 55, FM8PE531M
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2.1.10 LVDTCON (LVDT Control Register)
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-0
B4
R/W-0
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x0D
Name
LVDTCON
EIS
RDPORT
IOB3EN
LVREN
INTEDG LVDSEL2 LVDSEL1 LVDSEL0
Note: more bits’ default state, please refer to Table 2.3.
LVDSEL2:LVDSEL0:Low voltage detects select bits.
LVDSEL2:LVDSEL0
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2.6V
2.4V
2.2V
1.8V
3.6V
2.0V
2.0V, Disable by Sleep
Disable
INTEDG:Interrupt edge select bit.
= 0, interrupt on falling edge of INT pin.
= 1, interrupt on rising edge of INT pin.
LVREN:LVDT reset function select bit.
= 0, Enable LVDT reset chip, reset voltage define by LVDSEL<2:0>.
= 1, Disable LVDT reset chip.
IOB3EN:IOB3/RSTB function select bit.
= 0, RSTB pin is select, IOB3 state of the bit is read as “0”.
= 1, IOB3 pin is select.
RDPORT:Read port control bit for output pins.
= 0, From pins.
= 1, From register.
EIS:Define the function of IOB0/INT pin.
= 0,IOB0 (bi-directional I/O pin) is selected. The path of INT is masked.
= 1,INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The path
of Port B input change of IOB0 pin is masked by hardware, the status of INT pin can also be read by way
of reading PORTB.
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2.1.11 INTEN (Interrupt Mask Register)
Read/Write-POR
R/W-0
B7
-
B6
-
-
B5
-
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0E
Name
INTEN
GIE
LVDTIE
CMPIE
INTIE
RFCIE
T1IE
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
T1IE:Timer1 overflow interrupt enable bit.
= 0, Disable the Timer1 overflow interrupt.
= 1, Enable the Timer1 overflow interrupt.
INTIE:External INT pin interrupt enable bit.
= 0, Disable the External INT pin interrupt.
= 1, Enable the External INT pin interrupt.
RFCIE:RFC module interrupt enable bit.
= 0, Disable the RFC module interrupt.
= 1, Enable the RFC module interrupt.
CMPIE:Comparator change interrupt enable bit.
= 0, Disable the comparator output change interrupt.
= 1, Enable the comparator output change interrupt.
LVDTIE:LVDT interrupt enable bit.
= 0, Disable the LVDT falling edge interrupt.
= 1, Enable the LVDT falling edge interrupt.
GIE:Global interrupt enable bit.
= 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue
execution at the instruction after the SLEEP instruction.
= 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device
will branch to the interrupt address (0x008).
Note:When an interrupt event occurs with the GIE bit and its corresponding interrupt enable bit are all set, the
GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will exit the
interrupt routine and set the GIE bit to re-enable interrupt.
2.1.12 INTFLAG (Interrupt Status Register)
Read/Write-POR
-
B7
-
-
B6
-
-
B5
-
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x0F
Name
INTFLAG
LVDTIF
CMPIF
INTIF
RFCIF
T1IF
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
T1IF:Timer1 overflow interrupt flag. Set when TMR1 overflows, reset by software.
RFCIF:RFC module interrupt flag. Set when RFC conversion is completed if RFCMOD = 0, reset by software.
INTIF:External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (LVDTCON<6>)) edge on INT
pin, reset by software.
LVDTIF:LVDT interrupt flag. Set when VDD under LVDT level, reset by software.
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Page 15 of 55, FM8PE531M
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2.1.13 PWMCON (PWM Control Register) (BANK0 & 1)
Read/Write-POR
-
B7
-
-
B6
-
-
B5
-
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x10
Name
PWMCON
PWMCS2 PWMCS1 PWMCS0
P1EN
P0EN
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
P0EN:PWM0 module enable bit.
= 0, Disable PWM0 output, IOA1/PWM0 pin is configured to IOA1 pin.
= 1, Enable PWM0 output, IOA1/PWM0 pin is configured to PWM0 pin.
P1EN:PWM1 module enable bit.
= 0, Disable PWM1 output, IOA2/PWM1 pin is configured to IOA2 pin.
= 1, Enable PWM1 output, IOA2/PWM1 pin is configured to PWM1 pin.
PWMCS2:PWMCS0:PWM clock source select bits.
PWMCS2:PWMCS0
PWM1 & 2 clock source
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8MHZ
4MHZ
2MHZ
1MHZ
500KHZ
250KHZ
125KHZ
No function
2.1.14 P0DPR (PWM0 Duty compare Pre-set Register) (BANK0 & 1)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x011
Name
P0DPR
PWM0 Duty Compare Pre-set register
Legend: x = unknown, more bits’ default state, please refer to Table 2.3.
P0DPR is PWM0 duty-cycle compare value pre-set register; see section 2.4 for detail description.
2.1.15 P1DPR (PWM1 Duty compare Pre-set Register) (BANK0 & 1)
Read/Write-POR
R/W-x
B7
R/W-x
B6
R/W-x
B5
R/W-x
B4
R/W-x
B3
R/W-x
B2
R/W-x
B1
R/W-x
B0
Address
0x012
Name
P1DPR
PWM1 Duty Compare Pre-set register
Legend: x = unknown, more bits’ default state, please refer to Table 2.3.
P1DPR is PWM1 duty-cycle compare value pre-set register; see section 2.4 for detail description.
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Page 16 of 55, FM8PE531M
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2.1.16 RFCCON (RFC Control Register) (BANK0 & 1)
Read/Write-POR
R/W-0
B7
R/W-0
B6
-
B5
-
R/W-0
B4
-
B3
-
-
B2
-
R/W-0
B1
R/W-0
B0
Address
0x013
Name
RFCCON
RFCON
START
RFCMOD
RFCS1
RFCS0
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
RFCS1:RFCS0:Select one the RFC oscillation network of RFCx (x = 0 to 2). The selected RFCx pin will be
configured as output pin if RFCON = 1. Other RFCx pins will behave as tristate input pins. If
RFCON = 0, all RFCx pins will behave as tristate input pins.
RFCS1:RFCS0
RFC channel
RFC0 pin is selected.
RFC1 pin is selected.
RFC2 pin is selected.
No function, don’t use.
0
0
1
1
0
1
0
1
RFCMOD:RFC mode selection bit.
= 0,Enable/disable the counter by CX signal, and the clock source of the counter is the internal system
clock (FCPU).
= 1,Enable/disable the counter by START bit, and the clock source of the counter is the CX signal.
START:RFC counter enable bit.
= 0, Stop the RFC conversion, reset by hardware when conversion is finished or by software.
= 1, RFC counter start to convert.
RFCON:RFC module enable bit
= 0, Disable RFC module, all the RFCx and CX pins will behave as tristate input pins.
= 1, Enable RFC module.
2.1.17 RFCDLB and RFCDHB (RFC Data Register Low Byte and High Byte) (BANK0 & 1)
Read/Write-POR
R-0
B7
R-0
B6
R-0
B5
R-0
B4
R-0
B3
R-0
B2
R-0
B1
R-0
B0
Address
0x14
Name
RFCDLB
Low byte of 15 bit RFC conversion result
Read/Write-POR
R-0
B7
R-0
B6
R-0
B5
R-0
B4
R-0
B3
R-0
B2
R-0
B1
R-0
B0
Address
0x15
Name
RFCDHB
RFCOV
RFCD14 RFCD13 RFCD12 RFCD11 RFCD10
RFCD9
RFCD8
Note: more bits’ default state, please refer to Table 2.3.
RFCD14:RFCD0:RFC conversion result.
RFCOV:RFC counter overflow flag. Set when RFC counter overflow, reset by RFC counter reset.
= 0, Not overflow.
= 1, Overflow.
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2.1.18 AWUCON (PORTA Wakeup Control Register) (BANK2 & 3)
Read/Write-POR
-
B7
-
-
B6
-
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x010
Name
AWUCON
WUA5
WUA4
WUA3
WUA2
WUA1
WUA0
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
WUA0:= 0, Disable the input change interrupt/wake-up function of IOA0 pin.
= 1, Enable the input change interrupt/wake-up function of IOA0 pin.
WUA1:= 0, Disable the input change interrupt/wake-up function of IOA1 pin.
= 1, Enable the input change interrupt/wake-up function of IOA1 pin.
WUA2:= 0, Disable the input change interrupt/wake-up function of IOA2 pin.
= 1, Enable the input change interrupt/wake-up function of IOA2 pin.
WUA3:= 0, Disable the input change interrupt/wake-up function of IOA3 pin.
= 1, Enable the input change interrupt/wake-up function of IOA3 pin.
WUA4:= 0, Disable the input change interrupt/wake-up function of IOA4 pin.
= 1, Enable the input change interrupt/wake-up function of IOA4 pin.
WUA5:= 0, Disable the input change interrupt/wake-up function of IOA5 pin.
= 1, Enable the input change interrupt/wake-up function of IOA5 pin.
2.1.19 APHCON (PORTA Pull-high Control Register) (BANK2 & 3)
Read/Write-POR
-
B7
-
-
B6
-
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x011
Name
APHCON
/PHA5
/PHA4
/PHA3
/PHA2
/PHA1
/PHA0
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
/PHA0:= 0, Enable the internal pull-high of IOA0 pin.
= 1, Disable the internal pull-high of IOA0 pin.
/PHA1:= 0, Enable the internal pull-high of IOA1 pin.
= 1, Disable the internal pull-high of IOA1 pin.
/PHA2:= 0, Enable the internal pull-high of IOA2 pin.
= 1, Disable the internal pull-high of IOA2 pin.
/PHA3:= 0, Enable the internal pull-high of IOA3 pin.
= 1, Disable the internal pull-high of IOA3 pin.
/PHA4:= 0, Enable the internal pull-high of IOA4 pin.
= 1, Disable the internal pull-high of IOA4 pin.
/PHA5:= 0, Enable the internal pull-high of IOA5 pin.
= 1, Disable the internal pull-high of IOA5 pin.
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2.1.20 BWUCON (PORTB Wakeup Control Register) (BANK2 & 3)
Read/Write-POR
R/W-0
B7
R/W-0
B6
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x012
Name
BWUCON
WUB7
WUB6
WUB5
WUB4
WUB3
WUB2
WUB1
WUB0
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
WUB0:= 0, Disable the input change interrupt/wake-up function of IOB0 pin.
= 1, Enable the input change interrupt/wake-up function of IOB0 pin.
WUB1:= 0, Disable the input change interrupt/wake-up function of IOB1 pin.
= 1, Enable the input change interrupt/wake-up function of IOB1 pin.
WUB2:= 0, Disable the input change interrupt/wake-up function of IOB2 pin.
= 1, Enable the input change interrupt/wake-up function of IOB2 pin.
WUB3:= 0, Disable the input change interrupt/wake-up function of IOB3 pin.
= 1, Enable the input change interrupt/wake-up function of IOB3 pin.
WUB4:= 0, Disable the input change interrupt/wake-up function of IOB4 pin.
= 1, Enable the input change interrupt/wake-up function of IOB4 pin.
WUB5:= 0, Disable the input change interrupt/wake-up function of IOB5 pin.
= 1, Enable the input change interrupt/wake-up function of IOB5 pin.
WUB6:= 0, Disable the input change interrupt/wake-up function of IOB6 pin.
= 1, Enable the input change interrupt/wake-up function of IOB6 pin.
WUB7:= 0, Disable the input change interrupt/wake-up function of IOB7 pin.
= 1, Enable the input change interrupt/wake-up function of IOB7 pin.
2.1.21 BPHCON (PORTB Pull-high Control Register) (BANK2 & 3)
Read/Write-POR
R/W-1
B7
R/W-1
B6
R/W-1
B5
R/W-1
B4
R/W-1
B3
R/W-1
B2
R/W-1
B1
R/W-1
B0
Address
0x013
Name
BPHCON
/PHB7
/PHB6
/PHB5
/PHB4
GP
/PHB2
/PHB1
/PHB0
Note: more bits’ default state, please refer to Table 2.3.
/PHB0:= 0, Enable the internal pull-high of IOB0 pin.
= 1, Disable the internal pull-high of IOB0 pin.
/PHB1:= 0, Enable the internal pull-high of IOB1 pin.
= 1, Disable the internal pull-high of IOB1 pin.
/PHB2:= 0, Enable the internal pull-high of IOB2 pin.
= 1, Disable the internal pull-high of IOB2 pin.
GP:General purpose read/write bits.
/PHB4:= 0, Enable the internal pull-high of IOB4 pin.
= 1, Disable the internal pull-high of IOB4 pin.
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/PHB5:= 0, Enable the internal pull-high of IOB5 pin.
= 1, Disable the internal pull-high of IOB5 pin.
/PHB6:= 0, Enable the internal pull-high of IOB6 pin.
= 1, Disable the internal pull-high of IOB6 pin.
/PHB7:= 0, Enable the internal pull-high of IOB7 pin.
= 1, Disable the internal pull-high of IOB7 pin.
2.1.22 CMPCON1 (Comparator Control Register1)
Read/Write-POR
-
B7
-
-
B6
-
R-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x014
Name
CMPCON1
COUT
CINV
CINS
CM2
CM1
CM0
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
CM2:CM0:Comparator mode select bits. See Figure 2.10 for detail description.
CM2:CM0
Comparator mode
Comparator Off (lowest power).
Comparator Reset (low power).
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Multiplexed Input with CVREF
.
Multiplexed Input with Bandgap.
Comparator with CVREF & Bandgap.
Comparator with IOB7 & IOB6.
CINS:Comparator input switch bit.
When CM2:CM0 = 100 or 101:
= 0, VIN- connects to CIN-.
= 1, VIN- connects to CIN+.
Other modes:
Ignore.
CINV:Comparator output polarity inversion bit.
= 0, Output not inverted.
= 1, Output inverted.
COUT:Comparator output bit.
If C1INV = 0:= 0, VIN+ < VIN-.
= 1, VIN+ > VIN-.
If C1INV = 1:= 0, VIN+ > VIN-.
= 1, VIN+ < VIN-.
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2.1.23 CMPCON2 (Comparator Control Register2)
Read/Write-POR
-
B7
-
-
B6
-
R/W-0
B5
R/W-0
B4
R/W-0
B3
R/W-0
B2
R/W-0
B1
R/W-0
B0
Address
0x15
Name
CMPCON2
CVREN
CVRR
CVR3
CVR2
CVR1
CVR0
Legend: - = unimplemented, read as ‘0’; more bits’ default state, please refer to Table 2.3.
CVR3:CVR0:Comparator voltage reference (CVREF) select bits.
(CVR3:CVR0)*VDD
If CVRR = 1 (low range): CVREF
=
18
VDD (CVR3:CVR0)*VDD
+
If CVRR = 0 (high range): CVREF
=
10
20
CVRR:CVREF range selection bit.
= 0, High range.
= 1, Low range.
CVREN:Comparator voltage reference (CVREF) module enable bit.
= 0, Disable CVREF module.
= 1, Enable CVREF module.
2.1.24 PCHBUF (High Byte Buffer of Program Counter)
Read/Write-POR
-
B7
-
-
B6
-
-
B5
-
-
B4
-
-
B3
-
-
B2
-
W-0
B1
W-0
B0
Address
0x16
Name
PCHBUF
2 MSBs Buffer of PC
Legend: - = unimplemented, read as ‘0’, more bits’ default state, please refer to Table 2.3.
Bit1:Bit0:See 2.1.2 for detail description.
2.1.25 ACC (Accumulator)
Read/Write-POR
R/W-x
Address
N/A
Name
ACC
B7
B6
B5
B4
B3
B2
B1
B0
Accumulator
Legend: x = unknown, more bits’ default state, please refer to Table 2.3.
Accumulator is an internal data transfer, or instruction operand holding. It cannot be addressed.
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FM8PE531M
2.2 I/O Ports
PORTA and PORTB are bi-directional tristate I/O ports. PORTA are 6-pin I/O port, PORTB are 8-pin I/O port. Please
note that IOB3 is an input or open-drain output pin.
All I/O pins have data direction control registers (IOSTA, IOSTB) which can configure these pins as output or input.
IOA<5:0>, IOB<5:4> and IOB<2:0> have its corresponding pull-high control bits (APHCON and BPHCON register)
to enable the weak internal pull-high. The weak pull-high is automatically turned off when the pin is configured as
an output pin.
All I/O pins also provides the input change interrupt/wake-up function. Each pin has its corresponding input change
interrupt/wake-up enable bits (AWUCON and BWUCON) to select the input change interrupt/wake-up source.
The IOB0 is also an external interrupt input signal.
Please note, IOB3 voltage on these pins must not exceed VDD, otherwise it will cause the pin breakdown.
Figure 2.3: Block Diagram of I/O Pins
IOA5 ~ IOA0, IOB5, IOB4, IOB2, IOB1:
DATA BUS
D
Q
IOST
Latch
WR IOSTx
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
D
Q
Q
Set RST bit
WUxn
Latch
EN
Pull-high are not shown in this figure
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FM8PE531M
IOB0:
DATA BUS
D
Q
IOST
Latch
IOST R
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
EN
Q
D
RD PORT
Q
Q
Set RST bit
Latch
WUB0
EIS
EN
INT
INTEDG
EIS
Pull-high are not shown in this figure
IOB3:
DATA BUS
D
Q
IOST
Latch
WR IOSTB3
EN
Q
Q
I/O PIN
D
DATA
Latch
WR PORT
RD PORT
EN
Q
D
IOB3EN
Q
Q
Set RST bit
WUB3
Latch
EN
Voltage on this pin must not exceed VDD
.
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FM8PE531M
2.3 Timer1
The Timer1 is a 16-bit timer/counter with the following features:
Readable and writable.
Internal or external clock selection.
Asynchronous operation.
Interrupt on overflow from 0xFFFF to 0x0000.
Wake-up upon overflow
Figure 2.4: Block Diagram of the Timer1
TMR1 Register
TMR1H TMR1L
IOB2/T1CKI
1
Prescaler
/1, /2, /4, /8
Set T1IF flag
on overflow
Instruction Cycle (FCPU/2)
0
T1CS
T1EN
T1PS1:T1PS0
2.3.1
Timer1 Pre-scaler
Timer1 has four pre-scaler options allowing 1, 2, 4, or 8 divisions of the clock input. The T1PS<1:0> bits
(T1CON<4:3>) control the pre-scaler counter. The pre-scaler counter is not directly readable or writable; however,
the pre-scaler counter is cleared upon a write to TMR1HB or TMR1LB.
2.3.1.1 Using Timer1 with an Internal Clock: Timer mode
Timer mode is selected by clearing the T1CS bit (T1CON<1>). In timer mode, the timer1 register (TMR1HB and
TMR1LB) will increment every instruction cycle (pre-scaler ratio is 1:1).
2.3.1.2 Using Timer1 with an External Clock: Counter mode
Counter mode is selected by setting the T1CS bit (T1CON<1>). In this mode, Timer1 will increment either on every
rising edge of pin T1CKl.
In this mode, the external clock input is not synchronized. The timer continues to increment asynchronous to the
internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, which
will wake-up the processor. However, special precautions in software are needed to read/write the timer.
Reading TMR1HB or TMR1LB, while the timer is running from an external asynchronous clock, will ensure a valid
read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit
values itself, poses certain problems, since the timer may overflow between the reads.
For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention
may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable
value in the timer register.
2.3.2
Timer1 Operation During SLEEP
Timer1 can be operate during SLEEP mode. In this mode, an external clock source can be used to increment the
counter.
The device will wake-up on an overflow. If the GIE bit (INTEN<7>) is set, the device will wake-up and jump to the
interrupt vector. If the GIE bit is cleared, the device will wake-up and continue execution at the instruction after the
SLEEP instruction.
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2.4 Pulse Width Modulation (PWM)
FM8PE531M provides two PWM output shared with IOA1/PWM0 and IOA2/PWM1 pins. These PWM period-time
are fixed and cannot be programmable.
The PWM0 and PWM1 outputs has a maximum resolution of 8-bits, the duty cycle of the output can vary from 0%
to 99%.
The PWM0 and PWM1 period time can be calculated as follows:
256
Period time of PWM =
PWM Clock source frequency
The PWM0 duty cycle time can be calculated as follows:
P0DPR
Duty cycle time of PWM0 =
PWM Clock source frequency
Similarly, this formula can be used directly on PWM1.
Figure 2.5: PWM0 Output Waveform
00 01
40
FE FF 00
FE FF
Period internal counter:
PWM Period
PWM Duty
PWM1 Output:
Note: Red line will be fixed output “LOW”.
Example 2.2: PWM0 & PWM1Setting
ASM Language Code
#include
<8PE531M.ASH>
…
MOVIA
0x40
MOVAR
P0DPR
; PWM0 Duty time = 0x40 / 8MHZ = 8uS
; PWM1 Duty time = 0x80 / 8MHZ = 16uS
MOVIA
0x80
MOVAR
P1DPR
MOVIA
MOVAR
…
0x03
; PWM Clock source to 8MHZ, and Enable PWM0 & PWM1 output
; Period cycle = 256 / 8MHZ = 32uS
PWMCON
C Language Code
#include <8PE531M.h>
…
P0DPR=0x40;
P1DPR=0x80;
PWMCON=0x03;
…
// PWM0 Duty time = 0x40 / 8MHZ = 8uS
// PWM1 Duty time = 0x80 / 8MHZ =16uS
// PWM Clock source to 8MHZ, and enable PWM0 & PWM1 output
// Period cycle = 256 / 8MHZ = 32uS
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FM8PE531M
2.5 Resistor to Frequency Converter (RFC)
The Resistor to Frequency Converter (RFC) can compare two different sensors with the reference resistor
separately.
This RFC contains four external pins:
CX: the oscillation Schmitt trigger input (IOA3/CX pin).
RFC0 ~ RFC2: the resistor/sensor output pin 0 ~ 2 (RFC0, RFC1, and RFC2 pins)
Figure 2.6: The Block Diagram of RFC
RFCS1:0 = 2
RRFC2
Counter active signal, controlled by
CX pin signal if RFCMOD = 0, or
START bit if RFCMOD = 1
RFCS1:0 = 1
RFC2
RRFC1
Set RCIF Flag
when count finished
RFC1
RFCS1:0 = 0
RRFC0
EN
15-bit counter
RFC0
1
CLKIN
FCPU
0
CX
CCx
RFCMOD
Table 2.1: The Description of RFC Control Bits
Select one the RFC oscillation network of RFCx (x = 0 to 2). The selected RFCx pin will be
RFCS1:RFCS0configured as RFCx output pin if RFCON = 1. Other RFCx pins will still behave as tristate input
pins. If RFCON = 0, all RFCx pins will behave as tristate input pins.
= 0, Enable/disable the counter by CX signal, and the clock source of the counter is the internal
RFCMOD
system clock (FCPU).
= 1, Enable/disable the counter by START bit, and the clock source of the counter is the CX signal.
= 0, Stop the RFC conversion
START
= 1, RFC counter start to convert. Reset by hardware after conversion is finished.
Note: Don’t clear START bit by software during the RFC conversion.
= 0, Disable RFC module, all the RFCx and CX pins will behave as tristate input pins.
= 1, Enable RFC module.
RFCON
2.5.1
RC Oscillator Network
The RFC circuitry may build up 3 RC oscillation networks through RFC0 to RFC2 and CX pins with external resistors.
Only one RC oscillation network may be active at a time. When the oscillation network is built up, the count active
pulse will be generated by the oscillation network and transferred to the 15-bit counter through the CX pin. It will
then enable or disable the 15-bit counter in order to count the oscillation clock. The 15-bit RFC counter is cleared
when a value is written to RFCCON register, RFCON bit is cleared, and during any kind of reset as well.
How to build the RC oscillation network?
1. Connect the resistor and capacitor on RFCx (x = 0 to 2, if needed) and CX pins.
2. Switch all of the needed RFCx and CX pins to input mode.
3. Enable the RFC module by set the RFCON bit.
4. Select one of RFCx pins by RFCS1:RFCS0 bits to enable the output pin for RC networks respectively. The
selected RFCx will output low at this time. Other RFCx pins will become of a tristate type.
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5. Set START bit to enable the RC oscillation network and 15-bit counter. The RC oscillation network will not
operate if this bit has not been set. If RFCMOD bit = 0, Clear the START bit by H/W will finish the conversion,
and the RFCIF flag will be set (if enable interrupt). If RFCMOD bit = 1, Clear the START bit by S/W will finish
the conversion, and the RFCIF flag will not be set.
2.5.2
Enable/Disable the Counter by CX Signal
In this mode, CX pin is the signal to control the counter period and the clock source of the counter comes from the
internal system clock (FCPU).
The counter will start to count after the first rising edge signal applied on the CX pin after the RFCON bit
(RFCCON<7>) is set. Once the second rising edge is applied to the CX pin after the counter is enabled, the counter
will stop counting. And after the second falling edge is applied to the CX pin, the RFC block will clear the START bit
and set the RFC interrupt flag RFCIF bit (INTFLAG<1>) if RFCIE bit (INTEN<1>) is set.
User also can be polling the RFCON or RFCIF bit to check if the conversion is finished.
Figure 2.7: The Sample of the RFC Counter Controlled by the CX Pin (RFCMOD = 0)
START
CX signal on pin
CX signal
By S/W
By H/W
Counter active
RFC Counter
FCPU
0
1
2
3
N-2 N-1
N
Counter active
By S/W
Counter starts
to count
Counting stops, caused by
the 2nd falling edge of CX
2.5.3
Enable/Disable the Counter by START Bit
In this mode, START bit is the signal to control the counter period and the clock source of the counter comes from
the CX pin.
The counter will start to count after the START bit (RFCCON<6>) is set. Once the START bit is cleared by S/W, the
counter will stop counting. In this case, the RFC interrupt flag RFCIF bit (INTFLAG<1>) will not be set.
Figure 2.8: The Sample of the RFC Counter Controlled by the START Bit (RFCMOD = 1)
START
Counter active
RFC Counter
CX signal
By S/W
0
1
2
3
4
5
6
7
N-2 N-1
N
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2.6 Comparator Module
The FM8PE513M device has one comparator. The inputs to the comparator is multiplexed with the IOB6 and IOB7
pins. There is an on-chip comparator voltage reference (CVREF and Bandgap) that can also be applied to an input
of these comparators.
The compared results are stored in the COUT bit of CMPCON1 register. This bit is read-only.
All pins configured as comparator analog inputs will read as a ‘0’s.
Figure 2.9: Single Comparator
VIN-
VIN+
VIN-
+
-
Output
VIN+
2.6.1
Comparator output state can be read internally via the COUT bit of the CMPCON1 register.
2.6.2 Comparator Output Polarity
Comparator Output State
The polarity of the comparator output can be inverted by setting the CINV bit of the CMPCON1 register. Clearing
CINV bit to “0” results in a non-inverted output. Setting CINV bit to “1” results in a polarity inverted output.
Table 2.2: COUT Status/Output vs. Input Conditions & CINV
Input Conditions
VIN+ < VIN-
VIN+ > VIN-
VIN+ < VIN-
VIN+ > VIN-
Comparator Output
CINV
COUT
0
1
0
1
0
0
1
1
0
1
1
0
2.6.3
Comparator Input Switch
The inverting input (VIN-) of the comparators may be switched between two analog pins if CM<2:0> = 100 or 101.
In these modes, both pins remain in analog mode regardless of which pin is selected as the input. The CINS bit of
the CMPCON1 register controls the comparator input switch.
2.6.4
Comparator Operating Modes
There are six modes of operation for the comparator. The CM<2:0> bits of CMPCON1 register used to select these
modes.
The pins denoted as “A” will read as a “0” regardless the state of the I/O pin or the I/O control IOSTBx bit. If pins
are used as comparator analog inputs, the corresponding IOSTBx bit must be set to “1”.
Pins denoted as “D” means pins not used as comparator, these pins are normal I/O pin.
If the comparator mode is changed, the comparator output level may not be valid for a specified period of time, so
comparator interrupts should be disabled during a comparator mode change.
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Figure 2.10: Comparator I/O Operating Modes
CM2:CM0 = 011
CM2:CM0 = 000, 001, 010
Comparator Reset (low power)
Comparator OFF (lowest power)
A
D
IOB7/CIN-
IOB6/CIN+
IOB7/CIN-
IOB6/CIN+
-
-
OFFNOTE1
OFFNOTE1
A
D
+
+
CM2:CM0 = 111
CM2:CM0 = 101
Comparator with Output
Multiplexed Input with Bandgap
A
IOB7/CIN-
CINS=0
A
-
IOB7/CIN-
-
A
CINS=1
IOB6/CIN+
COUT
COUT
A
+
+
IOB6/CIN+
From Bandgap
CM2:CM0 = 110
CM2:CM0 = 100
Comparator with bandgap and CVREF
Multiplexed Input with CVREF
A
IOB7/CIN-
CINS=0
-
Bandgap
CVREF
-
A
CINS=1
IOB6/CIN+
COUT
COUT
+
+
From CVREF module
Note1:Reads as “0”.
Note2:A = Comparator analog input, pins always read ‘0’.
D = Digital I/O.
CINS = Comparator input switch select bit (CMPCON1<3>).
COUT = Comparator output bit (CMPCON1<5>).
2.6.5
Comparator Voltage Reference (CVREF)
The comparator module also allows the selection of an internally generated voltage reference for one of the
comparator inputs. The internal reference signal is used for three of the six comparator modes. The CMPCON2
register controls the voltage reference module.
The voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range. The following
equations determine the output voltages:
(CVR3:CVR0)*VDD
If CVRR = 1 (low range): CVREF
=
18
VDD (CVR3:CVR0)*VDD
= +
If CVRR = 0 (high range): CVREF
Figure 2.11: Comparator Voltage Reference
10
20
16 stages
8R
R
R
R
R
VDD
8R
CVRR
CVREN
CVREF
to comparator
MUX
CVR<3:0>
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2.7 Interrupts
The FM8PE531M has up to four sources of interrupt:
1. Timer1 overflow interrupt.
2. RFC module interrupt.
3. External interrupt INT pin.
4. Comparator interrupt.
5. Programmable voltage LVDT interrupt.
6. PORTA and PORTB external interrupt.
INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.
A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all
interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register
regardless of the status of the GIE bit.
When an interrupt event occurs with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will
be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 0x008.
The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
2.7.1
Timer1 Interrupt
An overflow (0xFFFF 0x0000) in the TMR1HB:TMR1LB register pair will set the flag bit T1IF (INTFLAG<0>). To
enable the interrupt, T1IE bit (INTEN<0>), and GIE bit (INTEN<7>) should be set.
The T1IF bit must be cleared by software before re-enabling this interrupt.
2.7.2
RFC Module Interrupt
After RFC conversion is finished, the RFCIF flag (INTFLAG<1>) will be set. This interrupt can be disabled by
clearing RFCIE bit (INTEN<1>).
The RFC interrupt only for CX mode (RFCMOD=0).
2.7.3
External INT Interrupt
External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (LVDTCON<3>).
When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set.
The INTIE bit (INTEN<2>) and GIE bit (INTEN<7>) must be set to enable the interrupt. If any of these bits cleared,
the interrupt is not enable.
The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP. If
GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit cleared, the program
will execute next PC after wake-up.
2.7.4
Comparator Status Change Interrupt
The comparator interrupt flag bit CMPIF (INTFLAG<3>) is set whenever there is a change in the output value of the
comparator.
The CMPIE bit (INTEN<3>) and GIE bit (INTEN<7>) must be set to enable the interrupt. If any of these bits cleared,
the interrupt is not enable.
2.7.5
Programmable voltage LVDT interrupt
When the VDD voltage drops below programmed voltage (Selection by LVDTSEL<2:0> bits (LVDTCON<2:0>)), flag
bit LVDTIF (INTFLAG<4>) will be set. In addition, the LVDTIF bit can be clear by software.
The LVDTIE bit (INTEN<4>), LVREN bit (LVDTCON<4>), and GIE bit (INTEN<7>) must be set to enable the
interrupt. If any of these bits cleared, the interrupt is not enable.
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2.7.6
PORTA and PORTB external Interrupt
Before the PORTA and PORTB input change interrupt are enable, reading PORTA and PORTB (any instruction
accessed to PORTA and PORTB, including read/write instructions) is necessary. Any pin which corresponding
WUAn (AWUCON<5:0>) or WUBn bit (BWUCON<7:0>) is cleared to “0” or configured as output or IOB0 pin
configured as INT pin will be excluded from this function.
The PORTA and PORTB input change interrupt also can wake-up the system from SLEEP condition, the GIE bit
decides whether the processor branches to the interrupt vector following wake-up. If GIE bit was set, the program
will execute interrupt service routine after wake-up; or if GIE bit cleared, the program will execute next PC after
wake-up.
2.8 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction.
̅̅̅̅
̅̅̅̅
When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer will
be cleared and keeps running, and the oscillator driver is turned off.
All I/O pins maintain the status they had before the SLEEP instruction was executed.
2.8.1
Wake-up from SLEEP Mode
The device can wake-up from SLEEP mode through one of the following events:
1. RSTB reset.
2. WDT time-out wake-up (if enabled).
3. Interrupt from IOB0/INT pin, PORTA or PORTB change, or Timer1 interrupt.
External RSTB reset and WDT time-out will cause a device reset. Interrupt event is considered a continuation of
program execution.
̅̅̅̅
̅̅̅̅
̅̅̅̅
In the reset case, the PD and TO bits can be used to determine the cause of device reset. The PD bit is set on
̅̅̅̅
power-up and is cleared when SLEEP instruction is executed. The TO bit is cleared if a WDT time-out occurred.
The RST bit is set on PORTA or PORTB input change wake-up.
For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up
is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the SLEEP
instruction. If the GIE bit is set, the device will branch to the interrupt address (0x008).
2.9 Reset
FM8PE531M devices may be RESET in one of the following ways:
1. Power-on Reset (POR)
2. Brown-out Reset (BOR)
3. RSTB Pin Reset
4. WDT time-out Reset during normal operation
Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and
unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT
Reset.
A Power-on RESET pulse is generated on-chip when VDD rise is detected. To use this feature, the user merely ties
the RSTB pin to VDD
.
On-chip Low Voltage Detector (LVD) places the device into reset when VDD is below a fixed voltage. This ensures
that the device does not continue program execution outside the valid operation VDD range. Brown-out RESET is
typically used in AC line or heavy loads switched applications.
A RSTB or WDT time-out during normal operation also results in a device RESET.
̅̅̅̅
̅̅̅̅
The PD and TO bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.
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Table 2.3: Reset Conditions for All Registers
Power-on Reset
RSTB Reset
WDT Reset
Register
Address
Brown-out Reset
xxxx xxxx
xxxx xxxx
0000 0000
0101 1xxx
00xx xxxx
--11 1111
--xx xxxx
1111 1111
xxxx xxxx
---0 0000
0000 0000
0000 0000
1111 0000
1110 0111
0--0 0000
---0 0000
---0 0000
xxxx xxxx
xxxx xxxx
00-0 --00
0000 0000
0000 0000
--00 0000
--11 1111
0000 0000
1111 1111
--00 0000
--00 0000
---- --00
xxxx xxxx
ACC
INDF
N/A
0x00
xxxx xxxx
uuuu uuuu
0000 0000
010# #xxx
00uu uuuu
--11 1111
--xx xxxx
1111 1111
xxxx xxxx
---0 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0--0 0000
---0 0000
---0 0000
xxxx xxxx
xxxx xxxx
00-0 --00
0000 0000
0000 0000
--00 0000
--11 1111
0000 0000
1111 1111
--00 0000
--00 0000
---- --00
uuuu uuuu
PCL
0x02
STATUS
FSR
0x03
0x04
IOSTA
0x05
PORTA
0x06
IOSTB
0x07
PORTB
0x08
T1CON
0x09
TMR1LB
TMR1HB
OSCCON
LVDTCON
INTEN
0x0A
0x0B
0x0C
0x0D
0x0E
INTFLAG
PWMCON
P0DPR
0x0F
0x10, Bank0 & 1
0x11, Bank0 & 1
0x12, Bank0 & 1
0x13, Bank0 & 1
0x14, Bank0 & 1
0x15, Bank0 & 1
0x10, Bank2 & 3
0x11, Bank2 & 3
0x12, Bank2 & 3
0x13, Bank2 & 3
0x14, Bank2 & 3
0x15, Bank2 & 3
0x16
P1DPR
RFCCON
RFCDLB
RFCDHB
AWUCON
APHCON
BWUCON
BPHCON
CMPCON1
CMPCON2
PCHBUF
General Purpose Registers
0x18 ~ 0x3F
Legend:u = unchanged, x = unknown, - = unimplemented, read as 0.
# = refer to the following table for possible values.
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̅̅̅̅ ̅̅̅̅
Table 2.4: RST / TO / PD Status after Reset or Wake-up
̅̅̅̅
̅̅̅̅
RST
0
TO
PD
RESET was caused by
Power-on Reset
1
1
u
1
0
0
1
1
1
u
0
1
0
0
0
Brown-out reset
0
RSTB Reset during normal operation
RSTB Reset during SLEEP
0
0
WDT Reset during normal operation
WDT Wake-up during SLEEP
Wake-up on pin change during SLEEP
0
1
Legend: u = unchanged
̅̅̅̅ ̅̅̅̅
Table 2.5: Events AffectingTO / PDStatus Bits
̅̅̅̅
̅̅̅̅
PD
Event
TO
Power-on
1
0
1
1
1
u
0
1
WDT Time-Out
SLEEP instruction
CLRWDT instruction
Legend: u = unchanged
2.10 Oscillator Configurations
The system clock can be generated from two internal oscillators. The HIRC (8MHZ) is a calibrated high-frequency
oscillator. The LIRC (55KHZ) is an un-calibrated low-frequency oscillator.
The Oscillator Control register (OSCCON) controls the system clock and frequency selection options. The OSCCON
register contains IRCF (frequency selection bits), CPUS (CPU clock source select bit) and IRCEN (HIRC module
enable bit), see section 2.1.9 for detail description.
Figure 2.12: System Clock Source Block Diagram
LIRC
55KHZ
Power-up Timer (PWRT)
Watchdog Timer (WDT)
HIRC
8MHZ
8MHZ
4MHZ
000
001
010
011
100
101
0
1
2MHZ
System clock (FCPU
)
IRCEN
1MHZ
500KHZ
250KHZ
CPUS
IRCF<2:0>
To Internal Block
FHIRC
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2.10.1 How to change system clock speed
The system clock speed can be selected by setting the Clock Divider Select bits IRCF<2:0> of the OSCCON register.
When you want to switch clock source, Need follow these steps:
1. Switching the clock source to LIRC (CPUS bit (OSCCON<3>) set to 0).
2. Insert a NOP instruction.
3. Specify new clock speed** (see note2).
4. Insert a NOP instruction.
5. Switching the clock source to HIRC (CPUS bit (OSCCON<3>) set to 1).
6. Insert a NOP instruction.
Example 2.3: Change clock speed (Change to 4MHZ
)
ASM Language Code
#include
<8PE531M.ASH>
…
BCR
NOP
BSR
BCR
BCR
NOP
BSR
NOP
…
OSCCON,CPUS_B
; Switch system clock source to LIRC, required.
OSCCON,IRCF0_B
OSCCON,IRCF1_B
OSCCON,IRCF2_B
; 4MHZ IRCF<2:0> is 001
OSCCON,CPUS_B
; Switch system clock source to HIRC, required.
C Language Code
#include <8PE531M.h>
…
OSCCONbits.CPUS=0;
NOP();
// Switch system clock source to LIRC, required.
OSCCONbits.IRCF0=1;
OSCCONbits.IRCF1=0;
OSCCONbits.IRCF2=0;
NOP();
// 4MHZ IRCF<2:0> is 001
OSCCONbits.CPUS=1;
NOP();
// Switch system clock source to HIRC, required.
…
Note:1. OSCCON register prohibits direct write value, Need using BSR/BCR instruction.
2. When switch to another speed, setting procedures must same as example.
3. Failure to follow set procedures could result in unexpected situation occurs.
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3.0 INSTRUCTION SET
Mnemonic,
Operands
Status
Affected
Description
Operation
Cycles
BCR
R, bit Clear bit in R
R, bit Set bit in R
0 R<b>
1
1
-
-
-
-
-
BSR
1 R<b>
BTRSC
BTRSS
NOP
R, bit Test bit in R, Skip if Clear
R, bit Test bit in R, Skip if Set
No Operation
Skip if R<b> = 0
Skip if R<b> = 1
No operation
0x00 WDT,
1/2
1/2
1
̅̅̅̅ ̅̅̅̅
CLRWDT
Clear Watchdog Timer
1
TO,PD
0x00 WDT,
0x00 WDT pre-scaler
̅̅̅̅ ̅̅̅̅
SLEEP
Go into power-down mode
Return from subroutine
Return from interrupt, set GIE bit
Clear ACC
1
2
2
TO,PD
RETURN
RETFIE
Top of Stack PC
-
-
Top of Stack PC,
1 GIE
CLRA
CLRR
MOVAR
MOVR
DECR
0x00 ACC
0x00 R
ACC R
1
1
1
1
1
Z
Z
-
R
R
Clear R
Move ACC to R
R, d Move R
R dest
Z
Z
R, d Decrement R
R - 1 dest
R - 1 dest,
Skip if result = 0
DECRSZ
INCR
R, d Decrement R, Skip if 0
R, d Increment R
1/2
1
-
Z
-
R + 1 dest
R + 1 dest,
Skip if result = 0
INCRSZ
R, d Increment R, Skip if 0
1/2
ADDAR
SUBAR
ADCAR
SBCAR
ANDAR
IORAR
XORAR
COMR
R, d Add ACC and R
R + ACC dest
R - ACC dest
1
1
1
1
1
1
1
1
C, DC, Z
R, d Subtract ACC from R
R, d Add ACC and R with Carry
R, d Subtract ACC from R with Carry
R, d AND ACC with R
C, DC, Z
R + ACC + C dest
C, DC, Z
̅̅̅̅̅̅̅
R + ACC + C dest
C, DC, Z
ACC and R dest
ACC or R dest
R xor ACC dest
Z
Z
Z
Z
R, d Inclusive OR ACC with R
R, d Exclusive OR ACC with R
R, d Complement R
ꢀ
R dest
R<7> C,
RLR
R, d Rotate left R through Carry
R<6:0> dest<7:1>,
C dest<0>
1
C
C dest<7>,
RRR
R, d Rotate right R through Carry
R, d Swap R
R<7:1> dest<6:0>,
R<0> C
1
1
C
-
R<3:0> dest<7:4>,
R<7:4> dest<3:0>
SWAPR
MOVIA
ADDIA
SUBIA
ANDIA
IORIA
I
I
I
I
I
I
Move Immediate to ACC
I ACC
1
1
1
1
1
1
-
Add ACC and Immediate
Subtract ACC from Immediate
AND Immediate with ACC
OR Immediate with ACC
I + ACC ACC
I - ACC ACC
ACC and I ACC
ACC or I ACC
ACC xor I ACC
C, DC, Z
C, DC, Z
Z
Z
Z
XORIA
Exclusive OR Immediate to ACC
I ACC,
Top of Stack PC
RETIA
I
Return, place Immediate in ACC
2
-
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Mnemonic,
Operands
Status
Description
Operation
Cycles
Affected
PC + 1 Top of Stack,
I PC<10:0>
CALL
I
Call subroutine
2
-
GOTO
BANK
I
I
Unconditional branch
I PC<10:0>
I RP<1:0>
2
1
-
-
Move Immediate to memory bank bits
Note:1. 2 cycles for skip, else 1 cycle.
2. bit:Bit address within an 8-bit register R
R:Register address (0x00 to 0x3F)
I:Immediate data
ACC:Accumulator
d:Destination select;
=0 (store result in ACC)
=1 (store result in file register R)
dest:Destination
PC:Program Counter
WDT:Watchdog Timer Counter
GIE:Global interrupt enable bit
̅̅̅̅
TO:Time-out bit
̅̅̅̅
PD:Power-down bit
C:Carry bit
DC:Digital carry bit
Z:Zero bit
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ADCAR
Add ACC and R with Carry
Syntax:
ADCAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
Status Affected:
Description:
R + ACC + C dest
C, DC, Z
Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDAR
Syntax:
Add ACC and R
ADDAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
ACC + R dest
Status Affected:
Description:
C, DC, Z
Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ADDIA
Add ACC and Immediate
Syntax:
ADDIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC + I ACC
C, DC, Z
Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the
ACC register.
1
Cycles:
ANDAR
Syntax:
AND ACC and R
ANDAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
ACC and R dest
Status Affected:
Description:
Z
The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored in
the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Cycles:
ANDIA
AND Immediate with ACC
Syntax:
ANDIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC AND I ACC
Z
The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
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BANK
Move Immediate to memory bank bits
Syntax:
BANK I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x0≤I≤0x3
I RP<1:0>
None
The memory bank bits are loaded with the 2-bit immediate ‘I’.
1
BCR
Clear Bit in R
BCR R, b
0x00≤R≤0x3F
0x0≤b≤0x7
0 R<b>
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
Clear bit ‘b’ in register ‘R’.
1
BSR
Set Bit in R
BSR R, b
0x00≤R≤0x3F
0x0≤b≤0x7
1 R<b>
None
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Set bit ‘b’ in register ‘R’.
1
BTRSC
Test Bit in R, Skip if Clear
Syntax:
BTRSC R, b
Operands:
0x00≤R≤0x3F
0x0≤b≤0x7
Operation:
Skip if R<b> = 0
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.
If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is discarded,
and a NOP is executed instead making this a 2-cycle instruction.
1/2
Cycles:
BTRSS
Test Bit in R, Skip if Set
Syntax:
BTRSS R, b
Operands:
0x00≤R≤0x3F
0x0≤b≤0x7
Operation:
Skip if R<b> = 1
Status Affected:
Description:
None
If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is
discarded and a NOP is executed instead, making this a 2-cycle instruction.
1/2
Cycles:
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CALL
Subroutine Call
Syntax:
CALL I
Operands:
Operation:
0x000≤I≤0x3FF
PC + 1 Top of Stack,
I PC<9:0>
Status Affected:
Description:
None
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit immediate
address is loaded into PC bits <9:0>.
2
Cycles:
CLRA
Clear ACC
Syntax:
CLRA
Operands:
Operation:
None
0x00 ACC;
1 Z
Status Affected:
Description:
Cycles:
Z
The ACC register is cleared. Zero bit (Z) is set.
1
CLRR
Clear R
Syntax:
CLRR R
Operands:
Operation:
0x00≤R≤0x3F
0x00 R;
1 Z
Status Affected:
Description:
Cycles:
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
CLRWDT
Syntax:
Clear Watchdog Timer
CLRWDT
Operands:
Operation:
None
0x00 WDT;
̅̅̅̅
1 TO;
̅̅̅̅
1 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
Cycles:
TO, PD
̅̅̅̅
̅̅̅̅
The CLRWDT instruction resets the WDT. The status bits TO and PD will be set.
1
COMR
Complement R
COMR R, d
0x00≤R≤0x3F
d∈[0,1]
Syntax:
Operands:
ꢀ
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
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DECR
Decrement R
Syntax:
DECR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
Status Affected:
Description:
R - 1 dest
Z
Decrement of register ‘R’. If ‘d’ is 0 the result is stored in the ACC register. If ‘d’ is 1 the result
is stored back in register ‘R’.
1
Cycles:
DECRSZ
Syntax:
Decrement R, Skip if 0
DECRSZ R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R - 1 dest; skip if result =0
Status Affected:
Description:
None
The contents of register ‘R’ are decrement. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ’R’.
If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is
executed instead and making it a 2-cycle instruction.
1/2
Cycles:
GOTO
Unconditional Branch
Syntax:
GOTO I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x000≤I≤0x3FF
I PC<9:0>
None
GOTO is an unconditional branch. The 10-bit immediate value is loaded into PC bits <9:0>.
2
INCR
Increment R
Syntax:
Operands:
INCR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
R + 1 dest
Status Affected:
Description:
Z
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
INCRSZ
Syntax:
Increment R, Skip if 0
INCRSZ R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R + 1 dest, skip if result = 0
Status Affected:
Description:
None
The contents of register ‘R’ are increment. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is the result is stored back in register ‘R’.
If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP
is executed instead and making it a 2-cycle instruction.
1/2
Cycles:
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IORAR
OR ACC with R
Syntax:
IORAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
Status Affected:
Description:
ACC or R dest
Z
Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
IORIA
OR Immediate with ACC
Syntax:
IORIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC or I ACC
Z
The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
MOVAR
Move ACC to R
Syntax:
MOVAR R
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x00≤R≤0x3F
ACC R
None
Move data from the ACC register to register ‘R’.
1
MOVIA
Move Immediate to ACC
Syntax:
MOVIA I
Operands:
Operation:
Status Affected:
Description:
Cycles:
0x00≤I≤0xFF
I ACC
None
The 8-bit immediate ‘I’ is loaded into the ACC register. The don’t cares will assemble as 0s.
1
MOVR
Move R
Syntax:
MOVR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R dest
Status Affected:
Description:
Z
The contents of register ‘R’ is moved to destination ‘d’. If ‘d’ is 0, destination is the ACC
register. If ‘d’ is 1, the destination is file register ‘R’. ‘d’ is 1 is useful to test a file register since
status flag Z is affected.
1
Cycles:
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NOP
No Operation
Syntax:
NOP
Operands:
Operation:
Status Affected:
Description:
Cycles:
None
No operation
None
No operation.
1
RETFIE
Return from Interrupt, Set ‘GIE’ Bit
Syntax:
RETFIE
Operands:
Operation:
None
Top of Stack PC
1 GIE
None
Status Affected:
Description:
The program counter is loaded from the top of the stack (the return address). The ‘GIE’ bit is
set to 1. This is a 2-cycle instruction.
2
Cycles:
RETIA
Return with Immediate in ACC
Syntax:
RETIA I
Operands:
Operation:
0x00≤I≤0xFF
I ACC;
Top of Stack PC
Status Affected:
Description:
None
The ACC register is loaded with the 8-bit immediate ‘I’. The program counter is loaded from
the top of the stack (the return address). This is a 2-cycle instruction.
2
Cycles:
RETURN
Return from Subroutine
Syntax:
RETURN
Operands:
Operation:
Status Affected:
Description:
None
Top of Stack PC
None
The program counter is loaded from the top of the stack (the return address). This is a two-
cycle instruction.
2
Cycles:
RLR
Rotate Left R through Carry
Syntax:
Operands:
RLR R, d
0x00≤R≤0x3F
d∈[0,1]
Operation:
R<7> C;
R<6:0> dest<7:1>;
C dest<0>
Status Affected:
Description:
C
The contents of register ‘R’ are rotated left one bit to the left through the Carry Flag. If ‘d’ is 0
the result is placed in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
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RRR
Rotate Right R through Carry
Syntax:
RRR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
C dest<7>;
R<7:1> dest<6:0>;
R<0> C
C
Status Affected:
Description:
The contents of register ‘R’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0
the result is placed in the ACC register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
Cycles:
SLEEP
Enter SLEEP Mode
SLEEP
Syntax:
Operands:
Operation:
None
0x00 WDT;
̅̅̅̅
1 TO;
̅̅̅̅
0 PD
̅̅̅̅ ̅̅̅̅
Status Affected:
Description:
TO, PD
̅̅̅̅
̅̅̅̅
Time-out status bit (TO) is set. The power-down status bit (PD) is cleared. The WDT is cleared.
The processor is put into SLEEP mode.
1
Cycles:
SBCAR
Syntax:
Subtract ACC from R with Carry
SBCAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
̅̅̅̅̅̅̅
Operation:
R + ACC + C dest
Status Affected:
Description:
C, DC, Z
Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the
result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBAR
Syntax:
Subtract ACC from R
SUBAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R - ACC dest
Status Affected:
Description:
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
SUBIA
Subtract ACC from Immediate
Syntax:
SUBIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
I - ACC ACC
C, DC, Z
Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result
is placed in the ACC register.
1
Cycles:
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SWAPR
Swap nibbles in R
Syntax:
SWAPR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
R<3:0> dest<7:4>;
R<7:4> dest<3:0>
None
Status Affected:
Description:
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
Cycles:
XORAR
Syntax:
Exclusive OR ACC with R
XORAR R, d
Operands:
0x00≤R≤0x3F
d∈[0,1]
Operation:
ACC xor R dest
Status Affected:
Description:
Z
Exclusive OR the contents of the ACC register with register ’R’. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Cycles:
XORIA
Exclusive OR Immediate with ACC
Syntax:
XORIA I
Operands:
Operation:
Status Affected:
Description:
0x00≤I≤0xFF
ACC xor I ACC
Z
The contents of the ACC register are XOR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Cycles:
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4.0 ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
-
Min.
0
Typ.
-
Max.
70
Unit
°C
Ambient Operating
Temperature
Store Temperature
DC Supply Voltage
Input Voltage with respect to
Ground
-
-
-65
0
-
-
150
6
°C
V
VDD
-
-0.3
-
VDD+0.3
V
HBM (Human Body Mode)
MM (Machine Mode)
Soldering, 10 Sec
-
-
-
2.0
200
-
-
-
KV
V
ESD Susceptibility
(Standard)
Lead Temperature
250
°C
4.1 PACKAGE IR Re-flow Soldering Curve
250 5
10 1 sec
150 10
90 30 sec
2 ~ 5 / sec
2 ~ 5 / sec
Time
5.0 RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Parameter
DC Supply Voltage
Operating Temperature
Conditions
Min.
2.0
0
Typ.
Max.
5.5
Unit
V
-
-
-
-
70
°C
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6.0 ELECTRICAL CHARACTERISTICS
6.1 AC Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
FHIRC
Description
High Frequency IRC
Low Frequency IRC
Min.
-3%
Typ.
8
Max.
+3%
Unit
MHZ
KHZ
VDD
Low VDD=3V
High VDD=5V
3V
5V
3V
-
-
-
-
-
-
-
-
-
-
43.74
60.78
23.45
16.8
93.88
67.2
381
-
-
-
-
-
-
-
-
-
-
FLIRC
-
WDT=18mS
WDT=72mS
WDT=288mS
WDT=2Sec
5V
3V
5V
3V
5V
3V
5V
mS
TWDT
WDT period time
272
3.05
2.17
S
Note:1. At any time, a 0.1μF decoupling capacitor should be connected between VDD and VSS and device as
close as possible.
2. LIRC 55KHZ is an uncalibrated low-frequency oscillator, frequency is for reference only.
6.2 DC Characteristics
Ta=25°C
Test Conditions
Symbol
VIH
Description
Min.
Typ.
Max.
VDD
Unit
VDD
3V
5V
3V
5V
3V
5V
3V
5V
-
Conditions
-
-
-
-
1.26
1.78
1.25
1.9
Input high voltage, I/O Ports
(Without IOB3 Pin)
-
V
Input high voltage, IBO3 Pin
-
-
-
VDD
0.99
1.24
0.92
1.15
3.6
-
-
Input low voltage, I/O Ports
(Without IOB3 Pin)
VSS
VSS
VIL
V
V
-
Input low voltage, IOB3 Pin
-
LVDT=3.6V
-
-
-
LVDT=2.6
-
2.6
-
-
LVDT=2.4V
LVDT=2.2V
LVDT=2.0V
LVDT=1.8V
-
-
2.4
-
VLVDT
Low voltage detect
-
2.2
-
-
-
2.0
-
-
-
1.8
-
3V
5V
3V
5V
3V
5V
3V
5V
-
1.61
4.12
9.51
22.69
10.55
25.59
20.55
68.51
-
I/O Ports Drive current
(Without IOB3 Pin)
I/O Ports Sink current
(Without IOB3 Pin)
IOH
IOL
IPH
VOH=0.9VDD
VOL=0.1VDD
VOL=0.1VDD
Input pin at VSS
mA
mA
uA
1.5
-
-
-
15
-
-
-
IOB3 Pin Sink current
-
-
-
-
I/O Ports Pull-high current
55
85
Web site: http://www.feeling-techcom.tw
Rev1.00.003 Feb 23, 2017
Page 46 of 55, FM8PE531M
EELING
FM8PE531M
Test Conditions
Conditions
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
5V LVDT3.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.13
0.43
1.46
0.46
1.57
0.49
1.7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
-
3V
LVDT2.6
5V
ILVDT
LVDT current
3V
uA
LVDT2.4
5V
3V
LVDT2.2
5V
3V
0.53
1.83
0.6
LVDT2.0
5V
ILVDT
LVDT current
WDT current
uA
3V
LVDT1.8
5V
2.05
0.47
2.68
<1
3V
IWDT
ISB
Sleep mode, 2Sec
uA
uA
5V
3V
5V
3V
5V
Sleep mode (Power down)
current
-
<1
0.64
1.28
IDD
Operating current
FCPU = 8MHZ (4MIPS)
mA
6.3 Comparator Characteristics
Ta=25°C
Unit
Test Conditions
Conditions
Symbol
VIO
Description
Min.
Typ.
Max.
-
VDD
-
Comparator input offset
voltage
-
-
-
-
-
mV
V
Comparator input common
mode voltage
VICM
-
0
VDD
6.4 ELECTRICAL CHARACTERISTICS Typical charts of FM8PE531M
6.4.1
HIRC 8MHZ vs. Temperature
0.50%
Avg-5V
0.30%
0.10%
Avg-3V
-10
0
10
20
25
30
40
50
60
70
80
-0.10%
-0.30%
-0.50%
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.00.003 Feb 23, 2017
Page 47 of 55, FM8PE531M
EELING
FM8PE531M
6.4.2
LIRC 55KHZ vs. Temperature
30.00%
20.00%
10.00%
0.00%
-10
0
10
20
25
30
40
50
60
70
80
-10.00%
-20.00%
Temperature
Note: Curves are for design reference only.
6.4.3
HIRC 8 MHZ vs. Supply Voltage (Ta=25°C)
3.00%
8M HV
8M LV
2.00%
1.00%
0.00%
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
Voltage
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
-1.00%
-2.00%
-3.00%
Note: Curves are for design reference only.
6.4.4
LIRC 55KHZ vs. Supply Voltage (Ta=25°C)
20.00%
10.00%
0.00%
1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
-10.00%
-20.00%
-30.00%
-40.00%
-50.00%
-60.00%
-70.00%
Voltage
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.00.003 Feb 23, 2017
Page 48 of 55, FM8PE531M
EELING
FM8PE531M
6.4.5
Low Voltage Detect (LVDT=2.0V) vs. Temperature
2.50
Avg-2.0V
2.00
1.50
1.00
0.50
0.00
-10
0
10
20
25
30
40
40
40
50
50
50
60
60
60
70
70
70
80
Temperature
Note: Curves are for design reference only.
6.4.6
Low Voltage Detect (LVDT=3.6V) vs. Temperature
4.00
Avg-3.6V
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
-10
0
10
20
25
30
80
Temperature
Note: Curves are for design reference only.
6.4.7
Low Voltage Detect (LVDT=1.8V) vs. Temperature
2.00
Avg-1.8V
1.50
1.00
0.50
0.00
-10
0
10
20
25
30
80
Temperature
Note: Curves are for design reference only.
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Rev1.00.003 Feb 23, 2017
Page 49 of 55, FM8PE531M
EELING
FM8PE531M
6.4.8
Low Voltage Detect (LVDT=2.2V) vs. Temperature
2.50
Avg-2.2V
2.00
1.50
1.00
0.50
0.00
-10
0
10
20
25
30
40
40
40
50
50
50
60
60
60
70
70
70
80
Temperature
Note: Curves are for design reference only.
6.4.9
Low Voltage Detect (LVDT=2.4V) vs. Temperature
3.00
Avg-2.4V
2.50
2.00
1.50
1.00
0.50
0.00
-10
0
10
20
25
30
80
Temperature
Note: Curves are for design reference only.
6.4.10 Low Voltage Detect (LVDT=2.6V) vs. Temperature
3.00
2.50
2.00
1.50
1.00
0.50
0.00
Avg-2.6V
-10
0
10
20
25
30
80
Temperature
Note: Curves are for design reference only.
Web site: http://www.feeling-techcom.tw
Rev1.00.003 Feb 23, 2017
Page 50 of 55, FM8PE531M
EELING
FM8PE531M
7.0 PACKAGE DIMENSION
7.1 14-PIN PDIP
D
SEATING PLANE
0.018typ.
0.060typ.
0.100typ.
Dimension In Inches
Symbols
Min
Nom
-
Max
0.210
-
A
A1
A2
D
-
0.015
0.125
0.735
-
0.130
0.750
0.300 BSC.
0.250
0.130
0.355
7°
0.135
0.775
E
E1
L
0.245
0.115
0.335
0°
0.255
0.150
0.375
15°
eB
θ°
Web site: http://www.feeling-techcom.tw
Rev1.00.003 Feb 23, 2017
Page 51 of 55, FM8PE531M
EELING
FM8PE531M
7.2 16-PIN PDIP
SEATING PLANE
0.018typ.
0.060typ.
0.100typ.
Dimension In Inches
Symbols
Min
-
Nom
-
Max
A
A1
A2
D
0.172
0.038
0.135
0.775
0.015
0.125
0.735
-
0.130
0.755
0.300 BSC.
0.250
0.130
0.355
7°
E
E1
L
0.245
0.115
0.335
0°
0.255
0.150
0.375
15°
eB
θ°
Web site: http://www.feeling-techcom.tw
Rev1.00.003 Feb 23, 2017
Page 52 of 55, FM8PE531M
EELING
FM8PE531M
7.3 14-PIN SOP 150mil
View "A"
C
D
View "A"
GAUGE PLANE
SEATING PLANE
b
θo
L
0.10
e
Dimension In MM
Symbols
Min
Nom
Max
A
A1
A2
b
-
-
1.75
0.25
-
0.10
1.25
0.31
0.10
-
-
-
0.51
0.25
C
-
D
8.65 BSC
6.00 BSC
3.90 BSC
1.27 BSC
-
E
E1
e
L
0.40
0.25
0o
1.27
0.50
8o
H
θ
-
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Rev1.00.003 Feb 23, 2017
Page 53 of 55, FM8PE531M
EELING
FM8PE531M
7.4 16-PIN SOP 150mil
View "A"
C
D
View "A"
GAUGE PLANE
SEATING PLANE
b
θo
L
0.10
e
Dimension In MM
Symbols
Min
-
Nom
Max
A
A1
A2
b
-
1.75
0.25
-
0.10
1.25
0.31
0.10
-
-
-
0.51
0.25
c
-
D
E
9.90 BSC
6.00 BSC
E1
e
3.90 BSC
1.27 BSC
L
0.40
0.25
0o
-
-
-
1.27
0.50
8o
H
θ
Web site: http://www.feeling-techcom.tw
Rev1.00.003 Feb 23, 2017
Page 54 of 55, FM8PE531M
EELING
FM8PE531M
8.0 ORDERING INFORMATION
OTP Type MCU
FM8PE531MAP
Package Type Pin Count Package Size
MOQ
MSL Sample Stock
PDIP
SOP
PDIP
SOP
14
14
16
16
300mil
300mil
300mil
150mil
3,000EA/Tube
3
3
3
3
Available
Available
Available
Available
3,000EA/Tube
3,000EA/Reel
FM8PE531MAP
FM8PE531MBP
FM8PE531MBD
3,000EA/Tube
3,000EA/Tube
3,000EA/Reel
Web site: http://www.feeling-techcom.tw
Rev1.00.003 Feb 23, 2017
Page 55 of 55, FM8PE531M
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