AOD4132 [FREESCALE]
N-Channel Enhancement Mode Field; N沟道增强型场
| 型号： | AOD4132 |
| 厂家： | 
Freescale |
| 描述： | N-Channel Enhancement Mode Field |
| 文件： | 总6页 (文件大小：725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOD4132
N-Channel Enhancement Mode Field
Effect Transistor
General Description
provide excellent RDS(ON), low gate charge and low
The AOD4132 uses advanced trench technology to
gate resistance. This device is ideally suited for use as a low side switch in CPU core power conversion.
Features
VDS (V) = 30V
ID = 85A (VGS = 10V)
RDS(ON) < 4mΩ (VGS = 10V)
RDS(ON) < 6mΩ (VGS = 4.5V)
D
G
S
Absolute Maximum Ratings TA=25°C unless otherwise noted
Parameter
Symbol
Maximum
Units
Drain-Source Voltage
VDS
30
V
Gate-Source Voltage
VGS
±20
85
V
A
G
TC=25°C
TC=100°C
Continuous Drain
Current B,G
B
ID
63
Pulsed Drain Current
Avalanche Current C
Repetitive avalanche energy L=0.1mH C
IDM
IAR
EAR
200
30
A
112
100
50
mJ
TC=25°C
PD
W
Power Dissipation B
TC=100°C
TA=25°C
2.5
PDSM
W
°C
Power Dissipation A
1.6
TA=70°C
Junction and Storage Temperature Range
TJ, TSTG
-55 to 175
Thermal Characteristics
Parameter
Symbol
Typ
14.2
39
Max
20
Units
°C/W
°C/W
°C/W
Maximum Junction-to-Ambient A
Maximum Junction-to-Ambient A
t ≤ 10s
RθJA
Steady-State
Steady-State
50
Maximum Junction-to-Case C
RθJC
0.8
1.5
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AOD4132
N-Channel Enhancement Mode Field
Effect Transistor
Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
STATIC PARAMETERS
ID=250µA, VGS=0V
BVDSS
Drain-Source Breakdown Voltage
30
V
V
DS=24V, VGS=0V
1
5
IDSS
Zero Gate Voltage Drain Current
µA
TJ=55°C
VDS=0V, VGS= ±20V
VDS=VGS ID=250µA
VGS=10V, VDS=5V
IGSS
Gate-Body leakage current
Gate Threshold Voltage
On state drain current
100
3
nA
V
VGS(th)
ID(ON)
1
1.8
85
A
V
GS=10V, ID=20A
2.8
4.4
4
5.5
6
mΩ
RDS(ON)
Static Drain-Source On-Resistance
TJ=125°C
VGS=4.5V, ID=20A
VDS=5V, ID=20A
IS=1A,VGS=0V
4.4
mΩ
S
gFS
VSD
IS
Forward Transconductance
Diode Forward Voltage
106
0.72
1
V
Maximum Body-Diode Continuous Current
85
A
DYNAMIC PARAMETERS
Ciss
Coss
Crss
Rg
Input Capacitance
3700
700
4400
0.7
pF
pF
pF
Ω
VGS=0V, VDS=15V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
390
VGS=0V, VDS=0V, f=1MHz
0.54
SWITCHING PARAMETERS
Qg(10V) Total Gate Charge
Qg(4.5V) Total Gate Charge
63
33
76
40
nC
nC
nC
nC
ns
VGS=4.5V, VDS=15V, ID=20A
Qgs
Qgd
tD(on)
tr
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
8.6
17.6
12
V
GS=10V, VDS=15V, RL=0.75Ω,
15.5
40
ns
RGEN=3Ω
tD(off)
tf
ns
14
ns
trr
IF=20A, dI/dt=100A/µs
IF=20A, dI/dt=100A/µs
34
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
41
ns
Qrr
30
nC
A: The value of R θJA is measured with the device mounted on 1in 2 FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The
Power dissipation PDSM is based on steady-state R θJA and the maximum allowed junction temperature of 150°C. The value in any given
application depends on the user's specific board design, and the maximum temperature fo 175°C may be u sed if the PCB or heatsink allows it.
B. The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.
C: Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C.
D. The R θJA is the sum of the thermal impedence from junction to case R θJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300 µs pulses, duty cycle 0.5% max.
F. These tests are performed with the device mounted on 1 in 2 FR-4 board with 2oz. Copper, in a still air environment with T A=25°C. The SOA
curve provides a single pulse rating.
G. The maximum current rating is limited by the package current capability.
*This device is guaranteed green after data code 8X11 (Sep 1ST 2008).
Rev 1: Sep 2008
2/6
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AOD4132
N-Channel Enhancement Mode Field
Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
60
60
10V
50
50
VDS=5V
4.0V
40
40
125°C
30
20
30
3.5V
25°C
20
10
0
10
0
VGS=3V
1.5
2
2.5
3
3.5
4
4.5
0
1
2
3
4
5
V
GS(Volts)
V
DS (Volts)
Figure 2: Transfer Characteristics
Fig 1: On-Region Characteristics
8
7
6
5
4
3
2
1.6
ID=20A
1.4
1.2
1
VGS=4.5V
VGS=10V
VGS=4.5V
VGS=10V
0.8
0
10
20
30
40
50
60
0
25
50
75
100
125
150
175
I
D (A)
Temperature (°C)
Figure 3: On-Resistance vs. Drain Current and
Gate Voltage
Figure 4: On-Resistance vs. Junction
Temperature
8
6
4
2
0
1.0E+02
1.0E+01
1.0E+00
1.0E-01
1.0E-02
1.0E-03
1.0E-04
1.0E-05
125°C
125°C
25°C
ID=20A
25°C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
2
4
6
8
10
VSD (Volts)
V
GS (Volts)
Figure 6: Body-Diode Characteristics
Figure 5: On-Resistance vs. Gate-Source Voltage
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AOD4132
N-Channel Enhancement Mode Field
Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
5000
10
VDS=15V
ID=20A
Ciss
4000
8
6
4
2
0
3000
2000
Coss
1000
Crss
0
0
10
20
30
40
50
60
70
0
5
10
15
20
25
30
Qg (nC)
V
DS (Volts)
Figure 7: Gate-Charge Characteristics
Figure 8: Capacitance Characteristics
1000
100
10
100
80
60
40
20
0
TJ(Max)=150°C
TA=25°C
RDS(ON)
10µs
100µs
limited
1ms
10ms
0.1s
1s
10s
DC
TJ(Max)=150°C
TA=25°C
1
0.1
0.01
0.1
1
10
100
1000
0.1
1
10
100
Pulse Width (s)
VDS (Volts)
Figure 10: Single Pulse Power Rating Junction-to-
Ambient (Note F)
Figure 9: Maximum Forward Biased Safe
Operating Area (Note F)
10
D=Ton/T
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
TJ,PK=TA+PDM.ZθJA.RθJA
RθJA=50°C/W
1
0.1
0.01
PD
Ton
T
Single Pulse
0.001
0.001
0.00001
0.0001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance (Note F)
4/6
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AOD4132
N-Channel Enhancement Mode Field
Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS
120
100
80
60
40
20
0
120
100
80
60
40
20
0
TA=25°C
L ID
tA
=
BV −VDD
TA=150°C
0.000001
0.00001
Time in avalanche, tA (s)
Figure 12: Single Pulse Avalanche capability
0.0001
0.001
0.01
0
25
50
75
CASE (°C)
Figure 13: Power De-rating (Note B)
100
125
150
175
T
100
80
60
40
20
0
0
25
50
75
CASE (°C)
Figure 14: Current De-rating (Note B)
100
125
150
175
T
5/6
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AOD4132
N-Channel Enhancement Mode Field
Effect Transistor
Gate Charge Test Circuit & Waveform
Vgs
Qg
10V
+
VDC
+
Qgs
Qgd
Vds
VDC
-
-
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
Vds
90%
+
DUT
Vdd
Vgs
VDC
Rg
-
10%
Vgs
Vgs
td(on)
t
r
td(off)
t
f
ton
toff
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
L
EAR= 1/2 LIA2R
BVDSS
Vds
Id
Vgs
Vds
+
Vgs
Vdd
I AR
VDC
Id
Rg
-
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Qrr = - Idt
Vds +
Vds -
Ig
DUT
Vgs
trr
L
Isd
I F
Isd
Vgs
dI/dt
I RM
+
Vdd
VDC
Vdd
-
Vds
6/6
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