MB84VA2105 [FUJITSU]
16M (x 8) FLASH MEMORY & 1M (x 8) STATIC RAM; 16M ( ×8 )闪存和1M ( ×8 )静态RAM型号: | MB84VA2105 |
厂家: | FUJITSU |
描述: | 16M (x 8) FLASH MEMORY & 1M (x 8) STATIC RAM |
文件: | 总29页 (文件大小:378K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50108-1E
MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (× 8) FLASH MEMORY &
1M (× 8) STATIC RAM
MB84VA2104-10/MB84VA2105-10
■ FEATURES
• Power supply voltage of 2.7 to 3.6 V
• High performance
100 ns maximum access time
• Operating Temperature
–20 to +85°C
— FLASH MEMORY
• Minimum 100,000 write/erase cycles
• Sector erase architecture
One 16 K byte, two 8 K bytes, one 32 K byte, and thirty one 64 K bytes.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Boot Code Sector Architecture
MB84VA2104: Top sector
MB84VA2105: Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
Please refer to "MBM29LV160T/B" data sheet in detailed function
— SRAM
• Power dissipation
Operating: 35 mA max.
Standby : 30 µA max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 2.0 V to 3.6 V
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VA2104-10/MB84VA2105-10
■ BLOCK DIAGRAM
VCCf
VSS
A0 to A20
RY/BY
A0 to A20
16 M bit
Flash Memory
RESET
CEf
DQ0 to DQ7
VCCs
VSS
A0 to A16
1 M bit
Static RAM
WE
OE
CE1s
CE2s
2
MB84VA2104-10/MB84VA2105-10
■ PIN ASSIGNMENTS
(Top View)
A
B
C
D
E
F
G
H
6
5
4
3
2
1
CE1s
A10
VSS
DQ5
DQ7
A8
DQ1
DQ2
DQ4
A5
A1
A2
A4
CE2s
RY/BY
A9
A15
A0
A3
A7
OE
A11
DQ0
N.C.
CEf
VSS
A6
A19
N.C.
VCCf
N.C.
RESET A16
DQ3
N.C.
N.C.
A13
A20
A14
A18
VCCs
N.C.
A17
DQ6
N.C.
A12
WE
N.C.
Table 1 Pin Configuration
Function
Input/
Output
Pin
A0 to A16
A17 to A20
DQ0 to DQ7
CEf
Address Inputs (Common)
Address Input (Flash)
I
I
Data Inputs/Outputs (Common)
Chip Enable (Flash)
I/O
I
CE1s
CE2s
OE
Chip Enable (SRAM)
I
Chip Enable (SRAM)
I
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash)
I
WE
I
RY/BY
RESET
N.C.
O
Hardware Reset Pin/Sector Protection Unlock (Flash)
No Internal Connection
I
—
VSS
Device Ground (Common)
Power
Power
Power
VCCf
Device Power Supply (Flash)
VCCs
Device Power Supply (SRAM)
3
MB84VA2104-10/MB84VA2105-10
■ PRODUCT LINE UP
Flash Memory
SRAM
+0.6 V
Ordering Part No.
MB84VA2104-10/MB84VA2105-10
VCC = 3.0 V
–0.3 V
Max. Address Access Time (ns)
Max. CE Access Time (ns)
Max. OE Access Time (ns)
100
100
40
100
100
50
■ BUS OPERATIONS
Table 2 User Bus Operations
Operation (1), (3)
Full Standby
CEf
H
CE1s
H
CE2s
OE
WE
X
DQ0 to DQ7
RESET
X
L
X
HIGH-Z
HIGH-Z
DOUT
H
H
H
X
Output Disable
X
X
X
X
L
H
H
H
Read from Flash (2)
L
L
H
X
H
X
L
Write to Flash
L
H
L
DIN
H
X
Read from SRAM
Write to SRAM
H
H
L
H
H
X
L
L
H
L
DOUT
DIN
H
H
L
X
H
Flash Hardware Reset
X
X
X
HIGH-Z
L
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
Notes: 1. Other operations except for indicated this column are inhibited.
2. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
3. Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
4
MB84VA2104-10/MB84VA2105-10
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• One 16 K byte, two 8 K bytes, one 32 K byte, and thirty one 64 K bytes.
Individual-sector, multiple-sector, or bulk-erase capability.
.
Sector Size
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
32 Kbytes
8 Kbytes
Address Range
00000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
100000H to 10FFFFH
110000H to 11FFFFH
120000H to 12FFFFH
130000H to 13FFFFH
140000H to 14FFFFH
150000H to 15FFFFH
160000H to 16FFFFH
170000H to 17FFFFH
180000H to 18FFFFH
190000H to 19FFFFH
1A0000H to 1AFFFFH
1B0000H to 1BFFFFH
1C0000H to 1CFFFFH
1D0000H to 1DFFFFH
1E0000H to 1EFFFFH
1F0000H to 1F7FFFH
1F8000H to 1F9FFFH
1FA000H to 1FBFFFH
1FC000H to 1FFFFFH
Sector Size
16 Kbytes
8 Kbytes
Address Range
00000H to 03FFFH
04000H to 05FFFH
06000H to 07FFFH
08000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
100000H to 10FFFFH
110000H to 11FFFFH
120000H to 12FFFFH
130000H to 13FFFFH
140000H to 14FFFFH
150000H to 15FFFFH
160000H to 16FFFFH
170000H to 17FFFFH
180000H to 18FFFFH
190000H to 19FFFFH
1A0000H to 1AFFFFH
1B0000H to 1BFFFFH
1C0000H to 1CFFFFH
1D0000H to 1DFFFFH
1E0000H to 1EFFFFH
1F0000H to 1FFFFFH
8 Kbytes
32 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
64 Kbytes
8 Kbytes
16 Kbytes
MB84VA2104 Sector Architecture
MB84VA2105 Sector Architecture
5
MB84VA2104-10/MB84VA2105-10
Table 3 Sector Address Tables (MB84VA2104)
Sector
A20
A19
A18
A17
A16
A15
A14
A13
Address Range
Address
SA0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
00000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
100000H to 10FFFFH
110000H to 11FFFFH
120000H to 12FFFFH
130000H to 13FFFFH
140000H to 14FFFFH
150000H to 15FFFFH
160000H to 16FFFFH
170000H to 17FFFFH
180000H to 18FFFFH
190000H to 19FFFFH
1A0000H to 1AFFFFH
1B0000H to 1BFFFFH
1C0000H to 1CFFFFH
1D0000H to 1DFFFFH
1E0000H to 1EFFFFH
1F0000H to 1F7FFFH
1F8000H to 1F9FFFH
1FA000H to 1FBFFFH
1FC000H to 1FFFFFH
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
1
1
0
1
1
1
X
6
MB84VA2104-10/MB84VA2105-10
Table 4 Sector Address Tables (MB84VA2105)
Sector
Address
A20
A19
A18
A17
A16
A15
A14
A13
Address Range
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
00000H to 03FFFH
04000H to 05FFFH
06000H to 07FFFH
08000H to 0FFFFH
10000H to 1FFFFH
20000H to 2FFFFH
30000H to 3FFFFH
40000H to 4FFFFH
50000H to 5FFFFH
60000H to 6FFFFH
70000H to 7FFFFH
80000H to 8FFFFH
90000H to 9FFFFH
A0000H to AFFFFH
B0000H to BFFFFH
C0000H to CFFFFH
D0000H to DFFFFH
E0000H to EFFFFH
F0000H to FFFFFH
100000H to 10FFFFH
110000H to 11FFFFH
120000H to 12FFFFH
130000H to 13FFFFH
140000H to 14FFFFH
150000H to 15FFFFH
160000H to 16FFFFH
170000H to 17FFFFH
180000H to 18FFFFH
190000H to 19FFFFH
1A0000H to 1AFFFFH
1B0000H to 1BFFFFH
1C0000H to 1CFFFFH
1D0000H to 1DFFFFH
1E0000H to 1EFFFFH
1F0000H to 1FFFFFH
SA2
0
1
1
SA3
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
7
MB84VA2104-10/MB84VA2105-10
Table 5. 1 Flash Memory Autoselect Code
Type
A12
VIL
VIL
VIL
A6
VIL
VIL
VIL
A1
VIL
VIL
VIL
A0
VIL
VIH
VIH
Code (HEX)
04H
Manufacturer’s Code
MB84VA2104
MB84VA2105
C4H
Device Code
49H
Table 5. 2 Expanded Autoselect Code Table
Type
Manufacturer’s Code
MB84VA2104
MB84VA2105
Code
04H
DQ7
0
DQ6
0
DQ5
0
DQ4
0
DQ3
0
DQ2
1
DQ1
0
DQ0
0
C4H
49H
1
1
0
0
0
1
0
0
Device Code
0
1
0
0
1
0
0
1
8
MB84VA2104-10/MB84VA2105-10
Table 6 Flash Memory Command Definitions
Fourth Bus
First Bus
Second Bus Third Bus
Fifth Bus
Sixth Bus
Bus
Read/Write
Cycle
Write Cycle Write Cycle Write Cycle
Write Cycle Write Cycle
Command
Write
Sequence Cycles
Req’d
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset
Read/Reset
Autoselect
Program
1
3
3
4
6
6
XXXH F0H
—
—
—
—
—
RA
—
—
RD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
555H AAH 2AAH 55H 555H F0H
555H AAH 2AAH 55H 555H 90H
555H AAH 2AAH 55H 555H A0H
PA
PD
Chip Erase
Sector Erase
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
SA
30H
Sector Erase Suspend Erase can be suspended during sector erase with Addr (“H” or “L”). Data (B0H)
Sector Erase Resume Erase can be resumed after suspend with Addr (“H” or “L”). Data (30H)
Set to
3
555H AAH 2AAH 55H 555H 20H
—
—
—
—
—
—
—
Fast Mode
Fast Program
(Note)
2
XXXH A0H
PA
PD
—
—
—
—
—
—
—
—
—
Reset from
Fast Mode
(Note)
2
4
XXXH 90H XXXH F0H
—
—
—
—
—
—
—
—
—
—
Extended
Sector
XXXH 60H SPA 60H SPA 40H SPA
SD
Protect
Address bits A11 to A20 = X = “H” or “L” for all address commands except for Program Address (PA) and Sector
Address (SA).
Bus operations are defined in Table 2.
Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
RA =Address of the memory location to be read.
PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of
the write pulse.
SA =Address of the sector to be erased. The combination of A20, A19, A18, A17, A16, A15, A14, and A13 will
uniquely select any sector.
RD =Data read from location RA during read operation.
PD =Data to be programmed at location PA.
SPA =Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0).
SD =Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected
sector addresses.
Note:This command is valid while Fast Mode.
9
MB84VA2104-10/MB84VA2105-10
■ ABSOLUTE MAXIMUM RATINGS
Storage Temperature ..................................................................................................–55°C to +125°C
Ambient Temperature with Power Applied ..................................................................–25°C to +85°C
Voltage with Respect to Ground All pins (Note)..........................................................–0.3 V to VCCf +0.5 V
–0.3 V to VCCs +0.5 V
VCCf/VCCs Supply (Note) ..............................................................................................–0.3 V to +4.6 V
Note: Minimum DC voltage on input or I/O pins are –0.5 V. During voltage transitions, inputs may negativeovershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCCf +0.5 V or VCCs
+0.5 V. During voltage transitions, outputs may positive overshoot to VCC +2.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum rating conditions. Do not exceed these ratings.
■ RECOMMENDED OPERATING RANGES
Commercial Devices
Ambient Temperature (TA) .........................................................................–20°C to +85°C
VCCf/VCCs Supply Voltages.........................................................................+2.7 V to +3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
10
MB84VA2104-10/MB84VA2105-10
■ DC CHARACTERISTICS
Parameter
Parameter Description
Test Conditions
Min.
Typ.
Max. Unit
Symbol
ILI
Input Leakage Current
Output Leakage Current
—
—
–1.0
–1.0
—
—
—
—
—
+1.0
+1.0
30
µA
µA
ILO
tCYCLE = 10 MHz
Flash VCC Active Current VCCf = VCC Max., CEf = VIL
(Read)
ICC1f
ICC2f
ICC1s
mA
mA
OE = VIH
tCYCLE = 5 MHz
—
15
Flash VCC Active Current
(Program/Erase)
VCCf = VCC Max., CEf = VIL, OE = VIH
—
—
35
ttCYCLE =10 MHz
—
—
—
—
—
—
—
—
40
12
35
8
mA
mA
mA
mA
SRAM VCC Active
Current
VCCs = VCC Max.,
CE1s = VIL, CE2s = VIH
tCYCLE = 1 MHz
tCYCLE = 10 MHz
tCYCLE = 1 MHz
CE1s = 0.2 V,
SRAM VCC Active
Current
ICC2s
CE2s = VCCs – 0.2 V,
WE = VCCs – 0.2 V
Flash VCC Standby
Current
VCCf = VCC Max., CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V
ISB1f
ISB2f
ISB1s
—
—
—
—
5
5
µA
µA
Flash VCC Standby
Current (RESET)
VCCf = VCC Max., RESET = VSS ± 0.3 V
CE1s = VIH or CE2s = VIL
SRAM VCC Standby
Current
—
—
—
—
—
—
—
—
1
2
2
mA
µA
µA
µA
µA
µA
µA
TA = 25°C
VCCs =
3.0 V
±10%
TA = –20 to
+85°C
—
2
35
3
TA = 25°C
VCCs =
3.3 V
±0.3 V
CE1s = VCC –
0.2 V or CE2s
= 0.2 V
TA = –20 to
+85°C
SRAM VCC Standby
Current
—
—
—
40
1
ISB2s**
TA = 25°C
TA = –20 to
+40°C
VCCs =
3.0 V
3
TA = –20 to
+85°C
30
—
—
µA
VIL
VIH
Input Low Level
Input High Level
—
—
–0.3
2.2
—
—
0.6
V
V
VCC+0.3*
Output Low Voltage
Level
IOL = 2.1 mA,
VOL
VOH
VLKO
—
VCC – 0.5
2.3
—
—
—
0.4
—
V
V
V
VCCf = VCCs = VCC Min.
Output High Voltage
Level
IOH = –500 µA,
VCCf = VCCs = VCC Min.
Flash Low VCC Lock-Out
Voltage
—
2.5
* : VCC indicate lower of VCCf or VCCs
** :During standby mode with CE1s = VCCS – 0.2 V, CE2s should be CE2s < 0.2V or CE2s > VCCS – 0.2V
11
MB84VA2104-10/MB84VA2105-10
■ AC CHARACTERISTICS
• CE Timing
Parameter
Symbols
Description
Test Setup
-10
Unit
JEDEC Standard
—
tCCR
CE Recover Time
—
Min.
0
ns
• Timing Diagram for alternating SRAM to Flash
CEf
tCCR
tCCR
CE1s
CE2s
tCCR
tCCR
12
MB84VA2104-10/MB84VA2105-10
• Read Only Operations Characteristics (Flash)
Parameter
Symbols
-10
(Note)
Test
Setup
Description
Unit
JEDEC Standard
Min.
Max.
tAVAV
tAVQV
tRC
Read Cycle Time
—
100
—
—
ns
ns
CEf = VIL
OE = VIL
tACC
Address to Output Delay
100
tELQV
tGLQV
tEHQZ
tGHQZ
tCEf
tOE
tDF
tDF
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High-Z
Output Enable to Output High-Z
OE = VIL
—
—
—
—
100
40
ns
ns
ns
ns
—
—
—
30
30
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
—
tOH
—
—
0
—
ns
µs
tREADY
RESET Pin Low to Read Mode
—
20
Note: Test Conditions–Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to 3.0 V
Timing measurement reference level
Input: 1.5 V
Output: 1.5 V
13
MB84VA2104-10/MB84VA2105-10
• Read Cycle (Flash)
tRC
Addresses Stable
ADDRESSES
tACC
CEf
tOE
tDF
OE
tOEH
WE
tCE
HIGH-Z
HIGH-Z
DQ
Output Valid
tRC
ADDRESSES
Addresses Stable
tACC
tRH
RESET
tOH
HIGH-Z
DQ
Output Valid
14
MB84VA2104-10/MB84VA2105-10
• Erase/Program Operations (Flash)
Parameter Symbols
-10
Description
Unit
JEDEC
tAVAV
tAVWL
tAVEL
Standard
Min.
100
0
Typ.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
100
90
tWC
tAS
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
sec
µs
µs
ns
ns
ns
ns
ns
ns
Address Setup Time (WE to Addr.)
Address Setup Time (CEf to Addr.)
Address Hold Time (WE to Addr.)
Address Hold Time (CEf to Addr.)
Data Setup Time
tAS
0
tWLAX
tELAX
tAH
tAH
tDS
tDH
tOES
50
50
50
0
tDVWH
tWHDX
—
Data Hold Time
Output Enable Setup Time
0
Read
0
Output Enable
Hold Time
—
tOEH
Toggle and Data Polling
10
0
tGHEL
tGHWL
tWLEL
tELWL
tEHWH
tWHEH
tWLWH
tELEH
tGHEL
tGHWL
tWS
Read Recover Time Before Write (OE to CEf)
Read Recover Time Before Write (OE to WE)
WE Setup Time (CEf to WE)
CEf Setup Time (WE to CEf)
WE Hold Time (CEf to WE)
CEf Hold Time (WE to CEf)
Write Pulse Width
0
0
tCS
0
tWH
0
tCH
0
tWP
50
50
30
30
—
—
—
50
4
tCP
CEf Pulse Width
tWHWL
tEHEL
tWPH
tCPH
tWHWH1
Write Pulse Width High
CEf Pulse Width High
tWHWH1
Byte Programming Operation
1
tWHWH2
tWHWH2
Sector Erase Operation (Note 1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
tVCS
tVLHT
tVIDR
tRB
VCCf Setup Time
Voltage Transition Time (Note 2)
Rise Time to VID (Note 2)
500
0
Recover Time from RY/BY
tRP
RESET Pulse Width
500
200
—
—
tRH
RESET Hold Time Before Read
Delay Time from Embedded Output Enable
Program/Erase Valid to RY/BY Delay
tEOE
tBUSY
Note : 1. This does not include the preprogramming time.
2. This timing is for Sector Protection Operation.
15
MB84VA2104-10/MB84VA2105-10
• Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
555H
tWC
PA
PA
ADDRESSES
tRC
tAS
tAH
CEf
tCH
tCS
tCO
OE
tGHWL
tFOE
tWHWH1
tWP
tWPH
WE
tOH
tDS
tDH
PD
DOUT
DOUT
A0H
DQ7
DQ
16
MB84VA2104-10/MB84VA2105-10
• Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling
PA
ADDRESSES
PA
555H
tWC
tAH
tAS
WE
tWS
tWH
OE
tGHEL
tWHWH1
tCP
tCPH
CEf
DQ
tDS
tDH
PD
DOUT
DQ7
A0H
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
17
MB84VA2104-10/MB84VA2105-10
• AC Waveforms Chip/Sector Erase Operations (Flash)
SA*1
2AAH
555H
tWC
2AAH
tAS
555H
555H
ADDRESSES
tAH
CEf
tCS
tCH
OE
tWP
tWPH
tGHWL
WE
tDS
tDH
30H for Sector Erase
10H/
30H
AAH
AAH
55H
80H
55H
DQ
VCC
tVCS
Note: 1. SA is the sector address for Sector Erase. Addresses = 555H for Chip Erase.
18
MB84VA2104-10/MB84VA2105-10
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tOD
tFOE
OE
tOEH
WE
tCO
*
High-Z
High-Z
DQ7 =
Valid Data
Data In
Data In
DQ7
DQ7
tWHWH1 or 2
DQ
(DQ0 to DQ6)
DQ0 to DQ6
Valid Data
DQ0 to DQ6 = Invalid
tEOE
*DQ7 = Valid Data (The device has completed the Embedded operation.)
• AC Waveforms for Taggle Bit during Embedded Algorithm Operations (Flash)
CEf
tOEH
WE
tOES
OE
*
DQ6 =
Stop Toggling
DQ0 to DQ7
Data Valid
DQ6 =
Toggle
DQ6 = Toggle
Data In
DQ6
tEOE
*DQ6 = Stops toggling. (The device has completed the Embedded operation.)
19
MB84VA2104-10/MB84VA2105-10
• RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
• RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP
tRB
RY/BY
tREADY
• Temporary Sector Unprotection (Flash)
VCC
t
VIDR
t
VCS
t
VLHT
V
ID
3 V
3 V
RESET
CE
WE
t
VLHT
t
VLHT
Program or Erase Command Sequence
Unprotection period
RY/BY
20
MB84VA2104-10/MB84VA2105-10
• Extended Sector Protection (Flash)
VCC
tVCS
RESET
Add
tVLHT
tVIDR
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE
TIME-OUT
WE
Data
60H
60H
40H
01H
60H
tOE
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 150 µs (min)
21
MB84VA2104-10/MB84VA2105-10
• Read Cycle (SRAM)
Parameter
Parameter Description
Symbol
Min.
Max.
Unit
tRC
tAA
Read Cycle Time
100
—
—
—
—
5
—
100
100
100
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tCO1
tCO2
tOE
Chip Enable (CE1s) Access Time
Chip Enable (CE2s) Access Time
Output Enable Access Time
tCOE
tOEE
tOD
Chip Enable (CE1s Low and CE2s High) to Output Active
Output Enable Low to Output Active
Chip Enable (CE1s High or CE2s Low) to Output High-Z
Output Enable High to Output High-Z
Output Data Hold Time
—
0
—
—
—
10
40
tODO
tOH
40
—
• Read Cycle (Note 1) (SRAM)
tRC
ADDRESSES
CE1s
tAA
tOH
tCO1
tCOE
tOD
tCO2
CE2s
tOD
tOE
OE
DQ
tODO
tOEE
tCOE
VALID DATA OUT
Note: 1. WE remains HIGH for the read cycle.
22
MB84VA2104-10/MB84VA2105-10
•
Write Cycle (SRAM)
Parameter
Symbol
Parameter Description
Write Cycle Time
Min.
Max.
Unit
tWC
tWP
tCW
tAS
100
60
80
0
—
—
—
—
—
40
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable to End of Write
Address Setup Time
Write Recovery Time
WE Low to Output High-Z
WE High to Output Active
Data Setup Time
tWR
tODW
tOEW
tDS
0
—
0
60
0
tDH
Data Hold Time
• Write Cycle (Note 4) (WE control) (SRAM)
tWC
ADDRESSES
tAS
tWP
tWR
WE
CE1s
CE2s
tCW
tCW
tODW
tOEW
DOUT
Note 2
Note 5
Note 3
tDS
tDH
DIN
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the
output will remain at high impedance.
3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the
output will remain at high impedance.
4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
23
MB84VA2104-10/MB84VA2105-10
• Write Cycle (Note 4) (CE1s control) (SRAM)
tWC
ADDRESSES
tAS
tWP
tWR
WE
tCW
CE1s
CE2s
tCW
tCOE
tODW
DOUT
tDS
tDH
DIN
Note 5
Note 5
VALID DATA IN
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the
output will remain at high impedance.
3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the
output will remain at high impedance.
4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
24
MB84VA2104-10/MB84VA2105-10
• Write Cycle (Note 4) (CE2s Control) (SRAM)
tWC
ADDRESSES
tAS
tWP
tWR
WE
tCW
CE1s
CE2s
tCW
tODW
tCOE
DOUT
tDS
tDH
DIN
Note 5
VALID DATA IN
Note 5
Notes: 2. If CE1s goes LOW (or CE2s goes HIGH) coincident with or after WE goes LOW, the
output will remain at high impedance.
3. If CE1s goes HIGH (or CE2s goes LOW) coincident with or before WE goes HIGH, the
output will remain at high impedance.
4. If OE is HIGH during the write cycle, the outputs will remain at high impedance.
5. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
25
MB84VA2104-10/MB84VA2105-10
■ ERASE AND PROGRAMMING PERFORMANCE (Flash)
Limits
Parameter
Unit
Comment
Min.
Typ.
Max.
Excludes programming time
prior to erasure
Sector Erase Time
—
1
15
sec
Excludes system-level
overhead
Byte Programming Time
—
8
3,600
µs
Excludes system-level
overhead
Chip Programming Time
Erase/Program Cycle
—
16.8
—
100
—
sec
100,000
cycles
■ DATA RETENTION CHARACTERISTICS (SRAM)
Parameter
Parameter Description
Symbol
Min.
Typ.
Max.
Unit
VDH
Data Retention Supply Voltage
2.0
—
—
0
—
—
—
—
—
3.6
30*
40
—
V
VDH = 3.0 V
VDH = 3.6 V
µA
µA
ns
IDDS2
Standby Current
tCDR
tR
Chip Deselect to Data Retention Mode Time
Recovery Time
5
—
ms
* : 5 µA (Max.) at TA = –20°C to +40°C
• CE1s Controlled Data Retention Mode (Note 1)
VCCs
DATA RETENTION MODE
2.7 V
See Note 2
See Note 2
VIH
VCCS –0.2 V
CE1s
tCDR
tR
GND
26
MB84VA2104-10/MB84VA2105-10
• CE2s Controlled Data Retention Mode (Note 3)
VCCs
DATA RETENTION MODE
2.7 V
VIH
CE2s
tCDR
tR
VIL
0.2 V
GND
Notes:
1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2V or Vss
to 0.2V during data retention mode. Other input and input/output pins can be used between -0.3V to
Vccs+0.3V.
2.When CE1s is operating at the VIH min. level (2.2 V), the standby current is given by ISB1s during the
transition of VCCs from 3.6 to 2.2 V.
3. In CE2s controlled data retention mode, input and input/output pins can be used between between
-0.3V to Vccs+0.3V.
■ PIN CAPACITANCE
Parameter
Parameter Description
Test Setup
VIN = 0
Typ.
Max.
Unit
Symbol
CIN
Input Capacitance
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
T.B.D
pF
pF
pF
COUT
Output Capacitance
Control Pin Capacitance
VOUT = 0
VIN = 0
CIN2
Note: Test conditions TA = 25°C, f = 1.0 MHz
■ HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
■ CAUTION
1. )The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not
use autoselect and sector protect function by applying the high voltage (VID) to specific pins.
2. )For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected the
sector useing "Extended sector protect" command.
27
MB84VA2104-10/MB84VA2105-10
■ PACKAGE
48-pin plastic FBGA
(BGA-48P-M10)
■ PACKAGE DIMENSIONS
48-pin plastic BGA
(BGA-48P-M10)
Note: The actual shape of coners may differ from the dimension.
14.00±0.15(.551±.006)
1.40±0.20
7.00±0.15(.276±.006)
(.055±.008)
0.30±0.10
(.012±.004)
10.00±0.15
(.394±.006)
5.00±0.15
(.197±.006)
1st PIN
INDEX
INDEX
Ø0.40±0.10
(Ø.016±.004)
1.00±0.15
(.039±.006)
0.15(.006)
Dimension in mm (inches).
C
1998 FUJITSU LIMITED MCM-M002-3-2
28
MB84VA2104-10/MB84VA2105-10
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: (044) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
Fax: (408) 922-9179
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9805
FUJITSU LIMITED Printed in Japan
29
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