MB85RC64 [FUJITSU]
Memory FRAM 64 K (8 K x 8) Bit I2C; FRAM内存64 K（为8K ×8 ）位I2C
| 型号： | MB85RC64 |
| 厂家： | 
FUJITSU |
| 描述： | Memory FRAM 64 K (8 K x 8) Bit I2C |
| 文件： | 总20页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05–13109–3E
Memory FRAM
64 K (8 K × 8) Bit I2C
MB85RC64
■ DESCRIPTION
The MB85RC64 is a FRAM (Ferroelectric Random Access Memory) Stand-Alone chip in a configuration of
8,192 words × 8 bits, using the ferroelectric process and silicon gate CMOS process technologies for forming
the nonvolatile memory cells.
The MB85RC64 adopts the two-wire serial interface.
Unlike SRAM, the MB85RC64 is able to retain data without using a data backup battery.
The read/write endurance of the nonvolatile memory cells used for the MB85RC64 has improved to be at
least 1010 cycles, significantly out performing Flash memory and E2PROM in the number.
The MB85RC64 does not need a polling sequence after writing to the memory such as the case of Flash
memory nor E2PROM.
■ FEATURES
• Bit configuration
: 8,192 words × 8 bits
• Operating power supply voltage : 2.7 V to 3.6 V
• Operating frequency
• Two-wire serial interface
: 400 kHz (Max)
: I2C-bus specification ver. 2.1 compliant, supports Standard-mode/
Fast-mode.
Fully controllable by two ports: serial clock (SCL) and serial data (SDA).
• Operating temperature range : − 40 °C to +85 °C
• Data retention
• Read/write endurance
• Package
: 10 years ( + 75 °C)
: 1010 times
: Plastic / SOP, 8-pin (FPT-8P-M02)
• Low power consumption
: Operating current 0.15 mA (Max: @400 kHz), Standby current 5 μA (Typ)
Copyright©2010-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.6
MB85RC64
■ PIN ASSIGNMENT
(TOP VIEW)
A0
A1
1
2
3
4
8
7
6
5
VDD
WP
SCL
SDA
A2
VSS
(FPT-8P-M02)
■ PIN FUNCTIONAL DESCRIPTIONS
Pin
Pin Name
Number
Functional Description
Device Address pins
The MB85RC64 can be connected to the same data bus up to 8 devices.
Device addresses are used in order to identify each of the devices. Connect
these pins to VDD pin or VSS pin externally. Only if the combination of VDD and
VSS pins matches a device, an address and a code inputted from the SDA pin,
the device operates. In the open pin state, A0, A1, and A2 pins are pulled-down
and recognized as “L”.
1 to 3
A0 to A2
4
5
VSS
SDA
Ground pin
Serial Data I/O pin
This is an I/O pin of serial data for performing bidirectional communication of
address and writing or reading data of FRAM memory cell array. It is an open
drain output that may be wired OR with other open drain or open collector sig-
nals on the bus, so a pull-up resistance is required to be connected to the ex-
ternal circuit.
Serial Clock pin
6
SCL
This is a clock input pin for input/output timing serial data. Data is sampled on
the rising edge of the clock and output on the falling edge.
Write Protect pin
When the Write Protect pin is “H”, the writing operation is disabled. When the
Write Protect pin is “L”, the entire memory region can be overwritten. The read-
ing operation is always enabled regardless of the Write Protect pin condition. In
the open pin state, the Write Protect pin is pulled-down and recognized as “L”.
7
8
WP
VDD
Supply Voltage pin
2
DS05–13109–3E
MB85RC64
■ BLOCK DIAGRAM
Serial/Parallel Converter
SDA
FRAM Array
8,192 × 8
SCL
WP
Column Decoder/Sense Amp/
Write Amp
A0, A1, A2
■ I2C (Inter-Integrated Circuit)
The MB85RC64 has the two-wire serial interface; the I2C bus,and operates as a slave device.
The I2C bus defines communication roles of “master” and “slave” devices, with the master side holding the
authority to initiate control. Furthermore, a I2C bus connection is possible where a single master device is
connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a
unique device address to the slave device.
• I2C Interface System Configuration Example
VDD
Pull-up
Resistors
SCL
SDA
I2C Bus
MB85RC64
I2C Bus
MB85RC64
I2C Bus
MB85RC64
I2C Bus
Master
...
A2 A1 A0
A2 A1 A0
A2 A1 A0
0
0
0
0
0
1
0
1
0
Device address
DS05–13109–3E
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MB85RC64
■ I2C COMMUNICATION PROTOCOL
The I2C bus is a two wire serial interface that uses a bidirectional data bus (SDA) and serial clock (SCL). A
data transfer can only be initiated by the bus master, which will also provide the serial clock for synchroni-
zation. The SDA signal should change while SCL is Low. However, as an exception, when starting and
stopping communication sequence, SDA is allowed to change while SCL is High.
• Start Condition
To start read or write operations by the I2C bus, set the SDA input from High to Low while the SCL input is
in High in order to start reading and writing.
• Stop Condition
Set the SDA input from Low to High while the SCL input is in High in order to terminate the I2C bus commu-
nication. Because the MB85RC64 does not need the writing wait time unlike E2PROM, it goes to the standby
state immediately after the stop condition input.
• Start Condition, Stop Condition
SCL
SDA
Start
Stop
Note : The FRAM device does not need the programming wait time like tWC after issuing the Stop Condition
such as.
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MB85RC64
■ ACKNOWLEDGE (ACK)
In the I2C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge
signal indicates that every each 8 bits of the data is successfully sent and received. The information receiver
side usually outputs “L” every time on the 9th SCL clock after each 8 bits are successfully transmitted. On
the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow the acknowl-
edge signal to be received and checked. During this Hi-Z-released period, the receiver side pulls the SDA
line down to indicate “L” that the previous 8bits communication is successfully received.
If the information receiver side detects Stop condition before driving the acknowledge “L”, the read operation
ends and the I2C bus enters the standby state. If Stop condition is not sent, nor does the transmitter detect
the acknowledge “L”, the bus remains in the released state “H” without doing anything.
• Acknowledge timing overview diagram
1
2
3
8
9
SCL
SDA
ACK
The transmitter side should always release SDA on the
9th bit. At this time, the receiver side outputs a pull-down
to indicate a successful byte transfer (ACK response).
Start
DS05–13109–3E
5
MB85RC64
■ DEVICE ADDRESS WORD (Slave address)
Following the start condition, the bus master sends the 8bits device address word (Slave address) to start
I2C communication. The device address word (8bits) consists of a device Type code (4bits), device address
code (3bits), and a read/write code (1bit).
• Device Type Code (4bits)
The upper 4 bits of the device address word are a device type code that identifies the device type, and are
fixed at “1010” for the MB85RC64.
• Device Address Code (3bits)
Following the device type code, the 3 bits of the device address code are input in order of A2, A1, and A0.
Each MB85RC64 is given a unique 3bits code on the device address pin (external hardware pin A2, A1, and
A0). When the device address code is received by the slave device, the slave only responds if the hardware
device address of which is equal to its unique 3bits code.
• Read/Write Code (1bit)
The 8th bit of the device address word is the R/W (read/write) code. When the R/W code is “0”, a write
operation is enabled, and the R/W code is “1”, a read operation is enabled for the MB85RC64.
It turns to a stand-by state if the device code is not “1010” or device address code does not equal to pins
A2, A1, and A0.
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DS05–13109–3E
MB85RC64
■ DATA STRUCTURE
In the I2C bus, the acknowledge “L” is output on the 9th bit after the 8 bits of the device and address word
following the start condition. After confirming the acknowledge response at the slave, the I2C master outputs
8bits × 2 memory address to the I2C slave. When the memory address input ends, the slave again outputs
the acknowledge “L”. After this operation, the I/O data follows in units of 8 bits, with the acknowledge “L”
output after every 8bits.
It is determined by the R/W code whether the data line is driven by the master or the slave. For a write
operation the slave will accept 8bits from the master then send an acknowledge. If the master detects the
acknowledge, the master will transfer the next 8bits. For a read operation the slave will place 8bits on the
I2C bus, then wait for an acknowledge from the master.
• Data Structure Diagram
2
Start
1
2
3
4
5
6
7
8
9
1
..
..
SCL
SDA
ACK
A
1
0
1
0
R/W
S
A2 A1 A0
Access from master
Access from slave
S
A
Start Condition
ACK
■ FRAM ACKNOWLEDGE -- POLLING NOT REQUIRED
The MB85RC64 performs write operations at the same speed as read operations, so any waiting time for
an ACK polling* does not occur. The write cycle takes no additional time.
*: As to E2PROM, the Acknowledge Polling is performed as a progress check in the write programming step.
It places NAK condition on the bus as of “not acknowledged” during the writing programming period. The
busy status for the write programming is given from 9th ACK bit. That “done” condition is placed onto I2C
bus by E2PROM I2C device and your program had to poll the bus in order to sense that condition.
■ WRITE PROTECT (WP)
The entire memory array can be write protected using the Write Protect pin. When the Write Protect pin is
set to “H”, the entire memory map will be write protected. When the Write Protect pin is “L”, all addresses
may be overwritten. Reading is allowed regardless of the WP pin's High/Low.
Note : The Write Protect pin is pulled down internally to VSS pin, therefore if the Write Protect pin is open, the
pin status is detected as Low (write enabled).
DS05–13109–3E
7
MB85RC64
■ COMMAND
• Byte Write
If the 8th bit of the device address word (R/W = 0) is sent following the start condition, the slave responds
with an ACK. After this ACK, write addresses and data are sent in the same way, and the write ends by
master, generating a stop condition at the end.
Address
High 8bits
Address
Low 8bits
Write
Data 8bits
1
0 1 0 A2 A1 A0 0 A
A
A
A P
S
0 0 0 X X X X X
X X X X X X X X
Access from master
Access from slave
MSB
LSB
S
P
Start Condition
Stop Condition
A ACK
Note : In the MB85RC64, input “000” as the upper 3 bits of the MSB.
• Page Write
If additional 8bits are sent after the same command as Byte Write, a page write is performed. If more bytes
are sent than will fit up to the end of the address, the address rolls over to 0000H. Therefore, if more than
8KBytes are sent, the data is overwritten in order starting from the start of the FRAM memory address that
was written first. Because FRAM performs write operations at bus speed, the data will be written to FRAM
after the ACK response finishes immediately.
Address
High 8bits
Address
Low 8bits
Write
Data 8bits
Write
Data
...
1
0 1 0 A2 A1 A0 0 A
A
A
A
A
P
S
Access from master
Access from slave
S
P
Start Condition
Stop Condition
A ACK
Note : It is not necessary to take a period for internal write operation cycles from the buffer to the memory after
the stop condition is generated.
8
DS05–13109–3E
MB85RC64
• Current Address Read
When the previous write or read operation finishes successfully up to the stop command and if the last
accessed address is taken to be “n”, then the address at “n+1” is read by sending the following command
unless turning the power off. If the end of the address range is reached internally, the address counter will
roll over to 0000H. The current address is undefined immediately after the power is turned on.
Access from master
Access from slave
S
P
Start Condition
Stop Condition
(n+1) address
Read
Data 8bits
1
0 1 0 A2 A1 A0 1 A
N P
S
A ACK
NACK
N
• Random Read
The one byte of data at the address as saved in the buffer can be read out synchronously to SCL by specifying
the address in the same way as for a write, and then issuing another start condition and sending the Control
Byte (R/W = 1).
The final NACK is issued by the receiver that receives the data. In this case, this bit is issued by the master
side.
n address
Address
High 8bits
Address
Low 8bits
Read
Data 8bits
1
0
1
0 A2 A1 A0 0
A
A
A
1
0
1
0 A2 A1 A0 1
A
N P
S
S
Access from master
Access from slave
S
P
Start Condition
Stop Condition
A ACK
NACK
N
DS05–13109–3E
9
MB85RC64
• Sequential Read
Data can be received continuously following the control byte after specifying the address the same as for
Random Read. If the read reaches the end of address for the MB85RC64, the internal read address auto-
matically rolls over to 0000H.
Read
Data
Read
Data 8bits
Read
Data 8bits
...
...
A
A
A
N P
Access from master
Access from slave
Stop Condition
P
A ACK
NACK
N
10
DS05–13109–3E
MB85RC64
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Max
Min
Power supply voltage*
Input pin voltage*
VCC
VIN
− 0.5
− 0.5
− 0.5
− 40
− 40
+4.0
V
VCC + 0.5 ( ≤ 4.0)
VCC + 0.5 ( ≤ 4.0)
+ 85
V
Output pin voltage*
Ambient temperature
Storage temperature
VOUT
TA
V
°C
°C
Tstg
+ 125
*: These parameters are based on the condition that VSS is 0 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
Typ
Max
Power supply voltage*
“H” level input voltage*
VCC
VIH
2.7
3.3
3.6
V
V
VCC + 0.5
( ≤ 4.0)
VCC × 0.8
⎯
“L” level input voltage*
Ambient temperature
VIL
− 0.5
− 40
⎯
⎯
+ 0.6
+ 85
V
TA
°C
*: These parameters are based on the condition that VSS is 0 V.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
onthedatasheet.Usersconsideringapplicationoutsidethelistedconditionsareadvisedtocontact
their representatives beforehand.
DS05–13109–3E
11
MB85RC64
■ ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(within recommended operating conditions)
Value
Parameter
Symbol
Condition
Unit
Min
Typ
Max
SCL, SDA = 0 V to VCC
A0, A1, A2, WP = 0 V or VCC
Input leakage current
|ILI|
⎯
⎯
1
μA
Output leakage current
|ILO|
VOUT = 0 V to VCC
⎯
⎯
⎯
1
μA
μA
Operating power supply current
ICC
SCL = 400 kHz
100
150
SCL, SDA = VCC
Standby current
ISB
⎯
⎯
5
20
μA
A0, A1, A2, WP = 0 V or VCC
“L” level output voltage
VOL
IOL = 2 mA
⎯
0.4
V
2. AC Characteristics
Parameter
Value
Symbol
Unit
Min
0
Max
400
⎯
SCL clock frequency
Clock high time
FSCL
THIGH
TLOW
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
600
1300
⎯
Clock low time
⎯
SCL/SDA rise time
SCL/SDA fall time
Start condition hold
Start condition setup
SDA input hold
Tr
300
300
⎯
Tf
⎯
THD:STA
TSU:STA
THD:DAT
TSU:DAT
TDH:DAT
TSU:STO
TAA
600
600
0
⎯
⎯
SDA input setup
100
0
⎯
SDA output hold
⎯
Stop condition setup
SDA output access after SCL fall
Pre-charge time
600
⎯
⎯
900
⎯
TBUF
1300
Pulse width ignored
(Input Filter on SCL and SDA)
TSP
⎯
50
ns
AC characteristics were measured under the following measurement conditions.
Power supply voltage : 2.7 V to 3.6 V
Operating temperature : − 40 °C to + 85 °C
Input voltage magnitude : 0.3 V to 2.7 V
Input rise time
Input fall time
: 5 ns
: 5 ns
: VCC/2
: VCC/2
Input judge level
Output judge level
12
DS05–13109–3E
MB85RC64
3. AC Timing Definitions
TSU:DAT
THD:DAT
VIH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
SCL
Stop
Start
VIL
VIH
VIH
VIL
VIH
VIL
VIH
VIL
SDA
VIL
TSU:STA THD:STA
TSU:STO
Tr
Tf
THIGH
TLOW
VIH
VIL
VIH
VIL
VIH
VIH
VIL
SCL
SDA
Stop
Start
VIL
VIH
VIH
VIH
VIL
VIH
VIL
VIL
VIL
Tbuf
Tr
Taa
Tf
Tsp
TDH:DAT
VIH
SCL
SDA
VIL
VIL
VIH
VIL
VIH
VIL
Valid
VIL
1/FSCL
4. Pin Capacitance
Parameter
Value
Unit
Symbol
Conditions
Min
Typ
⎯
Min
15
I/O capacitance
CI/O
CIN
⎯
⎯
pF
pF
VIN = VOUT = 0 V,
f = 1 MHz, TA = + 25 °C
Input capacitance
⎯
15
5. AC Test Load Circuit
3.3 V
Output
100 pF
DS05–13109–3E
13
MB85RC64
■ POWER ON SEQUENCE
tr
tpu
tpd
VCC
VCC
2.7 V
2.7 V
VIH (Min)
VIH (Min)
1.0 V
1.0 V
VIL (Max)
VIL (Max)
0 V
0 V
*
*
SDA, SCL >VCC × 0.8
SDA, SCL : Don't care
SDA, SCL >VCC × 0.8
SDA, SCL
SDA, SCL
* : SDA, SCL (Max) < VCC + 0.5 V
Value
Parameter
Symbol
Unit
Min
85
Max
SDA, SCL level hold time during power down
SDA, SCL level hold time during power up
Power supply rise time
tpd
tpu
tr
⎯
⎯
⎯
ns
ns
μs
85
10
■ NOTES ON USE
• Data written before performing IR reflow is not guaranteed.
• VDD pin is required to be rising from 0 V because turning the power on from an intermediate level may
cause malfunctions, when the power is turned on.
During the access period from the start condition to the stop condition, keep the level of WP, A0, A1, and
A2 pins to “H” or “L”.
14
DS05–13109–3E
MB85RC64
■ ORDERING INFORMATION
Part number
Package
Remarks
8-pin, plastic SOP
(FPT-8P-M02)
MB85RC64PNF-G-JNE1
8-pin, plastic SOP
(FPT-8P-M02)
MB85RC64PNF-G-JNERE1
Embossed Carrier tape
DS05–13109–3E
15
MB85RC64
■ PACKAGE DIMENSION
8-pin plastic SOP
Lead pitch
1.27 mm
3.9 mm × 5.05 mm
Gullwing
Package width
package length
×
Lead shape
Sealing method
Mounting height
Weight
Plastic mold
1.75 mm MAX
0.06 g
(FPT-8P-M02)
8-pin plastic SOP
(FPT-8P-M02)
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3) Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
+0.25
1 5.05 –0.20 .199 +–..000180
0.22 +–00..0073
.009 +–..000031
*
8
5
*2 3.90 0.30 6.00 0.40
(.154 .012) (.236 .016)
Details of "A" part
45°
1.55 0.20
(Mounting height)
(.061 .008)
0.25(.010)
0.40(.016)
0~8°
"A"
1
4
1.27(.050)
0.44 0.08
(.017 .003)
M
0.13(.005)
0.50 0.20
(.020 .008)
0.15 0.10
(.006 .004)
(Stand off)
0.60 0.15
(.024 .006)
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
C
2002-2010 FUJITSU SEMICONDUCTOR LIMITED F08004S-c-4-9
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
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MEMO
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MEMO
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MEMO
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MB85RC64
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Specifications are subject to change without notice. For further information please contact each office.
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Customers are advised to consult with sales representatives before ordering.
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of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
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ing in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-
current levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
相关型号：
MB85RC64APNF-G-JNERE1
Memory Circuit, 8KX8, CMOS, PDSO8, 3.90 X 5.05 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, ROHS COMPLIANT, PLASTIC, SOP-8
FUJITSU
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