MB86022-PF [FUJITSU]
PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24, PLASTIC, FP-24;
| 型号： | MB86022-PF |
| 厂家： | 
FUJITSU |
| 描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24, PLASTIC, FP-24 输入元件 光电二极管 |
| 文件： | 总16页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS04–13201–3aE
DATA SHEET
LINEAR IC CMOS
8 BIT 4-CHANNEL D/A CONVERTER
MB86022
CMOS 8-BIT 4-CHANNEL D/A CONVERTER
The Fujitsu MB86022 is a 8-bit 4-channel Digital to Analog Converter which is
fabricatedwith Fujitsu CMOS Technology. The data latch and output buffer circuitry
are provided on each channel which can operate independently selected by 2bit
data.
PLASTIC PACKAGE
DIP-24P-M03
• Resolution
: 8-Bits (4-channels)
: 200k sps
• Conversion Rate
PLASTIC PACKAGE
FPT-24P-M02
• Digital Input Voltage
: TTL Level
• Power Supply Voltage : +5V
PIN ASSIGNMENT
(TOP VIEW)
• Low Power Dissipation : 14mW typ. at +5V
______
D0
D1
D2
D3
D4
D5
D6
D7
C0
1
24
23
22
21
20
19
18
17
16
15
14
13
RESET
___
PD
• Each channel operates independently
2
3
VDD
VR2
VR1
AO0
AO1
AO2
AO3
N.C.
AG
• On-chip Data Initialization & Power Down Function
• Reference voltage mode selection: On-chip or External generation
• Easy to take interface with micro processor (Parallel Data Input)
4
5
6
7
8
9
C1
10
11
12
___
WR
___
CE
DG
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields.
However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit.
TM
Quick Pro
is a trademark of FUJITSU LIMITED
1995 by FUJITSU LIMITED
Copyright
1
MB86022
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Parameter
Symbol
Pin Name
Unit
Min
Typ
–
Max
VDD
VDD
Power supply voltage
Digital input voltage
Analog input voltage
Analog output voltage
Analog output current
Storage temperature
GND–0.3
7
V
V
V
V
VDI
V
V
V
DD+0.3
DD+0.3
DD+0.3
All digital input pins
VR1,VR2
GND–0.3
GND–0.3
GND–0.3
–
V1, V2
VAO
IAO
–
AO0,AO1,AO2,AO3
AO0,AO1,AO2,AO3
–
–10
–40
–
10
mA
°C
Tstg
–
125
NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are
exceeded. Functional operation should be restricted to the conditions as detailed in the
operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
MB86022
BLOCK DIAGRAM
8
8-bit
Data
Latch
D0 to D7
8-bit
DAC
–
+
AO3
AO2
AO1
AO0
Buffer Amp.
8-bit
Data
Latch
8-bit
DAC
–
+
Buffer Amp.
2
8-bit
Data
Latch
C0,C1
8-bit
DAC
Channel
–
+
Select
&
___
WR
Control
Logic
___
CE
Buffer Amp.
8-bit
Data
Latch
8-bit
DAC
–
+
Buffer Amp.
______
RESET
___
PD
VR1
VR2
VREF
Circuit
VDD DG AG
3
MB86022
PIN DESCRIPTION
System Pin Number Symbol
Descriptions
22
13
14
VDD
DG
AG
Power Supply Voltage 5V
GND for Digital System
GND for Analog System
Power
Supply
___
PD
Power down control signal pin. The circuit is set power down when this pin goes to “L”.
This pin is pulled up by high resistance. TTL interface.
23
24
Reset input signal pin. The data at all channels is initialized when this pin goes to “L”.
At this time, the D/A output is set at D(A)=128.
This pin is pulled up by high resistance. TTL interface.
______
RESET
___
CE
Chip enable signal pin. The data can be written when this pin goes to “L”. This pin is
pulled up by high resistance. TTL interface.
12
11
___
WR
Data write pin. The data from D0 to D7 is written when the rising edge (L ³ H) of this pin.
TTL interface.
Channel selection signal pin. Channels are selected by following table. TTL
interface.
9
C0
C1
C1 C0
Channel
L
L
H
H
L
H
L
0
1
2
3
Digital
Input
10
H
1
2
3
4
5
6
7
8
D0
D1
D2
D3
D4
D5
D6
D7
Data input signal pin. The digital data is read by the channel which is selected by C0 and
C1 pins when the rising edge of WR (L ³ H), and analog output is shown correspond to
that digital code. D0 is LSB and D7 is MSB. Code is set at 10000000 when reset. TTL
interface.
Reference voltage (H level) input pin. VDD is given by internal reference voltage circuit-
ry to this pin when internal reference voltage mode. In this case, the capacitor between
this pin and AG pin is required to limit noise generation. In case of external reference
voltage mode, the reference voltage should be given from this pin.
VR1
VR2
20
21
Analog
Input
Middle point of reference voltage input1pin.
Reference voltage (H level) input pin. ___
VDD is given by internal reference voltage cir-
2
cuitry to this pin when internal reference voltage mode. In this case, the capacitor be-
tween this pin and AG pin is required to limit noise generation. In case of external refer-
ence voltage mode, the reference voltage should be given from this pin.
4
MB86022
(Continued)
System Pin Number Symbol
Descriptions
Analog output pin of channel 3. This pin is set to high–impedance state at Power Down.
Analog output pin of channel 2. This pin is set to high–impedance state at Power Down.
Analog output pin of channel 1. This pin is set to high–impedance state at Power Down.
Analog output pin of channel 0. This pin is set to high–impedance state at Power Down.
No connection pin
16
17
18
19
15
AO3
AO2
AO1
AO0
N.C.
Analog
Output
–
5
MB86022
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Pin Name
Unit
Min
Typ
Max
VDD
Power supply voltage
Digital input voltage
4.75
5.0
5.25
V
VDD
VDI
V1
VDD
3.8
All digital input pins
0
–
V
V
V
VR1
VR2
1.2
3.75
2.5
Analog input voltage
V1+1.2
______
V1+3.8
______
V2
2
2
Analog output load
resistance
kΩ
20
–
–
–
–
RAL
CAL
Ta
AO0, AO1, AO2, AO3
Analog output load
capacitance
–
50
70
pF
°C
Operating temperature
–20
6
MB86022
ELECTRICAL CHARACTERISTICS
(V =4.75V to 5.25V, Ta=–20°C to 70°C)
DD
Value
Parameter
Symbol
Pin Name
Conditions
Unit
Min
Typ
Max
___
PD=“H”
___
PD=“L”
IDD1
IDD2
VIL
–
2.8
5.5
mA
mA
V
No
load
VDD
Power supply current
“L” Voltage
–
0
–
–
0.5
0.8
All digital input pins
VDD
VIH
“H” Voltage
Digital
2.2
–
V
input
µA
µA
µA
VDI=GND
IIL
“L” Current
–10
–10
–100
200
200
–
10
10
–25
–
___
D0 to D7, WR
VDI=VDD
IIH
“H” Current
–
___ ___ ______
PD, CE, RESET
VDI=GND
IPLU
tWHWR
tWLWR
tWLRP
tSD1
tSD2
tSCE
tHD1
tHD2
tHCE
Pull up current
–50
–
___
WR “H” Width
___
WR
___
WR
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
Ref. to timing chart
ns
ns
ns
ns
ns
ns
ns
ns
ns
___
WR “L” Width
–
–
______ ___
RESET, PD
Digital input “L” width
DATA Set up time 1
DATA Set up time 2
500
100
100
0
–
–
___
D0 to D7, WR
___
C0, C1, WR
–
–
–
–
___ ___
CE, WR
___
–
–
CE Set up time
___
D0 to D7, WR
___
C0, C1, WR
DATA Hold time 1
50
50
0
–
–
DATA Hold time 2
–
–
___ ___
CE, WR
___
CE Hold time
–
–
7
MB86022
(Continued)
(V =4.75V to 5.25V, Ta=–20°C to 70°C)
DD
Value
Pin Name
Parameter
Symbol
Conditions
Unit
Min
Typ
Max
___
WR
Ref. to timing chart
Ref. to timing chart
Rising time 1
Falling time 1
0
–
50
ns
ns
tr1
tf1
___
WR
0
0
–
–
50
50
D0 to D7, C0,
___ ______
tr2
Ref. to timing chart
Ref. to timing chart
Rising time 2
ns
ns
C1, CE, RESET,
___
PD
D0 to D7, C0,
___ ______
Falling time 2
Resolution
tf2
0
–
8
50
C1, CE, RESET,
___
PD
Res
–
–
bits
V
No external VR input
V
__D_D_
4
VAOL1
VR1=open
VR2=open
(Typ.) –0.1
(Typ.) +0.1
Input
code
D(A)=
0
Analog output
Min. voltage
AO0,
AO1,
AO2,
AO3
External VR input
VR1=V1
2xV2–V1
(Typ.) –0.1
(Typ.) –0.1
(Typ.) +0.1
(Typ.) +0.1
(Typ.) +0.1
V
V
VAOL2
VR2=V2
No external VR input
VR1=open
383
____
512
VAOH1
x VDD
Input
code
D(A)=
255
VR2=open
Analog output
Max. voltage
External VR input
VR1=V1
V1–V2
_____
128
(Typ.) –0.1 V1 –
V
VAOH2
VR2=V2
VR1,
VR2
Analog input
resistance
kΩ
RI
LE
DLE
tS
30
–1.5
–1
50
–
200
1.5
1
Linearity error
LSB
LSB
µs
AO0,
AO1,
AO2,
AO3
No external VR input
VR1=open
Differential
linearity error
VR2=open
–
Full scale change
(Ref. to timing chart)
Setting time
–
–
5
8
MB86022
FUNCTION DESCRIPTION
TRUTH TABLE
___
PD
______
RESET
___
CE
___
WR
C0, C1
D0 to D7
Function
Power down
Initialization
0
1
1
1
x
0
1
1
x
x
1
0
x
x
x
–
–
–
–
No data input
Data input
–
No analog output change
Analog output change
Channel selectiion
Fig. 1 – DATA SET TIMING DIAGRAM
D0 to D7
C0, C1
___
CE
___
WR
Data is read.
Analog output is changed.
Data is not read.
Analog output is not changed.
9
MB86022
SETTING OF ANALOG OUTPUT VOLTAGE
Data
Analog Output Voltage
VR1=V1
VR1=V1
VR1=Open
D(A) D7 D6 D5 D4 D3 D2 D1 D0
VR2=Open
VR2=V2
VR2=Open
(No external VR input)
(External VR1 input)
(External VR input)
V –V
___1___2
+ V2
VDD
2xV –V
_3_8_3_
512
____1___D_D_
____
x VDD
255
254
253
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
x 127
x 127 +
x 126 +
128
256
2
V –V
___1___2
+ V2
2xV –V
VDD
_3_8_2_
512
____1___D_D_
____
x VDD
x 126
128
256
2
V –V
___1___2
+ V2
_3_8_1_
512
2xV –V
VDD
x VDD
____1___D_D_
____
x 125
x 125 +
128
256
2
2xV –V
_____1___D_Dx (D(A) –128)
V1–V2
______
128
VDD
2
VDD
512
____
____
V2
256
x (D(A)–128) +
x (D(A)–128) +
V
____
DD
+
2
VDD
2xV1–VDD
_________
V1–V2
_2_5_7_
512
____
______
x VDD
+
+ V2
129
128
127
126
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
256
2
128
VDD
VDD
____
____
2
V2
2
2xV1–VDD
VDD
V1–V2
_2_5_5_
512
________
256
______
128
____
2
x VDD
+ V
x (–1) +
x (–2) +
x (–1)
x (–2)
2
V1–V2
2xV –V
____1___D_D
VDD
_2_5_4_
512
______
____
x VDD
+ V
2
128
2
256
2xV –V
VDD
V1–V2
___1___D__D
_1_3_0_
512
____
______
x VDD
+ V
+ V
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
x (–126) +
x (–127) +
x (–126)
x (–127)
2
256
128
2
2xV –V
___1___D__D
VDD
V1–V2
_1_2_9_
512
____
______
x VDD
2
256
128
2
VDD
____
VDD–V1
–(V1–V2) + V2
0
4
2xV1–VDD
________
V1–V2
128
VDD
512
______
____
1LSB
256
* Code is set at ”10000000” when reset mode.
10
MB86022
ANALOG OUTPUT VOLTAGE RANGE
Fig. 2 – ON-CHIP REFERENCE VOLTAGE MODE (NO EXTERNAL VR INPUT)
VDD
VDD
512
____
1LSB
_3_
4
x VDD
_3_8_3_
512
VAOH
V
x
DD
VDD
2
____
D/A Output range
VDD
4
____
VAOL
AG
(VR1=V , VR2=1/2xV
)
1
DD
Fig. 3 – EXTERNAL REFERENCE VOLTAGE MODE
VDD
2 x V1–VDD
__________
1LSB
256
(VR1) V1
2 x V1–VDD
__________
256
VDD
2
____
VAOH
x 127 +
VDD
2
____
D/A Output range
VAOL (VDD–V1)
AG
(VR1=V , VR2=V )
1
2
Fig. 4 – EXTERNAL REFERENCE VOLTAGE MODE
VDD
V1–V2
128
______
1LSB
(VR1) V1
(VR2) V2
_1_2_7_
128
VAOH
(V –V ) + V
2
x
1
2
D/A Output range
VAOL – (V1–V2) + V2
AG
11
MB86022
TYPICAL APPLICATION CIRCUIT FOR EACH MODE
Fig. 5–ON-CHIPREFERENCEVOLTAGEMODE
______
RESET
___
PD
+5V (VDD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
)
+
–
D0 to D7
1µF
+
–
1µF
AO0 to 3
9
C0
C1
10
11
12
N.C.
___
WR
___
CE
(VR1=V , VR2=1/2xV
)
1
DD
Fig. 6 – EXTERNAL REFERENCE VOLTAGE MODE
______
RESET
___
PD
+5V (VDD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
)
+
–
D0 to D7
1µF
V1
AO0 to 3
9
C0
C1
10
11
12
N.C.
___
WR
___
CE
(VR1=V , VR2=V )
1
2
Fig. 7 – EXTERNAL REFERENCE VOLTAGE MODE
______
RESET
___
PD
+5V (VDD
V2
V1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
)
D0 to D7
AO0 to 3
9
C0
C1
10
11
12
N.C.
___
WR
___
CE
12
MB86022
TIMING DIAGRAM
VIH
___
WR
VIL
tr1
tf1
tWHWR
tWLWR
VIH
D0 to D7
VIL
tr2
tf2
tSD1
tHD1
VIH
VIL
C0, C1
tr2
tf2
tSD2
tHD2
VIH
VIL
___
CE
tSCE
tHCE
tf2
tr2
±1LSB
AO0 to AO3
±1LSB
tS
VIH
VIL
______ ___
RESET, PD
tWLRP
13
MB86022
PACKAGE DIMENSIONS
24-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-24P-M03)
15°MAX
INDEX-1
INDEX-2
.300(7.62)
TYP
.260±.010
(6.60±0.25)
+.008
–.012
+0.20
–0.30
1.170
(29.72
)
.010±.002
(0.25±0.05)
+.020
–0
.034
.050(1.27)
MAX
+0.50
–0
(0.86
)
.172(4.36)MAX
.118(3.00)MIN
+.020
–0
.020(0.51)MIN
.100(2.54)
TYP
.050
.018±.003
(0.46±0.08)
+0.50
–0
(1.27
)
Dimensions in
inches (millimeters)
1991 FUJITSU LIMITED D24017S-3C
14
MB86022
24-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-24P-M02)
.110(2.80) MAX
+.010
–.008
+0.25
–0.20
(MOUNTING HEIGHT)
.002(0.05) MIN
.600
(15.24
)
(STAND OFF HEIGHT)
.402±.016
(10.20±0.40)
.362±.012
INDEX
.299±.012
(7.60±0.30)
(9.20±0.30)
.020±.008
(0.50±0.20)
.018±.004
(0.45±0.10)
.050(1.27)
TYP
+.002
–.001
+0.05
–0.02
.005(0.13) M
“A”
.006
(0.15
)
Details of “A” part
.008(0.20)
.024(0.60)
.007(0.18)
MAX
.004(0.10)
.550(13.97) REF
.027(0.68)
MAX
Dimensions in
inches (millimeters)
1991 FUJITSU LIMITED F24008S-4C
All Rights Reserved.
Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical
semiconductor applications. Complete Information sufficient for construction purposes
is not necessarily given.
The Information contained in this document has been carefully checked and is believed
to be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
The Information contained in this document does not convey any license under the
copyrights, patent rights or trademarks claimed and owned by Fujitsu.
Fujitsu reserves the right to change products or specifications without notice.
No part of this publication may be copied or reproduced in any form or by any means, or
transferred to any third party without prior written consent of Fujitsu.
15
MB86022
For further information please contact:
Japan
FUJITSU LIMITED
Electronic Devices
International Operations Department
KAWASAKI PLANT, 1015 Kamikodanaka,
Nakahara–ku, Kawasaki–shi,
Kanagawa 211, Japan
Tel: (044) 754–3753
FAX: (044) 754–3332
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134–1804, USA
Tel: (408) 922–9000
FAX: (408) 432–9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6–10
63303 Dreieich–Buchschlag,
Germany
Tel: (06103) 690–0
FAX: (06103) 690–122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
No. 51 Bras Basah Road,
Plaza By The Park,
#06–04 to #06–07
Singapore 0718
Tel: 336–1600
FAX: 336–1609
I9502
FUJITSU LIMITED Printed in Japan
16
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